Restructured filelists to be explicit to ensure compatibility with lint tools

flist/corstone101_ip.flist

+//-----------------------------------------------------------------------------
+// NanoSoC Corstone-101 Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Arm Corstone-101
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// =============    Corstone-101 search path    =============
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/
+
+// CMSDK APB Timer IP
+//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_timer/verilog
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_timer/verilog/cmsdk_apb_timer.v
+
+// CMSDK Dual Timers IP
+//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_frc.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers.v
+
+// CMSDK APB UART IP
+//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_uart/verilog
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_uart/verilog/cmsdk_apb_uart.v
+
+// CMSDK APB Watchdog IP
+//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_frc.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog.v
+
+// CMSDK APB Slave Mux IP
+//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_slave_mux/verilog
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_slave_mux/verilog/cmsdk_apb_slave_mux.v
+
+// CMSDK APB Subystem Top IP
+//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_subsystem/verilog
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_subsystem/verilog/cmsdk_apb_subsystem.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_subsystem/verilog/cmsdk_apb_test_slave.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_subsystem/verilog/cmsdk_irq_sync.v
+
+// CMSDK AHB Slave Mux IP
+//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_slave_mux/verilog
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_slave_mux/verilog/cmsdk_ahb_slave_mux.v
+
+// CMSDK AHB Default Slave IP
+//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_default_slave/verilog
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_default_slave/verilog/cmsdk_ahb_default_slave.v
+
+// CMSDK AHB GPIO IP
+//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_gpio/verilog
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_gpio/verilog/cmsdk_ahb_gpio.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_gpio/verilog/cmsdk_ahb_to_iop.v
+
+// CMSDK AHB to APB Bridge IP
+//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog/cmsdk_ahb_to_apb.v
+
+// CMSDK IOP to GPIO IP
+//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_iop_gpio/verilog
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_iop_gpio/verilog/cmsdk_iop_gpio.v
+
+// CMSDK Clockgate Models
+//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/clkgate
+// $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/clkgate/cm0_acg_tsmc180.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/clkgate/cm0p_acg_tsmc180.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/clkgate/cm0_pmu_acg_tsmc180.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/clkgate/cm0p_pmu_acg_tsmc180.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/clkgate/cm3_clk_gate_tsmc180.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/clkgate/cm3_etm_clk_gate_tsmc180.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/clkgate/cm4_clk_gate_tsmc180.v
+// $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/clkgate/cm4_etm_clk_gate_tsmc180.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/clkgate/cmsdk_clock_gate.v
+
+// CMSDK Memory Models
+//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_ahb_memory_models_defs.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_ahb_ram_beh.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_ahb_ram.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_ahb_rom.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_flash_rom16.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_flash_rom32.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_fpga_rom.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_fpga_sram.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_sram256x16.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_sram256x8.v
+
+// CMSDK AHB to SRAM bridge IP
+//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_sram/verilog
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_sram/verilog/cmsdk_ahb_to_sram.v
\ No newline at end of file

flist/corstone101_vip.flist

+//-----------------------------------------------------------------------------
+// NanoSoC Corstone-101 VIP Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Arm Corstone-101 VIP
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// =============    DMA-230 search path    =============
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/AhbLitePC/verilog
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/ApbPC/verilog
+
+// CMSDK Debug Tester VIP
+//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog/cmsdk_debug_tester_ahb_interconnect.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog/cmsdk_debug_tester_trace_capture.v
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog/cmsdk_debug_tester.v
+
+// CMSDK AHB Lite Protocol Checker VIP
+//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/AhbLitePC/verilog
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/AhbLitePC/verilog/AhbLitePC.v
+
+// CMSDK APB Protocol Checker VIP
+//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/ApbPC/verilog
+// $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/ApbPC/verilog/ApbPC.v
\ No newline at end of file

flist/nanosoc_busmatrix.flist

+//-----------------------------------------------------------------------------
+// NanoSoC BusMatrix IP Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for NanoSoC IP
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// =============    NanoSoC BusMatrix IP search path    =============
++incdir+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix
+
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_BOOTROM_0.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_DMEM_0.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_H.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_L.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXP.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_IMEM_0.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSIO.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSTABLE.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_default_slave.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_inititator_input.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_CPU_0.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DEBUG.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_0.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_1.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_BOOTROM_0.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_DMEM_0.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_H.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_L.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXP.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_IMEM_0.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSIO.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSTABLE.v
\ No newline at end of file

flist/nanosoc_ip.flist

@@ -16,6 +16,10 @@
 +libext+.v+.vlib
 
 // =============    NanoSoC IP search path    =============
+
+// Include Corstone IP
+-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/corstone101_ip.flist
+
 // NanoSoC Chip Pads Level
 $(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v
 
@@ -34,8 +38,7 @@ $(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_subsystems/systemctrl/verilog/nanosoc
 $(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_subsystems/interconnect/verilog/nanosoc_ss_interconnect.v
 
 // Bus Matrix
-+incdir+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix
--y $(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix
+-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_busmatrix.flist
 
 // NanoSoC Regions - Bootrom
 $(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/bootrom_0/verilog/nanosoc_bootrom_cpu_0.v

makefile

@@ -177,6 +177,7 @@ all_vcs : compile_vcs bootrom debugtester
 
 # ------- XM -----------
 
+	
 # Compile RTL
 compile_xm : bootrom
 	@echo ADP_FILE
@@ -185,6 +186,9 @@ compile_xm : bootrom
 	cd $(SIM_DIR); xmvlog  -work worklib -f xmvlog_sv.args -f xmvlog_ver.args -sv | tee -a compile_xm.log
 	cd $(SIM_DIR); xmelab  -mess -f xmelab.args -access +r | tee -a compile_xm.log
 
+lint_xm: compile_xm
+	cd $(SIM_DIR); hal $(XM_VC_OPTIONS) $(DEFINES_VC)
+	
 # Note : If coverage is required, you can add -coverage all to xmelab
 
 # Run simulation in batch mode

slcorem0_tech @ 3cfcbf34

-Subproject commit 5caa43ffdece4f8634e5f95b6110608f1339bc74
+Subproject commit 3cfcbf349a30c2da2903d33baa35d3e8d3c51fc2

sldma230_tech @ f050e6fd

-Subproject commit 00b54df54e90032aba15d470c6470523bca93d59
+Subproject commit f050e6fd3a8e67511f4974fb54eb6c72576f2614