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SoCLabs
NanoSoC Tech
Commits
d07c6a95
Commit
d07c6a95
authored
May 2, 2023
by
dam1n19
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SOC1-167
: testing verilog defines in tcl
parent
769ea9ba
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system/fpga_imp/scripts/build_mcu_fpga_ip.tcl
+2
-0
2 additions, 0 deletions
system/fpga_imp/scripts/build_mcu_fpga_ip.tcl
system/src/verilog/nanosoc_chip.v
+2
-0
2 additions, 0 deletions
system/src/verilog/nanosoc_chip.v
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0 deletions
system/fpga_imp/scripts/build_mcu_fpga_ip.tcl
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−
0
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d07c6a95
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@@ -57,6 +57,8 @@ source scripts/rtl_source_soclabs_ip.tcl
#source scripts/rtl_source_fpga_ip.tcl
# soclabs modified mcu system
set_property verilog_define
{
NOEXP
}
[
current_fileset
]
set soc_vlog ../src
read_verilog $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix_default_slave.v
read_verilog $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix_lite.v
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system/src/verilog/nanosoc_chip.v
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d07c6a95
...
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@@ -841,6 +841,7 @@ localparam CORTEX_M0 = 1;
// Expansion Region "exp" instance
//----------------------------------------
`ifdef
NOEXP
nanosoc_exp
#(.
ADDRWIDTH
(
29
)
)
u_nanosoc_exp
(
.
HCLK
(
HCLK
),
...
...
@@ -862,6 +863,7 @@ nanosoc_exp #(.ADDRWIDTH(29)
.
ip_data_req
(
exp_ip_req
),
.
op_data_req
(
exp_op_req
)
);
`endif
// soclabs_ahb_aes128_ctrl u_exp_aes128 (
// .ahb_hclk (HCLK),
...
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