diff --git a/system/fpga_imp/scripts/build_mcu_fpga_ip.tcl b/system/fpga_imp/scripts/build_mcu_fpga_ip.tcl index de9a0196153929d8d5262f4b578b70a78c35caaa..0fe9429a3ede28c15ef14a6c518d1cc8155151ca 100644 --- a/system/fpga_imp/scripts/build_mcu_fpga_ip.tcl +++ b/system/fpga_imp/scripts/build_mcu_fpga_ip.tcl @@ -57,6 +57,8 @@ source scripts/rtl_source_soclabs_ip.tcl #source scripts/rtl_source_fpga_ip.tcl # soclabs modified mcu system +set_property verilog_define {NOEXP} [current_fileset] + set soc_vlog ../src read_verilog $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix_default_slave.v read_verilog $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix_lite.v diff --git a/system/src/verilog/nanosoc_chip.v b/system/src/verilog/nanosoc_chip.v index 556ea7c8944fdeda8049fdd0d7c2be06492edab0..b8012b558958674ed7c25eb02b0907184274436b 100644 --- a/system/src/verilog/nanosoc_chip.v +++ b/system/src/verilog/nanosoc_chip.v @@ -841,6 +841,7 @@ localparam CORTEX_M0 = 1; // Expansion Region "exp" instance //---------------------------------------- +`ifdef NOEXP nanosoc_exp #(.ADDRWIDTH(29) ) u_nanosoc_exp ( .HCLK (HCLK), @@ -862,6 +863,7 @@ nanosoc_exp #(.ADDRWIDTH(29) .ip_data_req (exp_ip_req), .op_data_req (exp_op_req) ); +`endif // soclabs_ahb_aes128_ctrl u_exp_aes128 ( // .ahb_hclk (HCLK),