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Commit cb7b26aa authored by dam1n19's avatar dam1n19
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Changed Incdir syntax in filelists and started writing blackbox waivers for Arm IP

parent d0ddcf03
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1 merge request!1changed imem to rom to allow initial program loading, updated bootloader code...
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flist/corstone101_ip.flist
+ 3
− 14
View file @ cb7b26aa
......@@ -16,9 +16,9 @@
+libext+.v+.vlib
// ============= Corstone-101 search path =============
+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog
+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog
+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/
-incdir $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog
-incdir $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog
-incdir $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/
// CMSDK APB Timer IP
//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_timer/verilog
......@@ -26,7 +26,6 @@ $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_timer/verilog/cmsdk
// CMSDK Dual Timers IP
//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_frc.v
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers.v
......@@ -36,7 +35,6 @@ $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_uart/verilog/cmsdk_
// CMSDK APB Watchdog IP
//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_frc.v
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog.v
......@@ -73,19 +71,10 @@ $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_iop_gpio/verilog/cmsdk_
// CMSDK Clockgate Models
//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/clkgate
// $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/clkgate/cm0_acg_tsmc180.v
// $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/clkgate/cm0p_acg_tsmc180.v
// $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/clkgate/cm0_pmu_acg_tsmc180.v
// $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/clkgate/cm0p_pmu_acg_tsmc180.v
// $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/clkgate/cm3_clk_gate_tsmc180.v
// $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/clkgate/cm3_etm_clk_gate_tsmc180.v
// $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/clkgate/cm4_clk_gate_tsmc180.v
// $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/clkgate/cm4_etm_clk_gate_tsmc180.v
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/clkgate/cmsdk_clock_gate.v
// CMSDK Memory Models
//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_ahb_memory_models_defs.v
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_ahb_ram_beh.v
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_ahb_ram.v
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_ahb_rom.v
......
flist/corstone101_vip.flist
+ 3
− 3
View file @ cb7b26aa
......@@ -16,9 +16,9 @@
+libext+.v+.vlib
// ============= DMA-230 search path =============
+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog
+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/AhbLitePC/verilog
+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/ApbPC/verilog
-incdir $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog
-incdir $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/AhbLitePC/verilog
-incdir $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/ApbPC/verilog
// CMSDK Debug Tester VIP
//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog
......
flist/nanosoc_busmatrix.flist
+ 1
− 1
View file @ cb7b26aa
......@@ -16,7 +16,7 @@
+libext+.v+.vlib
// ============= NanoSoC BusMatrix IP search path =============
+incdir+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix
-incdir $(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix
$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_BOOTROM_0.v
$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_DMEM_0.v
......
lint/corstone101_ip.bb 0 → 100644
+ 60
− 0
View file @ cb7b26aa
//-----------------------------------------------------------------------------
// NanoSoC Corstone-101 Blackbox Lint Design Info File
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : HAL Design Info File for Blackboxing Arm IP
//-----------------------------------------------------------------------------
bb_list
{
// Exclude APB Timer as Arm IP
designunit = cmsdk_apb_timer;
file = $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_apb_timer/verilog/cmsdk_apb_timer.v;
// Exclude APB Dual Timer as Arm IP
designunit = cmsdk_apb_dualtimers;
file = $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers.v;
// Exclude APB UART as Arm IP
designunit = cmsdk_apb_uart;
file = $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_apb_uart/verilog/cmsdk_apb_uart.v;
// Exclude APB Watchdog as Arm IP
designunit = cmsdk_apb_watchdog;
file = $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog.v;
// Exclude AHB Slave Mux as Arm IP
designunit = cmsdk_ahb_slave_mux;
file = $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_ahb_slave_mux/verilog/cmsdk_ahb_slave_mux.v;
// Exclude AHB Default Slave as Arm IP
designunit = cmsdk_ahb_default_slave;
file = $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_ahb_default_slave/verilog/cmsdk_ahb_default_slave.v;
// Exclude AHB GPIO as Arm IP
designunit = cmsdk_ahb_gpio;
file = $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_ahb_gpio/verilog/cmsdk_ahb_gpio.v;
// Exclude AHB to APB Bridge as Arm IP
designunit = cmsdk_ahb_to_apb;
file = $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog/cmsdk_ahb_to_apb.v;
// Exclude IOP to GPIO Bridge as Arm IP
designunit = cmsdk_iop_gpio;
file = $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_iop_gpio/verilog/cmsdk_iop_gpio.v;
// Exclude AHB to SRAM Bridge as Arm IP
designunit = cmsdk_ahb_to_sram;
file = $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_ahb_to_sram/verilog/cmsdk_ahb_to_sram.v;
// Exclude SRAM Model as Arm IP
designunit = cmsdk_fpga_sram;
file = $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/models/memories/cmsdk_fpga_sram.v;
}
\ No newline at end of file
lint/nanosoc_ip.bb 0 → 100644
+ 20
− 0
View file @ cb7b26aa
//-----------------------------------------------------------------------------
// NanoSoC Blackbox Lint Design Info File
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : HAL Design Info File for Blackboxing NanoSoC IP Generated from Arm Scripts
//-----------------------------------------------------------------------------
bb_list
{
// Exclude Bus Matrix as Generated from Arm IP
designunit = nanosoc_busmatrix_lite;
file = $SOCLABS_NANOSOC_TECH_DIR/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v;
}
\ No newline at end of file
makefile
+ 6
− 1
View file @ cb7b26aa
......@@ -102,6 +102,9 @@ SIM_TOP_DIR ?= $(SOCLABS_PROJECT_DIR)/simulate/sim
SIM_DIR = $(SIM_TOP_DIR)/$(TESTNAME)
LINT_DIR = $(SOCLABS_PROJECT_DIR)/lint/nanosoc
LINT_INFO_DIR = $(SOCLABS_NANOSOC_TECH_DIR)/lint
# MTI option
#DF#MTI_OPTIONS = -novopt
MTI_OPTIONS = -suppress 2892
......@@ -187,7 +190,9 @@ compile_xm : bootrom
cd $(SIM_DIR); xmelab -mess -f xmelab.args -access +r | tee -a compile_xm.log
lint_xm: compile_xm
cd $(SIM_DIR); hal $(XM_VC_OPTIONS) $(DEFINES_VC)
@rm -rf $(LINT_DIR)
@mkdir -p $(LINT_DIR)
cd $(LINT_DIR); hal $(XM_VC_OPTIONS) $(DEFINES_VC) +debug -XMVERILOGARGS "-timescale 1ps/1ps" -top nanosoc_chip -design_info $(LINT_INFO_DIR)/nanosoc_ip.bb -design_info $(LINT_INFO_DIR)/corstone101_ip.bb
# Note : If coverage is required, you can add -coverage all to xmelab
......
slcorem0_tech @ d739e768
Compare 3cfcbf34...d739e768
Subproject commit 3cfcbf349a30c2da2903d33baa35d3e8d3c51fc2
Subproject commit d739e768c05b22987c06f3f86495890307fe480e
sldma230_tech @ 7df15848
Compare f050e6fd...7df15848
Subproject commit f050e6fd3a8e67511f4974fb54eb6c72576f2614
Subproject commit 7df15848c5c99720fa1853706ef76b1caef29ab0
verif/verilog/nanosoc_tb.v
+ 4
− 4
View file @ cb7b26aa
......@@ -82,11 +82,11 @@ module nanosoc_tb;
localparam BE=0;
`define ARM_CMSDK_INCLUDE_DEBUG_TESTER 1
`ifdef ADP_FILE
localparam ADP_FILENAME=`ADP_FILE;
`else
// `ifdef ADP_FILE
// localparam ADP_FILENAME=`ADP_FILE;
// `else
localparam ADP_FILENAME="adp.cmd";
`endif
// `endif
SROM_Ax32
......
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