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Commit c2b315e0 authored by Daniel Newbrook's avatar Daniel Newbrook
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First version DMA350_tests

parent 14c4fc8e
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1 merge request!2Feat dma350 merge into main
......@@ -4,7 +4,7 @@
Top build a NanoSoC System, additional Arm Licensed IP is required. The IP that is requried is the following:
- Arm Cortex-M0
- Arm Corstone-101
- Arm DMA-230 (PL230)
- Arm DMA-230 (PL230) OR Arm DMA-350
If you are unable to license the Cortex-M0, you may be able to get access to the Arm Cortex-M0 designstart which contains an obfuscated version of the Cortex-M0 processor along with the CMSDK (which is also included in the Corstone-101 subsystem).
......
#include "CMSDK_CM0.h"
#include <stdio.h>
#include "uart_stdout.h"
#include "config_id.h"
#include <string.h>
#include <inttypes.h>
#include "dma_350_command_lib.h"
//Channel number defines
// Note: Please add more channels if DMA has more than 8 channels
#define CH0 0
#define CH1 1
#define CH2 2
#define CH3 3
#define CH4 4
#define CH5 5
#define CH6 6
#define CH7 7
// Note: Please modify the addresses according to the system memory map
#define COPY_ADDR_SRC 0x80000000
#define COPY_ADDR_DST 0x90000000
#define COPY_ADDR_SRC_M1 0x88000000
#define COPY_ADDR_DST_M1 0x98000000
// Note: Please modify to the desired data size
#define DATA_SIZE 256
#define LARGE_DATA_SIZE 10000
// Note: Please modify to the desired boot settings
#define DMA_BOOT_ADDR 0x10000000
// Privileged mode enabled and disabled
// Note: Please modify according to your system
#define EnablePrivilegedMode() __asm("SVC #0")
#define DisablePrivilegedMode() __asm("SVC #1")
#define HW32_REG(ADDRESS) (*((volatile unsigned long *)(ADDRESS)))
#if defined ( __CC_ARM )
__asm void address_test_write(unsigned int addr, unsigned int wdata);
__asm unsigned int address_test_read(unsigned int addr);
#else
void address_test_write(unsigned int addr, unsigned int wdata);
unsigned int address_test_read(unsigned int addr);
#endif
//typedef unsigned long int uintptr_t;
// Array for command with a Header + 5 modified registers
uint32_t LinkCmd[6];
// Variable to store the address of the above array
uintptr_t LinkCmd_adr = (uintptr_t) LinkCmd;
void SystemInitialization(void);
int main(void) {
// Get the number of channels and trigger interfaces
uint32_t ch_num;
uint32_t trig_in_num;
uint32_t trig_out_num;
unsigned int actual_addr;
// Call Function for the testbench Specific Initialization
// Note: Change to the system specific function for initialization
SystemInitialization();
printf("<--- DMA START --->\n");
// Define structures for the tests
// Note: Command and channel parameters can be modified to the desired settings
// Set the DMA channel related parameters
// Channel Priority is '0' - Lowest Priority
// Cleaning DMA Channel registers at the end of the command is enabled
// Reloading initial register values at the end of the command is disabled
// STATUS_DONE status flag is asserted at the end of the command.
// Automatic pause request at the end of the command is disabled
// Maximum source and destination burst lengths sent by the DMA are 15+1=16 (Can be limited by FIFO size)
AdaChannelSettingsType ch_settings = {
.CHPRIO = 0,
.CLEARCMD = 1,
.REGRELOADTYPE = RELOAD_DISABLED,
.DONETYPE = DONETYPE_EOF_CMD,
.DONEPAUSEEN = 0,
.SRCMAXBURSTLEN = 15,
.DESMAXBURSTLEN = 15
};
AdaChannelSettingsType ch_settings_no_burst = {
.CHPRIO = 0,
.CLEARCMD = 1,
.REGRELOADTYPE = RELOAD_DISABLED,
.DONETYPE = DONETYPE_EOF_CMD,
.DONEPAUSEEN = 0,
.SRCMAXBURSTLEN = 0,
.DESMAXBURSTLEN = 0
};
// Set the attributes of the read AXI transactions sent by the DMA
// These settings affects the ARINNER[3:0], AWINNER[3:0], ARCACHE[3:0], AWCACHE[3:0] and AxDOMAIN[1:0] attributes
// of the AXI transactions
// This command uses Normal memory, Non-Cacheable, Bufferable, System-shareable AXI attributes
// ARINNER[3:0] = 4'b0011, AWINNER[3:0] = 4'b0011, ARCACHE[3:0] = 4'b0011, AWCACHE[3:0] = 4'b0011, AxDOMAIN[1:0] = 2'b11
// More information about the AXI attribute settings can be found in the TRM
// The command uses non-secure, non-privileged AXI read transactions
AdaChannelSrcAttrType ch_srcattr = {
.SRCMEMATTRLO = 4,
.SRCMEMATTRHI = 4,
.SRCSHAREATTR = 0,
.SRCNONSECATTR = 1,
.SRCPRIVATTR = 0
};
// Set the attributes of the write AXI transactions sent by the DMA
// These settings affects the ARINNER[3:0], AWINNER[3:0], ARCACHE[3:0], AWCACHE[3:0] and AxDOMAIN[1:0] attributes
// of the AXI transactions
// This command uses Normal memory, Non-Cacheable, Bufferable, System-shareable AXI attributes
// ARINNER[3:0] = 4'b0011, AWINNER[3:0] = 4'b0011, ARCACHE[3:0] = 4'b0011, AWCACHE[3:0] = 4'b0011, AxDOMAIN[1:0] = 2'b11
// More information about the AXI attribute settings can be found in the TRM
// The command uses non-secure, non-privileged AXI write transactions
AdaChannelDesAttrType ch_desattr = {
.DESMEMATTRLO = 4,
.DESMEMATTRHI = 4,
.DESSHAREATTR = 0,
.DESNONSECATTR = 1,
.DESPRIVATTR = 0
};
// Set the attributes of the read AXI transactions used for the command link related transfers
AdaChannelLinkAttrType ch_linkattr = {
.LINKMEMATTRLO = 4,
.LINKMEMATTRHI = 4,
.LINKSHAREATTR = 0
};
// Set the basic command parameters
// The command uses the defined COPY_ADDR_M0 as source address, COPY_ADDR_M1 as destination address
// the defined DATA_SIZE as source and destination data (X)size and 32 bit transaction size
AdaBaseCommandType command_base = {
.SRCADDR = COPY_ADDR_SRC, // Read from M0 interface
.DESADDR = COPY_ADDR_DST, // Write to M0 interface
.SRCXSIZE = DATA_SIZE,
.DESXSIZE = DATA_SIZE,
.TRANSIZE = BITS_32
};
AdaBaseCommandType command_base_alias = {
.SRCADDR = COPY_ADDR_SRC_M1, // Read from M1 interface
.DESADDR = COPY_ADDR_DST_M1, // Write to M1 interface
.SRCXSIZE = DATA_SIZE,
.DESXSIZE = DATA_SIZE,
.TRANSIZE = BITS_32
};
AdaBaseCommandType str_command_base = {
.SRCADDR = COPY_ADDR_SRC, // Read from M0 interface
.DESADDR = COPY_ADDR_DST, // Write to M1 interface
.SRCXSIZE = DATA_SIZE,
.DESXSIZE = 0,
.TRANSIZE = BITS_32
};
// Set the increment of source and destination addresses
// The source and destination address increments are 1
Ada1DIncrCommandType command_1d_incr = {
.SRCXADDRINC = 1, // Autoincrement by transaction size
.DESXADDRINC = 1 // Autoincrement by transaction size
};
// Set the transfer types (2D and wrapping support)
// The transaction type is 1D basic transfer
AdaWrapCommandType command_1d_wrap = {
.FILLVAL = 0,
.XTYPE = OPTYPE_CONTINUE,
.YTYPE = OPTYPE_DISABLE
};
// Set the transfer types (2D and wrapping support)
// 2D transfer - not used in the testbench, only an example
AdaWrapCommandType command_2d_wrap = {
.FILLVAL = 0,
.XTYPE = OPTYPE_CONTINUE,
.YTYPE = OPTYPE_CONTINUE
};
// Set the 2D transfer parameters
// 32 words * 16 lines -> 32 words * 16 lines
// It is not used in the testbench, only an example
Ada2DCommandType command_2d = {
.SRCYSIZE = 16,
.DESYSIZE = 16,
.SRCYADDRSTRIDE = 64,
.DESYADDRSTRIDE = 64
};
// Enable/disable the interupts of the channel
// Error and done interrupts are enabled
AdaIrqEnType ch_irqs = {
.INTREN_DONE = 1,
.INTREN_ERR = 1,
.INTREN_DISABLED = 0,
.INTREN_STOPPED = 0
};
// Set Trigger input 0
// Trigger input is used for Channel 0 as external hardware trigger in command trigger mode
AdaTrigInType command_trig_in = {
.USETRIGIN = 1,
.TRIGINSEL = 0,
.TRIGINTYPE = TRIGTYPE_HW_EXTERNAL,
.TRIGINMODE = TRIGINMODE_CMD,
.TRIGINBLKSIZE = 0
};
// Example for DMA flow control trigger
// Trigger input is used for Channel 0 as external hardware trigger in DMA flow control trigger mode
// and and the transfer size per trigger is 7+1=8
// It is not used in the testbench, only an example
AdaTrigInType command_trig_in_flow_cntrl = {
.USETRIGIN = 1,
.TRIGINSEL = 0,
.TRIGINTYPE = TRIGTYPE_HW_EXTERNAL,
.TRIGINMODE = TRIGINMODE_DMA_FLW,
.TRIGINBLKSIZE = 7
};
// Set Trigger Output 0
// Trigger output is used for Channel 0 as hardware trigger
AdaTrigOutType command_trig_out = {
.USETRIGOUT = 1,
.TRIGOUTSEL = 0,
.TRIGOUTTYPE = TRIGOUTTYPE_HW
};
// Set stream type
// Both stream in and out interfaces are used
AdaStreamType command_stream = {
.STREAMTYPE = OUT_ONLY
} ;
//Initialize TCM
printf("Initialize SRAM: \n");
actual_addr = command_base.SRCADDR;
unsigned int test_data[command_base.SRCXSIZE];
int j;
for(j = 0; j < 64; j++){
test_data[j] = j;
address_test_write(actual_addr,test_data[j]);
//printf("Written data: 0x%x to address 0x%x \n", test_data[j], actual_addr);
actual_addr = actual_addr+4;
}
for(j = 0; j < 64; j++){
test_data[j] = j;
address_test_write(actual_addr,test_data[j]);
//printf("Written data: 0x%x to address 0x%x \n", test_data[j], actual_addr);
actual_addr = actual_addr+4;
}
for(j = 0; j < 64; j++){
test_data[j] = j;
address_test_write(actual_addr,test_data[j]);
//printf("Written data: 0x%x to address 0x%x \n", test_data[j], actual_addr);
actual_addr = actual_addr+4;
}
for(j = 0; j < 64; j++){
test_data[j] = j;
address_test_write(actual_addr,test_data[j]);
//printf("Written data: 0x%x to address 0x%x \n", test_data[j], actual_addr);
actual_addr = actual_addr+4;
}
//Get the configuration information
ch_num = AdaGetChNum(SECURE);
trig_in_num = AdaGetTrigInNum(SECURE);
trig_out_num = AdaGetTrigOutNum(SECURE);
//Display the config parameters read
printf("Number of DMA channels: %d \n", ch_num);
printf("Number of DMA trigger inputs: %d \n", trig_in_num);
printf("Number of DMA trigger outputs: %d \n", trig_out_num);
printf("---STARTING 1D Command Tests No interrupts---\n");
// **********************************************************************************************
// Stage #1: Copy data from COPY_ADDR_SRC to COPY_ADDR_DST using all channels
// Simple 1D command with no interrupts
// **********************************************************************************************
printf("Test BURST with 1D basic commands from COPY_ADDR_SRC to COPY_ADDR_DST...\n");
for (uint32_t ch=0; ch < ch_num; ch++) {
//
// Write all settings to the DMA registers
AdaChannelInit(ch_settings, ch_srcattr, ch_desattr, ch, SECURE);
Ada1DIncrCommand(command_base, command_1d_incr, ch, SECURE);
SetAdaWrapRegs(command_1d_wrap, ch, SECURE);
//AdaSetIntEn(ch_irqs, ch, SECURE);
printf("DMA %d configured. Starting the transfer.\n", ch);
// Start DMA operation and wait for done IRQ
AdaEnable(ch, SECURE);
uint8_t ch_enabled = 1;
while (ch_enabled == 1) {
ch_enabled = AdaGetEnable(ch, SECURE);
}
printf("DMA transfer finished\n");
}
// **********************************************************************************************
// Stage #2: Copy data from COPY_ADDR_SRC to COPY_ADDR_DST using all channels
// Simple 1D command with no interrupts
// **********************************************************************************************
printf("Test NO BURST with 1D basic commands from COPY_ADDR_SRC to COPY_ADDR_DST...\n");
for (uint32_t ch=0; ch < ch_num; ch++) {
//
// Write all settings to the DMA registers
AdaChannelInit(ch_settings_no_burst, ch_srcattr, ch_desattr, ch, SECURE);
Ada1DIncrCommand(command_base, command_1d_incr, ch, SECURE);
SetAdaWrapRegs(command_1d_wrap, ch, SECURE);
//AdaSetIntEn(ch_irqs, ch, SECURE);
printf("DMA %d configured. Starting the transfer.\n", ch);
// Start DMA operation and wait for done IRQ
AdaEnable(ch, SECURE);
uint8_t ch_enabled = 1;
while (ch_enabled == 1) {
ch_enabled = AdaGetEnable(ch, SECURE);
}
printf("DMA transfer finished\n");
}
printf("Test Stream interface with 1D basic commands from COPY_ADDR_SRC to COPY_ADDR_DST...\n");
for (uint32_t ch=0; ch < ch_num; ch++) {
//
// Write all settings to the DMA registers
AdaChannelInit(ch_settings, ch_srcattr, ch_desattr, ch, SECURE);
Ada1DIncrCommand(str_command_base, command_1d_incr, ch, SECURE);
SetAdaWrapRegs(command_1d_wrap, ch, SECURE);
//AdaSetIntEn(ch_irqs, ch, SECURE);
AdaStreamInit(command_stream, ch, SECURE);
AdaStreamEnable(1, ch, SECURE);
printf("DMA %d configured. Starting the transfer.\n", ch);
// Start DMA operation and wait for done IRQ
AdaEnable(ch, SECURE);
uint8_t ch_enabled = 1;
while (ch_enabled == 1) {
ch_enabled = AdaGetEnable(ch, SECURE);
}
printf("DMA transfer finished\n");
}
printf("Test NO BURST with 1D basic commands using M1 interface...\n");
for (uint32_t ch=0; ch < ch_num; ch++) {
//
// Write all settings to the DMA registers
AdaChannelInit(ch_settings_no_burst, ch_srcattr, ch_desattr, ch, SECURE);
Ada1DIncrCommand(command_base_alias, command_1d_incr, ch, SECURE);
SetAdaWrapRegs(command_1d_wrap, ch, SECURE);
//AdaSetIntEn(ch_irqs, ch, SECURE);
printf("DMA %d configured. Starting the transfer.\n", ch);
// Start DMA operation and wait for done IRQ
AdaEnable(ch, SECURE);
uint8_t ch_enabled = 1;
while (ch_enabled == 1) {
ch_enabled = AdaGetEnable(ch, SECURE);
}
printf("DMA transfer finished\n");
}
UartEndSimulation();
return 0;
}
// Setup all components in the system
void SystemInitialization(void){
// Initialize the system. For example clock gating, PPU, SAU, security components, peripherals etc.
// Note: This function should setup all system components
// UART init
UartStdOutInit();
// Test banner message and revision number
puts("\nCortex Microcontroller System Design Kit - DMA Test - revision $Revision: 371321 $\n");
}
#if defined ( __CC_ARM )
/* Test function for write - for ARM / Keil */
__asm void address_test_write(unsigned int addr, unsigned int wdata)
{
STR R1,[R0]
DSB ; Ensure bus fault occurred before leaving this subroutine
BX LR
}
#else
/* Test function for write - for gcc */
void address_test_write(unsigned int addr, unsigned int wdata) __attribute__((naked));
void address_test_write(unsigned int addr, unsigned int wdata)
{
__asm(" str r1,[r0]\n"
" dsb \n"
" bx lr \n"
);
}
#endif
/* Test function for read */
#if defined ( __CC_ARM )
/* Test function for read - for ARM / Keil */
__asm unsigned int address_test_read(unsigned int addr)
{
LDR R1,[R0]
DSB ; Ensure bus fault occurred before leaving this subroutine
MOVS R0, R1
BX LR
}
#else
/* Test function for read - for gcc */
unsigned int address_test_read(unsigned int addr) __attribute__((naked));
unsigned int address_test_read(unsigned int addr)
{
__asm(" ldr r1,[r0]\n"
" dsb \n"
" movs r0, r1 \n"
" bx lr \n"
);
}
#endif
\ No newline at end of file
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#-----------------------------------------------------------------------------
# The confidential and proprietary information contained in this file may
# only be used by a person authorised under and to the extent permitted
# by a subsisting licensing agreement from Arm Limited or its affiliates.
#
# (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
# ALL RIGHTS RESERVED
#
# This entire notice must be reproduced on all copies of this file
# and copies of this file may only be made by a person if such person is
# permitted to do so under the terms of a subsisting license agreement
# from Arm Limited or its affiliates.
#
# SVN Information
#
# Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
#
# Revision : $Revision: 371321 $
#
# Release Information : Cortex-M System Design Kit-r1p1-00rel0
#-----------------------------------------------------------------------------
#
# Cortex-M System Design Kit software compilation make file
#
#-----------------------------------------------------------------------------
#
# Configurations
#
# Choose the core instantiated, can be
# - CORTEX_M0
# - CORTEX_M0PLUS
CPU_PRODUCT = CORTEX_M0
# Shared software directory
SOFTWARE_DIR = $(SOCLABS_NANOSOC_TECH_DIR)/software
CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
GENERIC_DIR = ../generic
ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0plus
else
DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0
endif
# Program file
TESTNAME = dma350_tests
# Endian Option
COMPILE_BIGEND = 0
# Configuration
ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
USER_DEFINE = -DCORTEX_M0PLUS
else
USER_DEFINE = -DCORTEX_M0
endif
DEPS_LIST = makefile
# Tool chain : ds5 / gcc / keil
TOOL_CHAIN = ds5
ifeq ($(TOOL_CHAIN),ds5)
ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
CPU_TYPE = --cpu Cortex-M0plus
else
CPU_TYPE = --cpu Cortex-M0
endif
endif
ifeq ($(TOOL_CHAIN),gcc)
ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
CPU_TYPE = -mcpu=cortex-m0plus
else
CPU_TYPE = -mcpu=cortex-m0
endif
endif
# Startup code directory for DS-5
ifeq ($(TOOL_CHAIN),ds5)
STARTUP_DIR = $(DEVICE_DIR)/Source/ARM
endif
# Startup code directory for gcc
ifeq ($(TOOL_CHAIN),gcc)
STARTUP_DIR = $(DEVICE_DIR)/Source/GCC
endif
ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
STARTUP_FILE = startup_CMSDK_CM0plus
SYSTEM_FILE = system_CMSDK_CM0plus
else
STARTUP_FILE = startup_CMSDK_CM0
SYSTEM_FILE = system_CMSDK_CM0
endif
# Configuration ID values
GENERIC_FILE = $(GENERIC_DIR)/config_id.h
# ---------------------------------------------------------------------------------------
# DS-5 options
# MicroLIB option
COMPILE_MICROLIB = 0
# Small Multiply (Cortex-M0/M0+ has small multiplier option)
COMPILE_SMALLMUL = 0
ARM_CC_OPTIONS = -c --c99 -O3 -Ospace -I $(DEVICE_DIR)/Include -I $(CORE_DIR) -I $(GENERIC_DIR) \
-I $(SOFTWARE_DIR)/common/retarget -I $(SOFTWARE_DIR)/drivers $(USER_DEFINE)
ARM_ASM_OPTIONS =
ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
--no_debug --rw_base 0x30000000 --ro_base 0x00000000 --map --info sizes
ifeq ($(COMPILE_BIGEND),1)
# Big Endian
ARM_CC_OPTIONS += --bigend
ARM_ASM_OPTIONS += --bigend
ARM_LINK_OPTIONS += --be8
endif
ifeq ($(COMPILE_MICROLIB),1)
# MicroLIB
ARM_CC_OPTIONS += --library_type=microlib
ARM_ASM_OPTIONS += --library_type=microlib --pd "__MICROLIB SETA 1"
ARM_LINK_OPTIONS += --library_type=microlib
endif
ifeq ($(COMPILE_SMALLMUL),1)
# In Cortex-M0, small multiply takes 32 cycles
ARM_CC_OPTIONS += --multiply_latency=32
endif
# ---------------------------------------------------------------------------------------
# gcc options
GNG_CC = arm-none-eabi-gcc
GNU_OBJDUMP = arm-none-eabi-objdump
GNU_OBJCOPY = arm-none-eabi-objcopy
LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts
LINKER_SCRIPT = $(LINKER_SCRIPT_PATH)/cmsdk_cm0.ld
GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE)
ifeq ($(COMPILE_BIGEND),1)
# Big Endian
GNU_CC_FLAGS += -mbig-endian
endif
# ---------------------------------------------------------------------------------------
all: all_$(TOOL_CHAIN)
# ---------------------------------------------------------------------------------------
# DS-5
all_ds5 : $(TESTNAME).hex $(TESTNAME).lst
$(TESTNAME).o : $(SOFTWARE_DIR)/common/validation/$(TESTNAME).c $(GENERIC_FILE) $(DEPS_LIST)
armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
dma_350_driver.o : $(SOFTWARE_DIR)/drivers/dma_350_command_lib.c $(DEPS_LIST)
armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
$(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST)
armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
retarget.o : $(SOFTWARE_DIR)/common/retarget/retarget.c $(DEPS_LIST)
armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
uart_stdout.o : $(SOFTWARE_DIR)/common/retarget/uart_stdout.c $(DEPS_LIST)
armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
$(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST)
armasm $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o $@
$(TESTNAME).ELF : $(TESTNAME).o dma_350_driver.o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
armlink $(ARM_LINK_OPTIONS) -o $@ $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o dma_350_driver.o
$(TESTNAME).hex : $(TESTNAME).ELF
fromelf --vhx --8x1 $< --output $@
$(TESTNAME).lst : $(TESTNAME).ELF
fromelf -c -d -e -s -z -v $< --output $@
# ---------------------------------------------------------------------------------------
# gcc
all_gcc:
$(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \
$(TESTNAME).c \
$(SOFTWARE_DIR)/common/retarget/retarget.c \
$(SOFTWARE_DIR)/common/retarget/uart_stdout.c \
$(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \
-I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
-I $(SOFTWARE_DIR)/common/retarget \
-I $(SOFTWARE_DIR)/drivers \
-L $(LINKER_SCRIPT_PATH) \
-D__STACK_SIZE=0x200 \
-D__HEAP_SIZE=0x1000 \
$(USER_DEFINE) -T $(LINKER_SCRIPT) -o $(TESTNAME).o
# Generate disassembly code
$(GNU_OBJDUMP) -S $(TESTNAME).o > $(TESTNAME).lst
# Generate binary file
$(GNU_OBJCOPY) -S $(TESTNAME).o -O binary $(TESTNAME).bin
# Generate hex file
$(GNU_OBJCOPY) -S $(TESTNAME).o -O verilog $(TESTNAME).hex
# Note:
# If the version of object copy you are using does not support verilog hex file output,
# you can generate the hex file from binary file using the following command
# od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
# ---------------------------------------------------------------------------------------
# Keil MDK
all_keil:
@echo "Please compile your project code and press ENTER when ready"
@read dummy
# ---------------------------------------------------------------------------------------
# Binary
all_bin: $(TESTNAME).bin
# Generate hex file from binary
od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
# ---------------------------------------------------------------------------------------
# Clean
clean :
@rm -rf *.o
@if [ -e $(TESTNAME).hex ] ; then \
rm -rf $(TESTNAME).hex ; \
fi
@if [ -e $(TESTNAME).lst ] ; then \
rm -rf $(TESTNAME).lst ; \
fi
@if [ -e $(TESTNAME).ELF ] ; then \
rm -rf $(TESTNAME).ELF ; \
fi
@if [ -e $(TESTNAME).bin ] ; then \
rm -rf $(TESTNAME).bin ; \
fi
@rm -rf *.crf
@rm -rf *.plg
@rm -rf *.tra
@rm -rf *.htm
@rm -rf *.map
@rm -rf *.dep
@rm -rf *.d
@rm -rf *.lnp
@rm -rf *.bak
@rm -rf *.lst
@rm -rf *.axf
@rm -rf *.sct
@rm -rf *.__i
@rm -rf *._ia
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