Skip to content
Snippets Groups Projects
Commit 14c4fc8e authored by Daniel Newbrook's avatar Daniel Newbrook
Browse files

Add dma350 AHB APB STREAM and trig

parent 33cd9cfd
Branches
Tags
1 merge request!2Feat dma350 merge into main
......@@ -7,3 +7,6 @@
[submodule "nanosoc/slcorem0_tech"]
path = nanosoc/slcorem0_tech
url = https://git.soton.ac.uk/soclabs/slcorem0_tech.git
[submodule "nanosoc/sldma350_tech"]
path = nanosoc/sldma350_tech
url = https://git.soton.ac.uk/soclabs/sldma350_tech.git
......@@ -5,6 +5,7 @@
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
// Daniel Newbrook (d.newbrook@soton.ac.uk)
//
// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
......@@ -30,4 +31,5 @@
-f $(SOCLABS_SOCDEBUG_TECH_DIR)/flist/socdebug.flist
// DMAC IP
-f $(SOCLABS_SLDMA350_TECH_DIR)/flist/sldma350_ahb.flist
-f $(SOCLABS_SLDMA230_TECH_DIR)/flist/sldma230_ip.flist
......@@ -84,7 +84,7 @@ else
ARM_CORSTONE_101_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical
ARM_CORTEX_M0_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical
TB_TOP ?= nanosoc_tb
NANOSOC_DEFINES += DMAC_0_PL230
NANOSOC_DEFINES += DMAC_DMA350
endif
endif
......
......@@ -8,6 +8,7 @@
//
// Copyright 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
`include "gen_defines.v"
module nanosoc_region_exp #(
parameter SYS_ADDR_W = 32, // System Address Width
......@@ -29,6 +30,34 @@ module nanosoc_region_exp #(
output wire HREADYOUT,
output wire HRESP,
output wire [SYS_DATA_W-1:0] HRDATA,
// DMAC Stream interfaces
`ifdef DMAC_DMA350
input wire EXP_STR_IN_0_TVALID,
output wire EXP_STR_IN_0_TREADY,
input wire [SYS_DATA_W-1:0] EXP_STR_IN_0_TDATA,
input wire [3:0] EXP_STR_IN_0_TSTRB,
input wire EXP_STR_IN_0_TLAST,
output wire EXP_STR_OUT_0_TVALID,
input wire EXP_STR_OUT_0_TREADY,
output wire [SYS_DATA_W-1:0] EXP_STR_OUT_0_TDATA,
output wire [3:0] EXP_STR_OUT_0_TSTRB,
output wire EXP_STR_OUT_0_TLAST,
input wire EXP_STR_OUT_0_FLUSH,
input wire EXP_STR_IN_1_TVALID,
output wire EXP_STR_IN_1_TREADY,
input wire [SYS_DATA_W-1:0] EXP_STR_IN_1_TDATA,
input wire [3:0] EXP_STR_IN_1_TSTRB,
input wire EXP_STR_IN_1_TLAST,
output wire EXP_STR_OUT_1_TVALID,
input wire EXP_STR_OUT_1_TREADY,
output wire [SYS_DATA_W-1:0] EXP_STR_OUT_1_TDATA,
output wire [3:0] EXP_STR_OUT_1_TSTRB,
output wire EXP_STR_OUT_1_TLAST,
input wire EXP_STR_OUT_1_FLUSH,
`endif
// Interrupt and DMAC Connections
output wire [3:0] EXP_IRQ,
......@@ -55,6 +84,33 @@ module nanosoc_region_exp #(
.HREADYOUT(HREADYOUT),
.HRESP(HRESP),
.HRDATA(HRDATA),
`ifdef DMAC_DMA350
.EXP_STR_IN_0_TVALID(EXP_STR_IN_0_TVALID),
.EXP_STR_IN_0_TREADY(EXP_STR_IN_0_TREADY),
.EXP_STR_IN_0_TDATA(EXP_STR_IN_0_TDATA),
.EXP_STR_IN_0_TSTRB(EXP_STR_IN_0_TSTRB),
.EXP_STR_IN_0_TLAST(EXP_STR_IN_0_TLAST),
.EXP_STR_OUT_0_TVALID(EXP_STR_OUT_0_TVALID),
.EXP_STR_OUT_0_TREADY(EXP_STR_OUT_0_TREADY),
.EXP_STR_OUT_0_TDATA(EXP_STR_OUT_0_TDATA),
.EXP_STR_OUT_0_TSTRB(EXP_STR_OUT_0_TSTRB),
.EXP_STR_OUT_0_TLAST(EXP_STR_OUT_0_TLAST),
.EXP_STR_OUT_0_FLUSH(EXP_STR_OUT_0_FLUSH),
.EXP_STR_IN_1_TVALID(EXP_STR_IN_1_TVALID),
.EXP_STR_IN_1_TREADY(EXP_STR_IN_1_TREADY),
.EXP_STR_IN_1_TDATA(EXP_STR_IN_1_TDATA),
.EXP_STR_IN_1_TSTRB(EXP_STR_IN_1_TSTRB),
.EXP_STR_IN_1_TLAST(EXP_STR_IN_1_TLAST),
.EXP_STR_OUT_1_TVALID(EXP_STR_OUT_1_TVALID),
.EXP_STR_OUT_1_TREADY(EXP_STR_OUT_1_TREADY),
.EXP_STR_OUT_1_TDATA(EXP_STR_OUT_1_TDATA),
.EXP_STR_OUT_1_TSTRB(EXP_STR_OUT_1_TSTRB),
.EXP_STR_OUT_1_TLAST(EXP_STR_OUT_1_TLAST),
.EXP_STR_OUT_1_FLUSH(EXP_STR_OUT_1_FLUSH),
`endif
.EXP_IRQ(EXP_IRQ),
.EXP_DRQ(EXP_DRQ),
.EXP_DLAST(EXP_DLAST)
......@@ -71,6 +127,9 @@ module nanosoc_region_exp #(
.HRESP (HRESP)
);
assign EXP_STR_IN_0_TREADY = 1'b1;
assign EXP_STR_IN_1_TREADY = 1'b1;
assign HRDATA = 32'heaedeaed; // Tie off Expansion Address Expansion Data
assign EXP_IRQ = 4'd0;
assign EXP_DRQ = 2'd0;
......
......@@ -339,7 +339,7 @@ module nanosoc_region_sysio #(
// APB subsystem for timers, UARTs
nanosoc_sysio_apb_ss #(
.APB_EXT_PORT12_ENABLE (1), // DMAC 1
.APB_EXT_PORT13_ENABLE (0), // Not Used
.APB_EXT_PORT13_ENABLE (1), // Not Used
.APB_EXT_PORT14_ENABLE (1), // USRT
.APB_EXT_PORT15_ENABLE (1), // DMAC 0
.INCLUDE_IRQ_SYNCHRONIZER(0), // require IRQs to be HCLK synchronous
......
......@@ -6,6 +6,7 @@
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
// Daniel Newbrook (d.newbrook@soton.ac.uk)
//
// Copyright 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
......@@ -67,6 +68,7 @@ module nanosoc_ss_dma #(
// DMAC 1 APB Configurtation Port
input wire DMAC_1_PSEL, // APB peripheral select
input wire DMAC_1_PSEL_HI,
input wire DMAC_1_PEN, // APB transfer enable
input wire DMAC_1_PWRITE, // APB transfer direction
input wire [DMAC_1_CFG_ADDR_W-1:0] DMAC_1_PADDR, // APB address
......@@ -75,12 +77,126 @@ module nanosoc_ss_dma #(
output wire DMAC_1_PREADY, // APB Ready
output wire DMAC_1_PSLVERR, // APB Slave Error
`ifdef DMAC_DMA350
// DMAC Channel 0 AXI stream out
output wire DMAC_STR_OUT_0_TVALID,
input wire DMAC_STR_OUT_0_TREADY,
output wire [SYS_DATA_W-1:0] DMAC_STR_OUT_0_TDATA,
output wire [4-1:0] DMAC_STR_OUT_0_TSTRB,
output wire DMAC_STR_OUT_0_TLAST,
// DMAC Channel 0 AXI Stream in
input wire DMAC_STR_IN_0_TVALID,
output wire DMAC_STR_IN_0_TREADY,
input wire [SYS_DATA_W-1:0] DMAC_STR_IN_0_TDATA,
input wire [4-1:0] DMAC_STR_IN_0_TSTRB,
input wire DMAC_STR_IN_0_TLAST,
output wire DMAC_STR_IN_0_FLUSH,
// DMAC Channel 1 AXI Stream out
output wire DMAC_STR_OUT_1_TVALID,
input wire DMAC_STR_OUT_1_TREADY,
output wire [SYS_DATA_W-1:0] DMAC_STR_OUT_1_TDATA,
output wire [4-1:0] DMAC_STR_OUT_1_TSTRB,
output wire DMAC_STR_OUT_1_TLAST,
// DMAC Channel 1 AXI Stream out
input wire DMAC_STR_IN_1_TVALID,
output wire DMAC_STR_IN_1_TREADY,
input wire [SYS_DATA_W-1:0] DMAC_STR_IN_1_TDATA,
input wire [4-1:0] DMAC_STR_IN_1_TSTRB,
input wire DMAC_STR_IN_1_TLAST,
output wire DMAC_STR_IN_1_FLUSH,
`endif
// DMAC 1 DMA Request and Status Port
input wire [DMAC_1_CHANNEL_NUM-1:0] DMAC_1_DMA_REQ, // DMA transfer request
output wire [DMAC_1_CHANNEL_NUM-1:0] DMAC_1_DMA_DONE, // DMA transfer done
output wire DMAC_1_DMA_ERR // DMA slave response not OK
);
`ifdef DMAC_DMA350
//-------------------------------
//DMA Controller 0 Instantiation
//-------------------------------
wire DMAC_1_PSEL_IN;
assign DMAC_1_PSEL_IN = DMAC_1_PSEL | DMAC_1_PSEL_HI;
sldma350_ahb #(
.SYS_ADDR_W (SYS_ADDR_W),
.SYS_DATA_W (SYS_DATA_W),
.CFG_ADDR_W (13),
.CHANNEL_NUM (DMAC_1_CHANNEL_NUM)
) u_dmac (
// AHB Clocks and Resets
.HCLK(SYS_HCLK),
.HRESETn(SYS_HRESETn),
// AHB Lite Port 0
.HADDR_0(DMAC_0_HADDR),
.HTRANS_0(DMAC_0_HTRANS),
.HWRITE_0(DMAC_0_HWRITE),
.HSIZE_0(DMAC_0_HSIZE),
.HBURST_0(DMAC_0_HBURST),
.HPROT_0(DMAC_0_HPROT),
.HWDATA_0(DMAC_0_HWDATA),
.HMASTLOCK_0(DMAC_0_HMASTLOCK),
.HRDATA_0(DMAC_0_HRDATA),
.HREADY_0(DMAC_0_HREADY),
.HRESP_0(DMAC_0_HRESP),
// AHB Lite Port 1
.HADDR_1(DMAC_1_HADDR),
.HTRANS_1(DMAC_1_HTRANS),
.HWRITE_1(DMAC_1_HWRITE),
.HSIZE_1(DMAC_1_HSIZE),
.HBURST_1(DMAC_1_HBURST),
.HPROT_1(DMAC_1_HPROT),
.HWDATA_1(DMAC_1_HWDATA),
.HMASTLOCK_1(DMAC_1_HMASTLOCK),
.HRDATA_1(DMAC_1_HRDATA),
.HREADY_1(DMAC_1_HREADY),
.HRESP_1(DMAC_1_HRESP),
// APB Configuration Port
.PCLKEN(SYS_PCLKEN),
.PSEL(DMAC_1_PSEL_IN),
.PEN(DMAC_1_PEN),
.PWRITE(DMAC_1_PWRITE),
.PADDR({DMAC_1_PSEL_HI, DMAC_1_PADDR}),
.PWDATA(DMAC_1_PWDATA),
.PRDATA(DMAC_1_PRDATA),
.PREADY(DMAC_1_PREADY),
.PSLVERR(DMAC_1_PSLVERR),
// DMA Request and Status Port
.DMA_REQ(DMAC_1_DMA_REQ),
.DMA_DONE(DMAC_1_DMA_DONE),
.DMA_ERR(DMAC_1_DMA_ERR),
.DMAC_STR_OUT_0_TVALID(DMAC_STR_OUT_0_TVALID),
.DMAC_STR_OUT_0_TREADY(DMAC_STR_OUT_0_TREADY),
.DMAC_STR_OUT_0_TDATA(DMAC_STR_OUT_0_TDATA),
.DMAC_STR_OUT_0_TSTRB(DMAC_STR_OUT_0_TSTRB),
.DMAC_STR_OUT_0_TLAST(DMAC_STR_OUT_0_TLAST),
.DMAC_STR_IN_0_TVALID(DMAC_STR_IN_0_TVALID),
.DMAC_STR_IN_0_TREADY(DMAC_STR_IN_0_TREADY),
.DMAC_STR_IN_0_TDATA(DMAC_STR_IN_0_TDATA),
.DMAC_STR_IN_0_TSTRB(DMAC_STR_IN_0_TSTRB),
.DMAC_STR_IN_0_TLAST(DMAC_STR_IN_0_TLAST),
.DMAC_STR_IN_0_FLUSH(DMAC_STR_IN_0_FLUSH),
.DMAC_STR_OUT_1_TVALID(DMAC_STR_OUT_1_TVALID),
.DMAC_STR_OUT_1_TREADY(DMAC_STR_OUT_1_TREADY),
.DMAC_STR_OUT_1_TDATA(DMAC_STR_OUT_1_TDATA),
.DMAC_STR_OUT_1_TSTRB(DMAC_STR_OUT_1_TSTRB),
.DMAC_STR_OUT_1_TLAST(DMAC_STR_OUT_1_TLAST),
.DMAC_STR_IN_1_TVALID(DMAC_STR_IN_1_TVALID),
.DMAC_STR_IN_1_TREADY(DMAC_STR_IN_1_TREADY),
.DMAC_STR_IN_1_TDATA(DMAC_STR_IN_1_TDATA),
.DMAC_STR_IN_1_TSTRB(DMAC_STR_IN_1_TSTRB),
.DMAC_STR_IN_1_TLAST(DMAC_STR_IN_1_TLAST),
.DMAC_STR_IN_1_FLUSH(DMAC_STR_IN_1_FLUSH)
);
`else
`ifdef DMAC_0_PL230
// -------------------------------
// DMA Controller 0 Instantiation
......@@ -153,6 +269,7 @@ module nanosoc_ss_dma #(
`endif
`ifdef DMAC_1_PL230
// -------------------------------
// DMA Controller 0 Instantiation
// -------------------------------
......@@ -161,7 +278,7 @@ module nanosoc_ss_dma #(
.SYS_DATA_W (SYS_DATA_W),
.CFG_ADDR_W (DMAC_1_CFG_ADDR_W),
.CHANNEL_NUM (DMAC_1_CHANNEL_NUM)
) u_dmac_0 (
) u_dmac_1 (
// AHB Clocks and Resets
.HCLK(SYS_HCLK),
.HRESETn(SYS_HRESETn),
......@@ -222,5 +339,6 @@ module nanosoc_ss_dma #(
assign DMAC_1_DMA_DONE = {DMAC_1_CHANNEL_NUM{1'b0}};
assign DMAC_1_DMA_ERR = 1'b0;
`endif
`endif
endmodule
\ No newline at end of file
......@@ -5,9 +5,12 @@
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
// Daniel Newbrook (d.newbrook@soton.ac.uk)
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Copyright (C) 2023, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
`include "gen_defines.v"
module nanosoc_ss_expansion #(
// System Parameters
......@@ -40,6 +43,35 @@ module nanosoc_ss_expansion #(
output wire EXP_HRESP,
output wire [31:0] EXP_HRDATA,
// DMAC Stream interfaces
`ifdef DMAC_DMA350
input wire EXP_STR_IN_0_TVALID,
output wire EXP_STR_IN_0_TREADY,
input wire [SYS_DATA_W-1:0] EXP_STR_IN_0_TDATA,
input wire [3:0] EXP_STR_IN_0_TSTRB,
input wire EXP_STR_IN_0_TLAST,
output wire EXP_STR_OUT_0_TVALID,
input wire EXP_STR_OUT_0_TREADY,
output wire [SYS_DATA_W-1:0] EXP_STR_OUT_0_TDATA,
output wire [3:0] EXP_STR_OUT_0_TSTRB,
output wire EXP_STR_OUT_0_TLAST,
input wire EXP_STR_OUT_0_FLUSH,
input wire EXP_STR_IN_1_TVALID,
output wire EXP_STR_IN_1_TREADY,
input wire [SYS_DATA_W-1:0] EXP_STR_IN_1_TDATA,
input wire [3:0] EXP_STR_IN_1_TSTRB,
input wire EXP_STR_IN_1_TLAST,
output wire EXP_STR_OUT_1_TVALID,
input wire EXP_STR_OUT_1_TREADY,
output wire [SYS_DATA_W-1:0] EXP_STR_OUT_1_TDATA,
output wire [3:0] EXP_STR_OUT_1_TSTRB,
output wire EXP_STR_OUT_1_TLAST,
input wire EXP_STR_OUT_1_FLUSH,
`endif
// SRAM Low Region AHB Port
input wire EXPRAM_L_HSEL,
input wire [SYS_ADDR_W-1:0] EXPRAM_L_HADDR,
......@@ -99,6 +131,33 @@ module nanosoc_ss_expansion #(
.HREADYOUT(EXP_HREADYOUT),
.HRESP(EXP_HRESP),
.HRDATA(EXP_HRDATA),
`ifdef DMAC_DMA350
.EXP_STR_IN_0_TVALID(EXP_STR_IN_0_TVALID),
.EXP_STR_IN_0_TREADY(EXP_STR_IN_0_TREADY),
.EXP_STR_IN_0_TDATA(EXP_STR_IN_0_TDATA),
.EXP_STR_IN_0_TSTRB(EXP_STR_IN_0_TSTRB),
.EXP_STR_IN_0_TLAST(EXP_STR_IN_0_TLAST),
.EXP_STR_OUT_0_TVALID(EXP_STR_OUT_0_TVALID),
.EXP_STR_OUT_0_TREADY(EXP_STR_OUT_0_TREADY),
.EXP_STR_OUT_0_TDATA(EXP_STR_OUT_0_TDATA),
.EXP_STR_OUT_0_TSTRB(EXP_STR_OUT_0_TSTRB),
.EXP_STR_OUT_0_TLAST(EXP_STR_OUT_0_TLAST),
.EXP_STR_OUT_0_FLUSH(EXP_STR_OUT_0_FLUSH),
.EXP_STR_IN_1_TVALID(EXP_STR_IN_1_TVALID),
.EXP_STR_IN_1_TREADY(EXP_STR_IN_1_TREADY),
.EXP_STR_IN_1_TDATA(EXP_STR_IN_1_TDATA),
.EXP_STR_IN_1_TSTRB(EXP_STR_IN_1_TSTRB),
.EXP_STR_IN_1_TLAST(EXP_STR_IN_1_TLAST),
.EXP_STR_OUT_1_TVALID(EXP_STR_OUT_1_TVALID),
.EXP_STR_OUT_1_TREADY(EXP_STR_OUT_1_TREADY),
.EXP_STR_OUT_1_TDATA(EXP_STR_OUT_1_TDATA),
.EXP_STR_OUT_1_TSTRB(EXP_STR_OUT_1_TSTRB),
.EXP_STR_OUT_1_TLAST(EXP_STR_OUT_1_TLAST),
.EXP_STR_OUT_1_FLUSH(EXP_STR_OUT_1_FLUSH),
`endif
// Interrupt and DMAC Connections
.EXP_IRQ(EXP_IRQ),
......
......@@ -6,6 +6,8 @@
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
// Daniel Newbrook (d.newbrook@soton.ac.uk)
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Copyright (C) 2023, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
......@@ -88,6 +90,7 @@ module nanosoc_ss_systemctrl #(
input wire DMAC_0_PSLVERR,
output wire DMAC_1_PSEL,
output wire DMAC_1_PSEL_HI,
input wire [APB_DATA_W-1:0] DMAC_1_PRDATA,
input wire DMAC_1_PREADY,
input wire DMAC_1_PSLVERR,
......@@ -267,7 +270,7 @@ module nanosoc_ss_systemctrl #(
// APB external Slave Interface
.exp12_psel(DMAC_1_PSEL),
.exp13_psel(),
.exp13_psel(DMAC_1_PSEL_HI),
.exp14_psel(USRT_PSEL),
.exp15_psel(DMAC_0_PSEL),
.exp_penable(SYSIO_PENABLE),
......@@ -277,9 +280,9 @@ module nanosoc_ss_systemctrl #(
.exp12_prdata(DMAC_1_PRDATA),
.exp12_pready(DMAC_1_PREADY),
.exp12_pslverr(DMAC_1_PSLVERR),
.exp13_prdata({APB_DATA_W{1'b0}}),
.exp13_pready(1'b1),
.exp13_pslverr(1'b1),
.exp13_prdata(DMAC_1_PRDATA),
.exp13_pready(DMAC_1_PREADY),
.exp13_pslverr(DMAC_1_PSLVERR),
.exp14_prdata(USRT_PRDATA),
.exp14_pready(USRT_PREADY),
.exp14_pslverr(USRT_PSLVERR),
......
......@@ -5,9 +5,12 @@
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
// Daniel Newbrook (d.newbrook@soton.ac.uk)
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Copyright (C) 2023, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
`include "gen_defines.v"
module nanosoc_system #(
// System Parameters
......@@ -415,6 +418,7 @@ module nanosoc_system #(
// DMAC 1 APB Configurtation Port - To System Control Subsystem
wire DMAC_1_PSEL; // APB peripheral select
wire DMAC_1_PSEL_HI;
wire [SYS_DATA_W-1:0] DMAC_1_PRDATA; // APB read data
wire DMAC_1_PREADY; // APB Ready Signal
wire DMAC_1_PSLVERR; // APB Error Signal
......@@ -442,6 +446,35 @@ module nanosoc_system #(
assign DMAC_1_DMA_REQ = {DMAC_1_CHANNEL_NUM{1'b0}};
`ifdef DMAC_DMA350
// DMAC Channel 0 AXI stream out
wire DMAC_STR_OUT_0_TVALID;
wire DMAC_STR_OUT_0_TREADY;
wire [SYS_DATA_W-1:0] DMAC_STR_OUT_0_TDATA;
wire [4-1:0] DMAC_STR_OUT_0_TSTRB;
wire DMAC_STR_OUT_0_TLAST;
// DMAC Channel 0 AXI Stream in
wire DMAC_STR_IN_0_TVALID;
wire DMAC_STR_IN_0_TREADY;
wire [SYS_DATA_W-1:0] DMAC_STR_IN_0_TDATA;
wire [4-1:0] DMAC_STR_IN_0_TSTRB;
wire DMAC_STR_IN_0_TLAST;
wire DMAC_STR_IN_0_FLUSH;
// DMAC Channel 1 AXI Stream out
wire DMAC_STR_OUT_1_TVALID;
wire DMAC_STR_OUT_1_TREADY;
wire [SYS_DATA_W-1:0] DMAC_STR_OUT_1_TDATA;
wire [4-1:0] DMAC_STR_OUT_1_TSTRB;
wire DMAC_STR_OUT_1_TLAST;
// DMAC Channel 1 AXI Stream out
wire DMAC_STR_IN_1_TVALID;
wire DMAC_STR_IN_1_TREADY;
wire [SYS_DATA_W-1:0] DMAC_STR_IN_1_TDATA;
wire [4-1:0] DMAC_STR_IN_1_TSTRB;
wire DMAC_STR_IN_1_TLAST;
wire DMAC_STR_IN_1_FLUSH;
`endif
// Instantiate Subsystem
//--------------------------
......@@ -504,6 +537,7 @@ module nanosoc_system #(
// DMAC 1 APB Configurtation Port
.DMAC_1_PSEL(DMAC_1_PSEL),
.DMAC_1_PSEL_HI(DMAC_1_PSEL_HI),
.DMAC_1_PEN(SYSIO_PENABLE),
.DMAC_1_PWRITE(SYSIO_PWRITE),
.DMAC_1_PADDR(SYSIO_PADDR),
......@@ -512,6 +546,34 @@ module nanosoc_system #(
.DMAC_1_PREADY(DMAC_1_PREADY),
.DMAC_1_PSLVERR(DMAC_1_PSLVERR),
`ifdef DMAC_DMA350
.DMAC_STR_OUT_0_TVALID(DMAC_STR_OUT_0_TVALID),
.DMAC_STR_OUT_0_TREADY(DMAC_STR_OUT_0_TREADY),
.DMAC_STR_OUT_0_TDATA(DMAC_STR_OUT_0_TDATA),
.DMAC_STR_OUT_0_TSTRB(DMAC_STR_OUT_0_TSTRB),
.DMAC_STR_OUT_0_TLAST(DMAC_STR_OUT_0_TLAST),
.DMAC_STR_IN_0_TVALID(DMAC_STR_IN_0_TVALID),
.DMAC_STR_IN_0_TREADY(DMAC_STR_IN_0_TREADY),
.DMAC_STR_IN_0_TDATA(DMAC_STR_IN_0_TDATA),
.DMAC_STR_IN_0_TSTRB(DMAC_STR_IN_0_TSTRB),
.DMAC_STR_IN_0_TLAST(DMAC_STR_IN_0_TLAST),
.DMAC_STR_IN_0_FLUSH(DMAC_STR_IN_0_FLUSH),
.DMAC_STR_OUT_1_TVALID(DMAC_STR_OUT_1_TVALID),
.DMAC_STR_OUT_1_TREADY(DMAC_STR_OUT_1_TREADY),
.DMAC_STR_OUT_1_TDATA(DMAC_STR_OUT_1_TDATA),
.DMAC_STR_OUT_1_TSTRB(DMAC_STR_OUT_1_TSTRB),
.DMAC_STR_OUT_1_TLAST(DMAC_STR_OUT_1_TLAST),
.DMAC_STR_IN_1_TVALID(DMAC_STR_IN_1_TVALID),
.DMAC_STR_IN_1_TREADY(DMAC_STR_IN_1_TREADY),
.DMAC_STR_IN_1_TDATA(DMAC_STR_IN_1_TDATA),
.DMAC_STR_IN_1_TSTRB(DMAC_STR_IN_1_TSTRB),
.DMAC_STR_IN_1_TLAST(DMAC_STR_IN_1_TLAST),
.DMAC_STR_IN_1_FLUSH(DMAC_STR_IN_1_FLUSH),
`endif
// DMAC 1 DMA Request and Status Port
.DMAC_1_DMA_REQ(DMAC_1_DMA_REQ),
.DMAC_1_DMA_DONE(DMAC_1_DMA_DONE),
......@@ -720,6 +782,34 @@ module nanosoc_system #(
.EXP_HRESP(EXP_HRESP),
.EXP_HRDATA(EXP_HRDATA),
`ifdef DMAC_DMA350
.EXP_STR_IN_0_TVALID(DMAC_STR_OUT_0_TVALID),
.EXP_STR_IN_0_TREADY(DMAC_STR_OUT_0_TREADY),
.EXP_STR_IN_0_TDATA(DMAC_STR_OUT_0_TDATA),
.EXP_STR_IN_0_TSTRB(DMAC_STR_OUT_0_TSTRB),
.EXP_STR_IN_0_TLAST(DMAC_STR_OUT_0_TLAST),
.EXP_STR_OUT_0_TVALID(DMAC_STR_IN_0_TVALID),
.EXP_STR_OUT_0_TREADY(DMAC_STR_IN_0_TREADY),
.EXP_STR_OUT_0_TDATA(DMAC_STR_IN_0_TDATA),
.EXP_STR_OUT_0_TSTRB(DMAC_STR_IN_0_TSTRB),
.EXP_STR_OUT_0_TLAST(DMAC_STR_IN_0_TLAST),
.EXP_STR_OUT_0_FLUSH(DMAC_STR_IN_0_FLUSH),
.EXP_STR_IN_1_TVALID(DMAC_STR_OUT_1_TVALID),
.EXP_STR_IN_1_TREADY(DMAC_STR_OUT_1_TREADY),
.EXP_STR_IN_1_TDATA(DMAC_STR_OUT_1_TDATA),
.EXP_STR_IN_1_TSTRB(DMAC_STR_OUT_1_TSTRB),
.EXP_STR_IN_1_TLAST(DMAC_STR_OUT_1_TLAST),
.EXP_STR_OUT_1_TVALID(DMAC_STR_IN_1_TVALID),
.EXP_STR_OUT_1_TREADY(DMAC_STR_IN_1_TREADY),
.EXP_STR_OUT_1_TDATA(DMAC_STR_IN_1_TDATA),
.EXP_STR_OUT_1_TSTRB(DMAC_STR_IN_1_TSTRB),
.EXP_STR_OUT_1_TLAST(DMAC_STR_IN_1_TLAST),
.EXP_STR_OUT_1_FLUSH(DMAC_STR_IN_1_FLUSH),
`endif
// SRAM Low Region AHB Port
.EXPRAM_L_HSEL(EXPRAM_L_HSEL),
.EXPRAM_L_HADDR(EXPRAM_L_HADDR),
......@@ -912,6 +1002,7 @@ module nanosoc_system #(
.DMAC_0_PSLVERR(DMAC_0_PSLVERR),
.DMAC_1_PSEL(DMAC_1_PSEL),
.DMAC_1_PSEL_HI(DMAC_1_PSEL_HI),
.DMAC_1_PRDATA(DMAC_1_PRDATA),
.DMAC_1_PREADY(DMAC_1_PREADY),
.DMAC_1_PSLVERR(DMAC_1_PSLVERR),
......
......@@ -36,6 +36,7 @@
//-----------------------------------------------------------------------------
//
`timescale 1ns/1ps
`include "gen_defines.v"
module nanosoc_tb;
......@@ -512,7 +513,7 @@ nanosoc_ft1248x1_track
// - Track inputs to on-chip PL230 DMAC and replicate state and outputs in testbench
// - log the RTL Inuts/outputs/internal-state of this traccking DMAC
// --------------------------------------------------------------------------------
`ifdef DMAC_0_PL230
`define DMAC_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_system.u_ss_dma.u_dmac_0.u_pl230_udma
pl230_udma u_track_pl230_udma (
......@@ -584,6 +585,7 @@ nanosoc_ft1248x1_track
.dma_ctrl_state(`DMAC_TRACK_PATH.u_pl230_ahb_ctrl.ctrl_state)
);
`endif
`endif
// --------------------------------------------------------------------------------
// Tracking Accelerator logging support
......
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment