Initial Update for 65nm and 28nm flows + synopsys SLM integration

b48b1671 · Daniel Newbrook · 5ecef650 · b48b1671 · b48b1671 · b48b1671
Commit b48b1671 authored 8 months ago by Daniel Newbrook
--- a/ASIC/60pin/Synopsys/scripts/synthesis.tcl
+++ b/ASIC/60pin/Synopsys/scripts/synthesis.tcl
--- a/ASIC/60pin/Synopsys/upf/nanosoc_chip_pads.upf
+++ b/ASIC/60pin/Synopsys/upf/nanosoc_chip_pads.upf
--- a/ASIC/accelerator_only/Cadence/scripts/genus.tcl
+++ b/ASIC/accelerator_only/Cadence/scripts/genus.tcl
--- a/ASIC/accelerator_only/accel_constraints.sdc
+++ b/ASIC/accelerator_only/accel_constraints.sdc
--- a/ASIC/constraints.sdc
+++ b/ASIC/constraints.sdc
--- a/ASIC/rf_08k.spec
+++ b/ASIC/rf_08k.spec
--- a/ASIC/rf_16k.spec
+++ b/ASIC/rf_16k.spec
--- a/ASIC/rom_via.spec
+++ b/ASIC/rom_via.spec
--- a/ASIC/60pin/Synopsys/scripts/synopsys_lib_conversion.tcl
+++ b/ASIC/60pin/Synopsys/scripts/synopsys_lib_conversion.tcl
-set RF_PATH $env(SOCLABS_PROJECT_DIR)/memories/rf
+set RF_PATH $env(SOCLABS_PROJECT_DIR)/memories/rf_16k
 read_lib $RF_PATH/rf_sp_hdf_ss_1p08v_1p08v_125c.lib
 write_lib RF_LIB_ss_1p08v_1p08v_125c -output $RF_PATH/rf_sp_hdf_ss_1p08v_1p08v_125c.db

--- a/ASIC/nanosoc_chip_pads/tsmc28hpcp/nanosoc_chip_pads_38pin.v
+++ b/ASIC/nanosoc_chip_pads/tsmc28hpcp/nanosoc_chip_pads_38pin.v
+//-----------------------------------------------------------------------------
+// Top-Level Pad implementation for TSMC65nm
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+//            (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+//                ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+//      SVN Information
+//
+//      Checked In          : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+//      Revision            : $Revision: 371321 $
+//
+//      Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Top level for example Cortex-M0/Cortex-M0+ microcontroller
+//-----------------------------------------------------------------------------
+//
+`include "gen_defines.v"
+module nanosoc_chip_pads (
+  inout  wire          VDDIO,
+  inout  wire          VSSIO,
+  inout  wire          VDD,
+  inout  wire          VSS,
+  inout  wire          VDDACC,
+  input  wire          SE,
+  input  wire          CLK, // input
+  input  wire          TEST, // input
+  input  wire          NRST,  // active low reset
+  inout  wire  [7:0]  P0,
+  inout  wire  [7:0]  P1,
+  inout  wire          SWDIO,
+  input  wire          SWDCK);
+//------------------------------------
+// internal wires
+localparam GPIO_TIO = 4;
+wire        pad_clk_i;
+wire        pad_nrst_i;
+wire        pad_test_i;
+wire        pad_swdclk_i;
+wire        pad_swdio_i;
+wire        pad_swdio_o;
+wire        pad_swdio_e;
+wire        pad_swdio_z;
+wire [15:0] pad_gpio_port0_i ; 
+wire [15:0] pad_gpio_port0_o ;
+wire [15:0] pad_gpio_port0_e ;
+wire [15:0] pad_gpio_port0_z ;
+wire [15:0] pad_gpio_port1_i ;
+wire [15:0] pad_gpio_port1_o ;
+wire [15:0] pad_gpio_port1_e ;
+wire [15:0] pad_gpio_port1_z ;
+wire        soc_nreset;
+wire        soc_diag_mode;
+wire        soc_diag_ctrl;
+wire        soc_scan_mode;
+wire        soc_scan_enable;
+wire [GPIO_TIO-1:0] soc_scan_in; //soc test status outputs
+wire [GPIO_TIO-1:0] soc_scan_out; //soc test status outputs
+wire        soc_bist_mode;
+wire        soc_bist_enable;
+wire [GPIO_TIO-1:0] soc_bist_in; //soc test status outputs
+wire [GPIO_TIO-1:0] soc_bist_out; //soc test status outputs
+wire        soc_alt_mode; // ALT MODE = UART
+wire        soc_uart_rxd_i; // UART RXD
+wire        soc_uart_txd_o = 1'b1; // UART TXD
+wire        soc_swd_mode; // SWD mode
+wire        soc_swd_clk_i; // SWDCLK
+wire        soc_swd_dio_i; // SWDIO tristate input
+wire        soc_swd_dio_o; // SWDIO trstate output
+wire        soc_swd_dio_e; // SWDIO tristate output enable
+wire        soc_swd_dio_z; // SWDIO tristate output hiz
+wire [15:0] soc_gpio_port0_i; // GPIO SOC tristate input
+wire [15:0] soc_gpio_port0_o; // GPIO SOC trstate output
+wire [15:0] soc_gpio_port0_e; // GPIO SOC tristate output enable
+wire [15:0] soc_gpio_port0_z; // GPIO SOC tristate output hiz
+wire [15:0] soc_gpio_port1_i; // GPIO SOC tristate input
+wire [15:0] soc_gpio_port1_o; // GPIO SOC trstate output
+wire [15:0] soc_gpio_port1_e; // GPIO SOC tristate output enable
+wire [15:0] soc_gpio_port1_z; // GPIO SOC tristate output hiz
+wire pad_se_i;
+// connect up high order GPIOs
+assign soc_gpio_port0_i[15:GPIO_TIO] = pad_gpio_port0_i[15:GPIO_TIO];
+assign pad_gpio_port0_o[15:GPIO_TIO] = soc_gpio_port0_o[15:GPIO_TIO];
+assign pad_gpio_port0_e[15:GPIO_TIO] = soc_gpio_port0_e[15:GPIO_TIO];
+assign pad_gpio_port0_z[15:GPIO_TIO] = soc_gpio_port0_z[15:GPIO_TIO];
+assign soc_gpio_port1_i[15:GPIO_TIO] = pad_gpio_port1_i[15:GPIO_TIO];
+assign pad_gpio_port1_o[15:GPIO_TIO] = soc_gpio_port1_o[15:GPIO_TIO];
+assign pad_gpio_port1_e[15:GPIO_TIO] = soc_gpio_port1_e[15:GPIO_TIO];
+assign pad_gpio_port1_z[15:GPIO_TIO] = soc_gpio_port1_z[15:GPIO_TIO];
+wire tiehi = 1'b1;
+wire tielo = 1'b0;
+nanosoc_chip_cfg #(
+    .GPIO_TIO (GPIO_TIO)
+  )
+  u_nanosoc_chip_cfg
+  (
+  // Primary Inputs
+   .pad_clk_i        (pad_clk_i         )
+  ,.pad_nrst_i       (pad_nrst_i        )
+  ,.pad_test_i       (pad_test_i        )
+  // Alternate/reconfigurable IP and associated bidirectional I/O
+  ,.pad_altin_i      (pad_se_i      )  // SWCLK/UARTRXD/SCAN-ENABLE
+  ,.pad_altio_i      (pad_swdio_i       )  // SWDIO/UARTTXD tristate input
+  ,.pad_altio_o      (pad_swdio_o       )  // SWDIO/UARTTXD trstate output
+  ,.pad_altio_e      (pad_swdio_e       )  // SWDIO/UARTTXD tristate output enable
+  ,.pad_altio_z      (pad_swdio_z       )  // SWDIO/UARTTXD tristate output hiz
+  // Reconfigurable General Purpose bidirectional I/Os Port-0 (user)
+  ,.pad_gpio_port0_i (pad_gpio_port0_i[GPIO_TIO-1:0]) // GPIO PAD tristate input
+  ,.pad_gpio_port0_o (pad_gpio_port0_o[GPIO_TIO-1:0]) // GPIO PAD trstate output
+  ,.pad_gpio_port0_e (pad_gpio_port0_e[GPIO_TIO-1:0]) // GPIO PAD tristate output enable
+  ,.pad_gpio_port0_z (pad_gpio_port0_z[GPIO_TIO-1:0]) // GPIO PAD tristate output hiz
+  // Reconfigurable General Purpose bidirectional I/Os Port-1 (system)
+  ,.pad_gpio_port1_i (pad_gpio_port1_i[GPIO_TIO-1:0]) // GPIO PAD tristate input
+  ,.pad_gpio_port1_o (pad_gpio_port1_o[GPIO_TIO-1:0]) // GPIO PAD trstate output
+  ,.pad_gpio_port1_e (pad_gpio_port1_e[GPIO_TIO-1:0]) // GPIO PAD tristate output enable
+  ,.pad_gpio_port1_z (pad_gpio_port1_z[GPIO_TIO-1:0]) // GPIO PAD tristate output hiz
+  //SOC
+  ,.soc_nreset       (soc_nreset        )
+  ,.soc_diag_mode    (soc_diag_mode     )
+  ,.soc_diag_ctrl    (soc_diag_ctrl     )
+  ,.soc_scan_mode    (soc_scan_mode     )
+  ,.soc_scan_enable  (soc_scan_enable   )
+  ,.soc_scan_in      (soc_scan_in       ) // soc test scan chain inputs
+  ,.soc_scan_out     (soc_scan_out      ) // soc test scan chain outputs
+  ,.soc_bist_mode    (soc_bist_mode     )
+  ,.soc_bist_enable  (soc_bist_enable   )
+  ,.soc_bist_in      (soc_bist_in       ) // soc bist control inputs
+  ,.soc_bist_out     (soc_bist_out      ) // soc test status outputs
+  ,.soc_alt_mode     (soc_alt_mode      )// ALT MODE = UART
+  ,.soc_uart_rxd_i   (soc_uart_rxd_i    ) // UART RXD
+  ,.soc_uart_txd_o   (soc_uart_txd_o    ) // UART TXD
+  ,.soc_swd_mode     (soc_swd_mode      ) // SWD mode
+  ,.soc_swd_clk_i    (soc_swd_clk_i     ) // SWDCLK
+  ,.soc_swd_dio_i    (soc_swd_dio_i     ) // SWDIO tristate input
+  ,.soc_swd_dio_o    (soc_swd_dio_o     ) // SWDIO trstate output
+  ,.soc_swd_dio_e    (soc_swd_dio_e     ) // SWDIO tristate output enable
+  ,.soc_swd_dio_z    (soc_swd_dio_z     ) // SWDIO tristate output hiz
+  ,.soc_gpio_port0_i (soc_gpio_port0_i[GPIO_TIO-1:0]) // GPIO SOC tristate input
+  ,.soc_gpio_port0_o (soc_gpio_port0_o[GPIO_TIO-1:0]) // GPIO SOC trstate output
+  ,.soc_gpio_port0_e (soc_gpio_port0_e[GPIO_TIO-1:0]) // GPIO SOC tristate output enable
+  ,.soc_gpio_port0_z (soc_gpio_port0_z[GPIO_TIO-1:0]) // GPIO SOC tristate output hiz
+  ,.soc_gpio_port1_i (soc_gpio_port1_i[GPIO_TIO-1:0]) // GPIO SOC tristate input
+  ,.soc_gpio_port1_o (soc_gpio_port1_o[GPIO_TIO-1:0]) // GPIO SOC trstate output
+  ,.soc_gpio_port1_e (soc_gpio_port1_e[GPIO_TIO-1:0]) // GPIO SOC tristate output enable
+  ,.soc_gpio_port1_z (soc_gpio_port1_z[GPIO_TIO-1:0]) // GPIO SOC tristate output hiz
+);
+  nanosoc_chip u_nanosoc_chip (
+`ifdef POWER_PINS
+  .VDD        (VDD),
+  .VSS        (VSS),
+  .VDDACC     (VDDACC),
+`endif
+//`ifdef ASIC_TEST_PORTS
+  .diag_mode   (soc_diag_mode     ),
+  .diag_ctrl   (soc_diag_ctrl     ),
+  .scan_mode   (soc_scan_mode     ),
+  .scan_enable (soc_scan_enable   ),
+  .scan_in     (soc_scan_in       ), // soc test scan chain inputs
+  .scan_out    (soc_scan_out      ),       // soc test scan chain outputs
+  .bist_mode   (soc_bist_mode     ),
+  .bist_enable (soc_bist_enable   ),
+  .bist_in     (soc_bist_in       ), // soc bist control inputs
+  .bist_out    (soc_bist_out      ),       // soc test status outputs
+  .alt_mode    (soc_alt_mode      ),// ALT MODE = UART
+  .uart_rxd_i  (soc_uart_rxd_i    ), // UART RXD
+  .uart_txd_o  (soc_uart_txd_o    ), // UART TXD
+  .swd_mode    (soc_swd_mode      ),    // SWD mode
+//`endif
+  .clk_i(pad_clk_i),
+  .test_i(soc_scan_mode),
+  .nrst_i(soc_nreset),
+  .p0_i(soc_gpio_port0_i), // level-shifted input from pad
+  .p0_o(soc_gpio_port0_o), // output port drive
+  .p0_e(soc_gpio_port0_e), // active high output drive enable (pad tech dependent)
+  .p0_z(soc_gpio_port0_z), // active low output drive enable (pad tech dependent)
+  .p1_i(soc_gpio_port1_i), // level-shifted input from pad
+  .p1_o(soc_gpio_port1_o), // output port drive
+  .p1_e(soc_gpio_port1_e), // active high output drive enable (pad tech dependent)
+  .p1_z(soc_gpio_port1_z), // active low output drive enable (pad tech dependent)
+  .swdio_i(soc_swd_dio_i),
+  .swdio_o(soc_swd_dio_o),
+  .swdio_e(soc_swd_dio_e),
+  .swdio_z(soc_swd_dio_z),
+  .swdclk_i(pad_swdclk_i)
+  );
+ // --------------------------------------------------------------------------------
+ // IO pad (TSMC 65nm specific Library napping)
+ // --------------------------------------------------------------------------------
+// Pad IO power supplies
+PVDD2CDG uPAD_VDDIO_0(
+   .VDDPST(VDDIO)
+   );
+//PVDD2CDG uPAD_VDDIO_1(
+//   .VDDPST(VDDIO)
+//   );
+PVDD2CDG uPAD_VDDIO_2(
+   .VDDPST(VDDIO)
+   );
+PVDD2POC uPAD_VDDIO_3(
+   .VDDPST(VDDIO)
+   );
+PVSS2CDG uPAD_VSSIO_0(
+   .VSSPST(VSSIO)
+   );
+PVSS2CDG uPAD_VSSIO_1(
+   .VSSPST(VSSIO)
+   );
+// Core power supplies
+PVDD1CDG uPAD_VDD_0(
+   .VDD(VDD)
+   );
+PVDD1CDG uPAD_VDD_1(
+   .VDD(VDD)
+   );
+PVDD1CDG uPAD_VDD_2(
+   .VDD(VDD)
+   );
+PVDD1CDG uPAD_VDD_3(
+   .VDD(VDD)
+   );
+PVSS1CDG uPAD_VSS_0(
+   .VSS(VSS)
+   );
+PVSS1CDG uPAD_VSS_1(
+   .VSS(VSS)
+   );
+PVSS1CDG uPAD_VSS_2(
+   .VSS(VSS)
+   );
+PVSS1CDG uPAD_VSS_3(
+   .VSS(VSS)
+   );
+// Accelerator Power supplies
+PVDD1CDG uPAD_VDDACC_0(
+   .VDD(VDDACC)
+   );
+PVDD1CDG uPAD_VDDACC_1(
+   .VDD(VDDACC)
+   );
+PVDD1CDG uPAD_VDDACC_2(
+   .VDD(VDDACC)
+   );
+// Clock, Reset and Serial Wire Debug ports
+PRDW0408SCDG uPAD_SE_I (
+    .IE(tiehi),
+    .C(pad_se_i),
+    .PE(tielo),
+    .DS(tielo),
+    .I(tielo),
+    .OEN(tiehi),
+    .PAD(SE)
+   );
+PRDW0408SCDG uPAD_CLK_I (
+    .IE(tiehi),
+    .C(pad_clk_i),
+    .PE(tielo),
+    .DS(tielo),
+    .I(tielo),
+    .OEN(tiehi),
+    .PAD(CLK)
+   );
+PRDW0408SCDG uPAD_TEST_I (
+    .IE(tiehi),
+    .C(pad_test_i),
+    .PE(tielo),
+    .DS(tielo),
+    .I(tielo),
+    .OEN(tiehi),
+    .PAD(TEST)
+   );
+PRDW0408SCDG uPAD_NRST_I (
+    .IE(tiehi),
+    .C(pad_nrst_i),
+    .PE(tielo),
+    .DS(tielo),
+    .I(tielo),
+    .OEN(tiehi),
+    .PAD(NRST)
+   );
+PRDW0408SCDG uPAD_SWDIO_IO (
+    .IE(pad_swdio_z),
+    .C(pad_swdio_i),
+    .PE(tielo),
+    .DS(tielo),
+    .I(pad_swdio_o),
+    .OEN(pad_swdio_z),
+    .PAD(SWDIO)
+   );
+PRDW0408SCDG uPAD_SWDCK_I (
+    .IE(tiehi),
+    .C(pad_swdclk_i),
+    .PE(tielo),
+    .DS(tielo),
+    .I(tielo),
+    .OEN(tiehi),
+    .PAD(SWDCK)
+   );
+// GPI.I Port 0 x 16
+PRDW0408SCDG uPAD_P0_00 (
+    .IE(pad_gpio_port0_z[00]),
+    .C(pad_gpio_port0_i[00]),
+    .PE(pad_gpio_port0_z[00]&pad_gpio_port0_o[00]),
+    .DS(tielo),
+    .I(pad_gpio_port0_o[00]),
+    .OEN(pad_gpio_port0_z[00]),
+    .PAD(P0[00])
+   );
+PRDW0408SCDG uPAD_P0_01 (
+    .IE(pad_gpio_port0_z[01]),
+    .C(pad_gpio_port0_i[01]),
+    .PE(pad_gpio_port0_z[01]&pad_gpio_port0_o[01]),
+    .DS(tielo),
+    .I(pad_gpio_port0_o[01]),
+    .OEN(pad_gpio_port0_z[01]),
+    .PAD(P0[01])
+   );
+PRDW0408SCDG uPAD_P0_02 (
+    .IE(pad_gpio_port0_z[02]),
+    .C(pad_gpio_port0_i[02]),
+    .PE(pad_gpio_port0_z[02]&pad_gpio_port0_o[02]),
+    .DS(tielo),
+    .I(pad_gpio_port0_o[02]),
+    .OEN(pad_gpio_port0_z[02]),
+    .PAD(P0[02])
+   );
+PRDW0408SCDG uPAD_P0_03 (
+    .IE(pad_gpio_port0_z[03]),
+    .C(pad_gpio_port0_i[03]),
+    .PE(pad_gpio_port0_z[03]&pad_gpio_port0_o[03]),
+    .DS(tielo),
+    .I(pad_gpio_port0_o[03]),
+    .OEN(pad_gpio_port0_z[03]),
+    .PAD(P0[03])
+   );
+PRDW0408SCDG uPAD_P0_04 (
+    .IE(pad_gpio_port0_z[04]),
+    .C(pad_gpio_port0_i[04]),
+    .PE(pad_gpio_port0_z[04]&pad_gpio_port0_o[04]),
+    .DS(tielo),
+    .I(pad_gpio_port0_o[04]),
+    .OEN(pad_gpio_port0_z[04]),
+    .PAD(P0[04])
+   );
+PRDW0408SCDG uPAD_P0_05 (
+    .IE(pad_gpio_port0_z[05]),
+    .C(pad_gpio_port0_i[05]),
+    .PE(pad_gpio_port0_z[05]&pad_gpio_port0_o[05]),
+    .DS(tielo),
+    .I(pad_gpio_port0_o[05]),
+    .OEN(pad_gpio_port0_z[05]),
+    .PAD(P0[05])
+   );
+PRDW0408SCDG uPAD_P0_06 (
+    .IE(pad_gpio_port0_z[06]),
+    .C(pad_gpio_port0_i[06]),
+    .PE(pad_gpio_port0_z[06]&pad_gpio_port0_o[06]),
+    .DS(tielo),
+    .I(pad_gpio_port0_o[06]),
+    .OEN(pad_gpio_port0_z[06]),
+    .PAD(P0[06])
+   );
+PRDW0408SCDG uPAD_P0_07 (
+    .IE(pad_gpio_port0_z[07]),
+    .C(pad_gpio_port0_i[07]),
+    .PE(pad_gpio_port0_z[07]&pad_gpio_port0_o[07]),
+    .DS(tielo),
+    .I(pad_gpio_port0_o[07]),
+    .OEN(pad_gpio_port0_z[07]),
+    .PAD(P0[07])
+   );
+// GPI.I Port 1 x 16
+PRDW0408SCDG uPAD_P1_00 (
+    .IE(pad_gpio_port1_z[00]),
+    .C(pad_gpio_port1_i[00]),
+    .PE(pad_gpio_port1_z[00]&pad_gpio_port1_o[00]),
+    .DS(tielo),
+    .I(pad_gpio_port1_o[00]),
+    .OEN(pad_gpio_port1_z[00]),
+    .PAD(P1[00])
+   );
+PRDW0408SCDG uPAD_P1_01 (
+    .IE(pad_gpio_port1_z[01]),
+    .C(pad_gpio_port1_i[01]),
+    .PE(pad_gpio_port1_z[01]&pad_gpio_port1_o[01]),
+    .DS(tielo),
+    .I(pad_gpio_port1_o[01]),
+    .OEN(pad_gpio_port1_z[01]),
+    .PAD(P1[01])
+   );
+PRDW0408SCDG uPAD_P1_02 (
+    .IE(pad_gpio_port1_z[02]),
+    .C(pad_gpio_port1_i[02]),
+    .PE(pad_gpio_port1_z[02]&pad_gpio_port1_o[02]),
+    .DS(tielo),
+    .I(pad_gpio_port1_o[02]),
+    .OEN(pad_gpio_port1_z[02]),
+    .PAD(P1[02])
+   );
+PRDW0408SCDG uPAD_P1_03 (
+    .IE(pad_gpio_port1_z[03]),
+    .C(pad_gpio_port1_i[03]),
+    .PE(pad_gpio_port1_z[03]&pad_gpio_port1_o[03]),
+    .DS(tielo),
+    .I(pad_gpio_port1_o[03]),
+    .OEN(pad_gpio_port1_z[03]),
+    .PAD(P1[03])
+   );
+PRDW0408SCDG uPAD_P1_04 (
+    .IE(pad_gpio_port1_z[04]),
+    .C(pad_gpio_port1_i[04]),
+    .PE(pad_gpio_port1_z[04]&pad_gpio_port1_o[04]),
+    .DS(tielo),
+    .I(pad_gpio_port1_o[04]),
+    .OEN(pad_gpio_port1_z[04]),
+    .PAD(P1[04])
+   );
+PRDW0408SCDG uPAD_P1_05 (
+    .IE(pad_gpio_port1_z[05]),
+    .C(pad_gpio_port1_i[05]),
+    .PE(pad_gpio_port1_z[05]&pad_gpio_port1_o[05]),
+    .DS(tielo),
+    .I(pad_gpio_port1_o[05]),
+    .OEN(pad_gpio_port1_z[05]),
+    .PAD(P1[05])
+   );
+PRDW0408SCDG uPAD_P1_06 (
+    .IE(pad_gpio_port1_z[06]),
+    .C(pad_gpio_port1_i[06]),
+    .PE(pad_gpio_port1_z[06]&pad_gpio_port1_o[06]),
+    .DS(tielo),
+    .I(pad_gpio_port1_o[06]),
+    .OEN(pad_gpio_port1_z[06]),
+    .PAD(P1[06])
+   );
+PRDW0408SCDG uPAD_P1_07 (
+    .IE(pad_gpio_port1_z[07]),
+    .C(pad_gpio_port1_i[07]),
+    .PE(pad_gpio_port1_z[07]&pad_gpio_port1_o[07]),
+    .DS(tielo),
+    .I(pad_gpio_port1_o[07]),
+    .OEN(pad_gpio_port1_z[07]),
+    .PAD(P1[07])
+   );
+assign pad_gpio_port0_i[8] = pad_gpio_port0_o[8] & pad_gpio_port0_e[8];
+assign pad_gpio_port0_i[9] = pad_gpio_port0_o[9] & pad_gpio_port0_e[9];
+assign pad_gpio_port0_i[10] = pad_gpio_port0_o[10] & pad_gpio_port0_e[10];
+assign pad_gpio_port0_i[11] = pad_gpio_port0_o[11] & pad_gpio_port0_e[11];
+assign pad_gpio_port0_i[12] = pad_gpio_port0_o[12] & pad_gpio_port0_e[12];
+assign pad_gpio_port0_i[13] = pad_gpio_port0_o[13] & pad_gpio_port0_e[13];
+assign pad_gpio_port0_i[14] = pad_gpio_port0_o[14] & pad_gpio_port0_e[14];
+assign pad_gpio_port0_i[15] = pad_gpio_port0_o[15] & pad_gpio_port0_e[15];
+assign pad_gpio_port1_i[8] = pad_gpio_port1_o[8] & pad_gpio_port1_e[8];
+assign pad_gpio_port1_i[9] = pad_gpio_port1_o[9] & pad_gpio_port1_e[9];
+assign pad_gpio_port1_i[10] = pad_gpio_port1_o[10] & pad_gpio_port1_e[10];
+assign pad_gpio_port1_i[11] = pad_gpio_port1_o[11] & pad_gpio_port1_e[11];
+assign pad_gpio_port1_i[12] = pad_gpio_port1_o[12] & pad_gpio_port1_e[12];
+assign pad_gpio_port1_i[13] = pad_gpio_port1_o[13] & pad_gpio_port1_e[13];
+assign pad_gpio_port1_i[14] = pad_gpio_port1_o[14] & pad_gpio_port1_e[14];
+assign pad_gpio_port1_i[15] = pad_gpio_port1_o[15] & pad_gpio_port1_e[15];
+endmodule
--- a/flows/makefile.asic
+++ b/flows/makefile.asic
@@ -34,19 +34,30 @@ FORMALITY_OUTPUT_FILELIST := $(TCL_ASIC_FLIST_DIR)/formality_flist.tcl
 DC_OUTPUT_FILELIST := $(TCL_ASIC_FLIST_DIR)/dc_flist.tcl
 # Location of outputs from synthesis
-MEMORIES_DIR		:= $(SOCLABS_PROJECT_DIR)/memories
+MEMORIES_DIR			:= $(SOCLABS_PROJECT_DIR)/memories
-RF_16K_SPEC_FILE	:= $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/rf_16k.spec
+RF_16K_65nm_SPEC_FILE	:= $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/TSMC65nm/rf_16k.spec
-RF_08K_SPEC_FILE		:= $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/rf_08k.spec
+RF_08K_65nm_SPEC_FILE	:= $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/TSMC65nm/rf_08k.spec
-ROM_SPEC_FILE		:= $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/rom_via.spec
+ROM_65nm_SPEC_FILE		:= $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/TSMC65nm/rom_via.spec
-BOOTROM_BIN_FILE_IN := $(SOCLABS_PROJECT_DIR)/system/src/bootrom/bintxt/bootrom.bintxt
+SRAM_16K_28nm_SPEC_FILE	:= $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/TSMC28nm/sram_16k.spec
-BOOTROM_BIN_FILE	:= $(SOCLABS_PROJECT_DIR)/system/src/bootrom/bintxt/bootrom.rcf
+ROM_28nm_SPEC_FILE		:= $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/TSMC28nm/rom_via.spec
-RF_16K_DIR			:= $(MEMORIES_DIR)/rf_16k
+BOOTROM_BIN_FILE_IN 	:= $(SOCLABS_PROJECT_DIR)/system/src/bootrom/bintxt/bootrom.bintxt
-RF_08K_DIR			:= $(MEMORIES_DIR)/rf_08k
+BOOTROM_BIN_FILE		:= $(SOCLABS_PROJECT_DIR)/system/src/bootrom/bintxt/bootrom.rcf
-ROM_DIR 			:= $(MEMORIES_DIR)/bootrom
+RF_16K_DIR				:= $(MEMORIES_DIR)/rf_16k
-REPORTS_FOLDER		:= $(IMP_NANOSOC_ASIC_DIR)/reports
+RF_08K_DIR				:= $(MEMORIES_DIR)/rf_08k
-SYN_LOGS			:= $(IMP_NANOSOC_ASIC_DIR)/logs
+ROM_DIR 				:= $(MEMORIES_DIR)/bootrom
-NETLIST_FOLDER		:= $(IMP_NANOSOC_ASIC_DIR)/netlist/
+SRAM_16K_DIR			:= $(MEMORIES_DIR)/sram_16k 
-NANOSOC_SYNTH_DIR	:= $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/
+REPORTS_FOLDER			:= $(IMP_NANOSOC_ASIC_DIR)/reports
+SYN_LOGS				:= $(IMP_NANOSOC_ASIC_DIR)/logs
+NETLIST_FOLDER			:= $(IMP_NANOSOC_ASIC_DIR)/netlist/
+NODE ?= 65
+ifeq ($(NODE),65)
+	NANOSOC_SYNTH_DIR	:= $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/TSMC65nm
+else
+	NANOSOC_SYNTH_DIR 	:= $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/TSMC28nm
+endif
 # NanoSoC Tech Flow Dependencies
 NANOSOC_FPGA_FLOW_DIR := $(SOCLABS_NANOSOC_TECH_DIR)/fpga
@@ -81,17 +92,48 @@ gen_memories: bootrom
 	cp $(BOOTROM_BIN_FILE_IN) $(BOOTROM_BIN_FILE)
 	echo "Generating register file memory libraries"
 	echo "16K RF"
-	cd $(RF_16K_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rf_sp_hdf_hvt_rvt/r0p0/bin/rf_sp_hdf_hvt_rvt all -spec $(RF_16K_SPEC_FILE);
+	cd $(RF_16K_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rf_sp_hdf_hvt_rvt/r0p0/bin/rf_sp_hdf_hvt_rvt all -spec $(RF_16K_65nm_SPEC_FILE);
-	cd $(RF_16K_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rf_sp_hdf_hvt_rvt/r0p0/bin/rf_sp_hdf_hvt_rvt liberty -spec $(RF_16K_SPEC_FILE);
+	cd $(RF_16K_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rf_sp_hdf_hvt_rvt/r0p0/bin/rf_sp_hdf_hvt_rvt liberty -spec $(RF_16K_65nm_SPEC_FILE);
 	echo "8K RF"
-	cd $(RF_08K_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rf_sp_hdf_hvt_rvt/r0p0/bin/rf_sp_hdf_hvt_rvt all -spec $(RF_08K_SPEC_FILE);
+	cd $(RF_08K_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rf_sp_hdf_hvt_rvt/r0p0/bin/rf_sp_hdf_hvt_rvt all -spec $(RF_08K_65nm_SPEC_FILE);
-	cd $(RF_08K_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rf_sp_hdf_hvt_rvt/r0p0/bin/rf_sp_hdf_hvt_rvt liberty -spec $(RF_08K_SPEC_FILE);
+	cd $(RF_08K_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rf_sp_hdf_hvt_rvt/r0p0/bin/rf_sp_hdf_hvt_rvt liberty -spec $(RF_08K_65nm_SPEC_FILE);
 	cd $(ROM_DIR)
 	echo "Generating ROM Libraries"
-	cd $(ROM_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rom_via_hdd_rvt_rvt/r0p0/bin/rom_via_hdd_rvt_rvt liberty -spec $(ROM_SPEC_FILE) -code_file $(BOOTROM_BIN_FILE);
+	cd $(ROM_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rom_via_hdd_rvt_rvt/r0p0/bin/rom_via_hdd_rvt_rvt liberty -spec $(ROM_65nm_SPEC_FILE) -code_file $(BOOTROM_BIN_FILE);
-	cd $(ROM_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rom_via_hdd_rvt_rvt/r0p0/bin/rom_via_hdd_rvt_rvt all -spec $(ROM_SPEC_FILE) -code_file $(BOOTROM_BIN_FILE);
+	cd $(ROM_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rom_via_hdd_rvt_rvt/r0p0/bin/rom_via_hdd_rvt_rvt all -spec $(ROM_65nm_SPEC_FILE) -code_file $(BOOTROM_BIN_FILE);
 	echo "Finished generating memory libraries"
+gen_memories_frontend_28nm: bootrom
+	@mkdir -p $(MEMORIES_DIR)
+	@mkdir -p $(SRAM_16K_DIR)
+	@mkdir -p $(ROM_DIR)
+	cp $(BOOTROM_BIN_FILE_IN) $(BOOTROM_BIN_FILE)
+	echo "Generating 16K SRAM Memory"
+	cd $(SRAM_16K_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_hvt_mvt/r0p0/bin/sram_sp_hde_hvt_mvt ascii -spec $(SRAM_16K_28nm_SPEC_FILE)
+	cd $(SRAM_16K_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_hvt_mvt/r0p0/bin/sram_sp_hde_hvt_mvt emulation -spec $(SRAM_16K_28nm_SPEC_FILE)
+	cd $(SRAM_16K_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_hvt_mvt/r0p0/bin/sram_sp_hde_hvt_mvt verilog -spec $(SRAM_16K_28nm_SPEC_FILE)
+	cd $(SRAM_16K_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_hvt_mvt/r0p0/bin/sram_sp_hde_hvt_mvt liberty -spec $(SRAM_16K_28nm_SPEC_FILE)
+	echo "Generating ROM Libraries"
+	cd $(ROM_DIR); $(PHYS_IP)/arm/tsmc/cln28ht//rom_via_hdd_2_svt_mvt/r0p0/bin/rom_via_hdd_2_svt_mvt ascii -spec $(ROM_28nm_SPEC_FILE) -code_file $(BOOTROM_BIN_FILE);
+	cd $(ROM_DIR); $(PHYS_IP)/arm/tsmc/cln28ht//rom_via_hdd_2_svt_mvt/r0p0/bin/rom_via_hdd_2_svt_mvt emulation -spec $(ROM_28nm_SPEC_FILE) -code_file $(BOOTROM_BIN_FILE);
+	cd $(ROM_DIR); $(PHYS_IP)/arm/tsmc/cln28ht//rom_via_hdd_2_svt_mvt/r0p0/bin/rom_via_hdd_2_svt_mvt verilog -spec $(ROM_28nm_SPEC_FILE) -code_file $(BOOTROM_BIN_FILE);
+	cd $(ROM_DIR); $(PHYS_IP)/arm/tsmc/cln28ht//rom_via_hdd_2_svt_mvt/r0p0/bin/rom_via_hdd_2_svt_mvt liberty -spec $(ROM_28nm_SPEC_FILE) -code_file $(BOOTROM_BIN_FILE);
+gen_memories_backend_28nm: bootrom
+	@mkdir -p $(MEMORIES_DIR)
+	@mkdir -p $(SRAM_16K_DIR)
+	@mkdir -p $(ROM_DIR)
+	cp $(BOOTROM_BIN_FILE_IN) $(BOOTROM_BIN_FILE)
+	echo "Generating 16K RF Memory"
+	cd $(SRAM_16K_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt lef-fp -spec $(SRAM_16K_28nm_SPEC_FILE)
+	cd $(SRAM_16K_DIR); $(PHYS_IP)/arm/tsmc/cln28ht/sram_sp_hde_2_svt_mvt/r0p0/bin/sram_sp_hde_2_svt_mvt gds2 -spec $(SRAM_16K_28nm_SPEC_FILE)
+	echo "Generating ROM Libraries"
+	cd $(ROM_DIR); $(PHYS_IP)/arm/tsmc/cln28ht//rom_via_hdd_2_svt_mvt/r0p0/bin/rom_via_hdd_2_svt_mvt lef-fp -spec $(ROM_28nm_SPEC_FILE) -code_file $(BOOTROM_BIN_FILE);
+	cd $(ROM_DIR); $(PHYS_IP)/arm/tsmc/cln28ht//rom_via_hdd_2_svt_mvt/r0p0/bin/rom_via_hdd_2_svt_mvt gds2 -spec $(ROM_28nm_SPEC_FILE) -code_file $(BOOTROM_BIN_FILE);
+gen_memories_28nm: gen_memories_frontend_28nm gen_memories_backend_28nm
 convert_mem_to_db: 
 	lc_shell -no_log -f  $(NANOSOC_SYNTH_DIR)/synopsys_lib_conversion.tcl

--- a/makefile
+++ b/makefile
@@ -124,6 +124,45 @@ ifdef ADC_3_INCLUDE
 	FLIST_INCLUDES += $(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/sl_ams_tech/SL_ADC_8bits/flist/sl_adc_8bits_ip.flist
 endif
+ifdef SNPS_PVT_TS_0_INCLUDE
+	NANOSOC_DEFINES += SNPS_PVT_MONITORING SNPS_PVT_TS_0_INCLUDE
+	FLIST_INCLUDES  += $(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/synopsys_28nm_slm_integration/flist/synopsys_pvt_ip.flist
+endif
+ifdef SNPS_PVT_TS_1_INCLUDE
+	NANOSOC_DEFINES += SNPS_PVT_MONITORING SNPS_PVT_TS_1_INCLUDE
+	FLIST_INCLUDES  += $(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/synopsys_28nm_slm_integration/flist/synopsys_pvt_ip.flist
+endif
+ifdef SNPS_PVT_TS_2_INCLUDE
+	NANOSOC_DEFINES += SNPS_PVT_MONITORING SNPS_PVT_TS_2_INCLUDE
+	FLIST_INCLUDES  += $(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/synopsys_28nm_slm_integration/flist/synopsys_pvt_ip.flist
+endif
+ifdef SNPS_PVT_TS_3_INCLUDE
+	NANOSOC_DEFINES += SNPS_PVT_MONITORING SNPS_PVT_TS_3_INCLUDE
+	FLIST_INCLUDES  += $(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/synopsys_28nm_slm_integration/flist/synopsys_pvt_ip.flist
+endif
+ifdef SNPS_PVT_TS_4_INCLUDE
+	NANOSOC_DEFINES += SNPS_PVT_MONITORING SNPS_PVT_TS_4_INCLUDE
+	FLIST_INCLUDES  += $(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/synopsys_28nm_slm_integration/flist/synopsys_pvt_ip.flist
+endif
+ifdef SNPS_PVT_TS_5_INCLUDE
+	NANOSOC_DEFINES += SNPS_PVT_MONITORING SNPS_PVT_TS_5_INCLUDE
+	FLIST_INCLUDES  += $(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/synopsys_28nm_slm_integration/flist/synopsys_pvt_ip.flist
+endif
+ifdef SNPS_PVT_PD_0_INCLUDE
+	NANOSOC_DEFINES += SNPS_PVT_MONITORING SNPS_PVT_PD_0_INCLUDE
+	FLIST_INCLUDES  += $(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/synopsys_28nm_slm_integration/flist/synopsys_pvt_ip.flist
+endif
+ifdef SNPS_PVT_VM_0_INCLUDE
+	NANOSOC_DEFINES += SNPS_PVT_MONITORING SNPS_PVT_VM_0_INCLUDE
+	FLIST_INCLUDES  += $(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/synopsys_28nm_slm_integration/flist/synopsys_pvt_ip.flist
+endif
 # System Design Filelist

--- a/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
+++ b/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
@@ -147,6 +147,10 @@ module nanosoc_region_sysio #(
  wire     [SYS_DATA_W-1:0]   adcsys_hrdata;
  wire                        adcsys_hresp;
+  wire                        pvtsys_hsel;  // ADC subsystem AHB interface signals
+  wire                        pvtsys_hreadyout;
+  wire     [SYS_DATA_W-1:0]   pvtsys_hrdata;
+  wire                        pvtsys_hresp;
  // AHB address decode
@@ -166,6 +170,9 @@ module nanosoc_region_sysio #(
    .sysctrl_hsel (sysctrl_hsel),
  `ifdef AMS_PERIPHERALS
    .adcsys_hsel  (adcsys_hsel),
+  `endif
+  `ifdef SNPS_PVT_MONITORING
+    .pvtsys_hsel  (pvtsys_hsel),
  `endif
    .defslv_hsel  (defslv_hsel)
  );
@@ -174,6 +181,11 @@ module nanosoc_region_sysio #(
 `else 
  parameter AMS_PERIPHERAL_PORT = 0;
 `endif
+`ifdef SNPS_PVT_MONITORING
+  parameter SNPS_PERIPHERAL_PORT = 1;
+`else
+  parameter SNPS_PERIPHERAL_PORT = 0;
+`endif 
  // AHB slave multiplexer
  cmsdk_ahb_slave_mux #(
    .PORT0_ENABLE  (1), // APB subsystem bridge
@@ -182,7 +194,7 @@ module nanosoc_region_sysio #(
    .PORT3_ENABLE  (1), // SYS control
    .PORT4_ENABLE  (1), // Default
    .PORT5_ENABLE  (AMS_PERIPHERAL_PORT), // ADC Region
-    .PORT6_ENABLE  (0),
+    .PORT6_ENABLE  (SNPS_PERIPHERAL_PORT), // Synopsys PVT monitoring region
    .PORT7_ENABLE  (0),
    .PORT8_ENABLE  (0),
    .PORT9_ENABLE  (0),
@@ -215,10 +227,10 @@ module nanosoc_region_sysio #(
    .HREADYOUT5   (adcsys_hreadyout),
    .HRESP5       (adcsys_hresp),
    .HRDATA5      (adcsys_hrdata),
-    .HSEL6        (1'b0),     // Input Port 6
+    .HSEL6        (pvtsys_hsel),     // Input Port 6
-    .HREADYOUT6   (defslv_hreadyout),
+    .HREADYOUT6   (pvtsys_hreadyout),
-    .HRESP6       (defslv_hresp),
+    .HRESP6       (pvtsys_hresp),
-    .HRDATA6      (defslv_hrdata),
+    .HRDATA6      (pvtsys_hrdata),
    .HSEL7        (1'b0),     // Input Port 7
    .HREADYOUT7   (defslv_hreadyout),
    .HRESP7       (defslv_hresp),
@@ -504,4 +516,57 @@ module nanosoc_region_sysio #(
  );
 `endif
+`ifdef SNPS_PVT_MONITORING
+  nanosoc_sysio_snps_pvt_ss #(
+  `ifdef SNPS_PVT_TS_0_INCLUDE
+      .SNPS_PVT_TS_0_ENABLE  (1),
+  `endif 
+  `ifdef SNPS_PVT_TS_1_INCLUDE
+      .SNPS_PVT_TS_1_ENABLE  (1),
+  `endif 
+  `ifdef SNPS_PVT_TS_2_INCLUDE
+      .SNPS_PVT_TS_2_ENABLE  (1),
+  `endif 
+  `ifdef SNPS_PVT_TS_3_INCLUDE
+      .SNPS_PVT_TS_3_ENABLE  (1),
+  `endif 
+  `ifdef SNPS_PVT_TS_4_INCLUDE
+      .SNPS_PVT_TS_4_ENABLE  (1),
+  `endif 
+  `ifdef SNPS_PVT_TS_5_INCLUDE
+      .SNPS_PVT_TS_5_ENABLE  (1),
+  `endif 
+  `ifdef SNPS_PVT_VM_0_INCLUDE
+      .SNPS_PVT_VM_0_ENABLE  (1),
+  `endif 
+  `ifdef SNPS_PVT_PD_0_INCLUDE
+      .SNPS_PVT_PD_0_ENABLE  (1),
+  `endif 
+    .INCLUDE_IRQ_SYNCHRONIZER(0),  // require IRQs to be HCLK synchronous
+    .INCLUDE_APB_TEST_SLAVE  (1),  // Include example test slave
+    .BE                      (BE)
+  ) u_nanosoc_sysio_snps_pvt_ss(
+      .HCLK(HCLK),
+      .HRESETn(HRESETn),
+      .HSEL(pvtsys_hsel),
+      .HADDR(HADDR[15:0]),
+      .HTRANS(HTRANS[1:0]),
+      .HWRITE(HWRITE),
+      .HSIZE(HSIZE),
+      .HPROT(HPROT),
+      .HREADY(HREADY),
+      .HWDATA(HWDATA[31:0]),
+      .HREADYOUT(pvtsys_hreadyout),
+      .HRDATA(pvtsys_hrdata),
+      .HRESP(pvtsys_hresp),
+      .PCLK(PCLK),    // Peripheral clock
+      .PCLKG(PCLKG),   // Gate PCLK for bus interface only
+      .PCLKEN(PCLKEN),  // Clock divider for AHB to APB bridge
+      .PRESETn(PRESETn) // APB reset
+  );
+`endif
 endmodule
--- a/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v
+++ b/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v
@@ -49,7 +49,8 @@ module nanosoc_sysio_decode #(
  parameter BASEADDR_GPIO1       = 32'h4001_1000,
  // Sysctrl base address
  parameter BASEADDR_SYSCTRL     = 32'h4001_f000,
-  parameter BASEADDR_ADC         = 32'h4002_0000
+  parameter BASEADDR_ADC         = 32'h4002_0000,
+  parameter BASEADDR_PVT         = 32'h4002_1000
 )(
    // System Address
    input wire                  hsel,
@@ -62,6 +63,9 @@ module nanosoc_sysio_decode #(
    output wire                 sysctrl_hsel,
  `ifdef AMS_PERIPHERALS
    output wire                 adcsys_hsel,
+  `endif
+  `ifdef SNPS_PVT_MONITORING
+    output wire                 pvtsys_hsel,
  `endif
    // Default slave
    output wire                 defslv_hsel
@@ -88,21 +92,38 @@ module nanosoc_sysio_decode #(
 `ifdef AMS_PERIPHERALS
  assign adcsys_hsel  = hsel & (haddr[31:12]==
                        BASEADDR_ADC[31:12]);     // 0x40020000
+`endif
+`ifdef SNPS_PVT_MONITORING
+  assign pvtsys_hsel  = hsel & (haddr[31:12]==
+                        BASEADDR_PVT[31:12]);     // 0x40021000
 `endif
  // ----------------------------------------------------------
  // Default slave decode logic
  // ----------------------------------------------------------
 `ifdef AMS_PERIPHERALS
-  assign defslv_hsel  = ~(apbsys_hsel |
+  `ifdef SNPS_PVT_MONITORING
-                          gpio0_hsel   | gpio1_hsel  |
+    assign defslv_hsel  = ~(apbsys_hsel |
-                          sysctrl_hsel | adcsys_hsel
+                            gpio0_hsel   | gpio1_hsel  |
-                         );
+                            sysctrl_hsel | adcsys_hsel | pvtsys_hsel
+                          );
+  `else 
+    assign defslv_hsel  = ~(apbsys_hsel |
+                            gpio0_hsel   | gpio1_hsel  |
+                            sysctrl_hsel | adcsys_hsel
+                          );
+  `endif
 `else
-  assign defslv_hsel  = ~(apbsys_hsel |
+  `ifdef SNPS_PVT_MONITORING
-                          gpio0_hsel   | gpio1_hsel  |
+    assign defslv_hsel  = ~(apbsys_hsel |
-                          sysctrl_hsel
+                            gpio0_hsel   | gpio1_hsel  |
-                         );
+                            sysctrl_hsel | pvtsys_hsel
+                          );
+  `else 
+    assign defslv_hsel  = ~(apbsys_hsel |
+                            gpio0_hsel   | gpio1_hsel  |
+                            sysctrl_hsel
+                          );
+  `endif
 `endif
 endmodule
--- a/synopsys_28nm_slm_integration @ 5ece300b
+++ b/synopsys_28nm_slm_integration @ 5ece300b
+Subproject commit 5ece300bcb4e7dd8cd0c4cc141e7faa8f42e3e23
--- a/projbranch
+++ b/projbranch
@@ -13,4 +13,5 @@
 nanosoc/slcorem0_tech: main
 nanosoc/sldma230_tech: main
 nanosoc/socdebug_tech: main
 nanosoc/sldma350_tech: main
\ No newline at end of file
+nanosoc/sl_ams_tech: main
\ No newline at end of file
--- a/software/common/validation/snps_pvt_tests.c
+++ b/software/common/validation/snps_pvt_tests.c
+/*
+ *-----------------------------------------------------------------------------
+ * The confidential and proprietary information contained in this file may
+ * only be used by a person authorised under and to the extent permitted
+ * by a subsisting licensing agreement from Arm Limited or its affiliates.
+ *
+ *            (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+ *                ALL RIGHTS RESERVED
+ *
+ * This entire notice must be reproduced on all copies of this file
+ * and copies of this file may only be made by a person if such person is
+ * permitted to do so under the terms of a subsisting license agreement
+ * from Arm Limited or its affiliates.
+ *
+ *      SVN Information
+ *
+ *      Checked In          : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+ *
+ *      Revision            : $Revision: 371321 $
+ *
+ *      Release Information : Cortex-M System Design Kit-r1p1-00rel0
+ *-----------------------------------------------------------------------------
+ */
+/*
+  A simple test to check the operation of APB slave multiplexer
+*/
+#ifdef CORTEX_M0
+#include "CMSDK_CM0.h"
+#endif
+#ifdef CORTEX_M0PLUS
+#include "CMSDK_CM0plus.h"
+#endif
+#ifdef CORTEX_M3
+#include "CMSDK_CM3.h"
+#endif
+#ifdef CORTEX_M4
+#include "CMSDK_CM4.h"
+#endif
+#include <stdio.h>
+#include "uart_stdout.h"
+#define HW32_REG(ADDRESS)  (*((volatile unsigned long  *)(ADDRESS)))
+#define HW16_REG(ADDRESS)  (*((volatile unsigned short *)(ADDRESS)))
+#define HW8_REG(ADDRESS)   (*((volatile unsigned char  *)(ADDRESS)))
+int snps_pvt_ts_detect(void);
+int snps_pvt_pd_detect(void);
+int ts0_check_registers(void);
+int pd0_check_registers(void);
+#if defined ( __CC_ARM   )
+__asm void          address_test_write(unsigned int addr, unsigned int wdata);
+__asm unsigned int  address_test_read(unsigned int addr);
+#else
+      void          address_test_write(unsigned int addr, unsigned int wdata);
+      unsigned int  address_test_read(unsigned int addr);
+#endif
+void                HardFault_Handler_c(unsigned int * hardfault_args, unsigned lr_value);
+int                 APB_test_slave_Check(unsigned int offset);
+/* Global variables */
+volatile int hardfault_occurred;
+volatile int hardfault_expected;
+volatile int temp_data;
+         int hardfault_verbose=0; // 0:Not displaying anything in hardfault handler
+#define SNPS_PVT_BASE          (0x40021000UL)
+#define SNPS_TS_0_BASE        (SNPS_PVT_BASE + 0x0000UL)
+#define SNPS_TS_1_BASE        (SNPS_PVT_BASE + 0x0010UL)
+#define SNPS_TS_2_BASE        (SNPS_PVT_BASE + 0x0020UL)
+#define SNPS_TS_3_BASE        (SNPS_PVT_BASE + 0x0030UL)
+#define SNPS_TS_4_BASE        (SNPS_PVT_BASE + 0x0040UL)
+#define SNPS_TS_5_BASE        (SNPS_PVT_BASE + 0x0050UL)
+#define SNPS_PD_0_BASE        (SNPS_PVT_BASE + 0x0060UL)
+#define SNPS_VM_0_BASE        (SNPS_PVT_BASE + 0x0060UL)
+int main (void)
+{
+  int err_code = 0;
+  int data[64];
+  int i;
+  // UART init
+  UartStdOutInit();
+  // Test banner message and revision number
+  puts("\nCortex Microcontroller System Design Kit");
+  puts(" - Synopsys PVT test - revision $Revision: 371321 $\n");
+  if(snps_pvt_pd_detect()==0) {
+    err_code += pd0_check_registers();
+  }
+  printf("\n\n ************************************ \n\n");
+  if((snps_pvt_ts_detect()==0)) {
+    err_code += ts0_check_registers();
+  }
+  if (err_code==0) {
+    printf ("\n** TEST PASSED **\n");
+  } else {
+    printf ("\n** TEST FAILED **, Error code = (0x%x)\n", err_code);
+  }
+  UartEndSimulation();
+  return 0;
+}
+int ts0_check_registers(void)
+{
+  uint32_t ts0_reg;
+  float temperature;
+  float K=81.1;
+  float Y=237.5;
+  puts("Testing status read/write access \n");
+  ts0_reg = address_test_read(SNPS_TS_0_BASE + 0x000);
+  printf("Status after reset: 0x%08X \n", ts0_reg);
+  ts0_reg = ts0_reg ^ 1;
+  address_test_write(SNPS_TS_0_BASE, ts0_reg);
+  ts0_reg = address_test_read(SNPS_TS_0_BASE);
+  printf("Status register after enable: 0x%08X \n", ts0_reg);
+  while(!(address_test_read(SNPS_TS_0_BASE)&0x10)){;}
+  printf("TS reset released \n");
+  ts0_reg = address_test_read(SNPS_TS_0_BASE);
+  ts0_reg = ts0_reg ^ 2;
+  address_test_write(SNPS_TS_0_BASE, ts0_reg);
+  printf("TS Run enabled \n");
+  while(!(address_test_read(SNPS_TS_0_BASE)&0x1000000)){;}
+  ts0_reg = address_test_read(SNPS_TS_0_BASE + 0x04);
+  temperature = (ts0_reg*Y/4094) - K;
+  printf("Temperature read data: 0x%08X = %f\n", ts0_reg,temperature);
+  // Clear ready reg
+  ts0_reg = address_test_read(SNPS_TS_0_BASE);
+  ts0_reg = ts0_reg ^ 0x8;
+  address_test_write(SNPS_TS_0_BASE, ts0_reg);
+  ts0_reg = address_test_read(SNPS_TS_0_BASE);
+  printf("Status register after clear ready: 0x%08X \n", ts0_reg);
+  // Enable continuous running
+  ts0_reg = ts0_reg ^ 0x4;
+  address_test_write(SNPS_TS_0_BASE, ts0_reg);
+  printf("TS Run continuous enabled \n");
+  while(!(address_test_read(SNPS_TS_0_BASE)&0x1000000)){;}
+  ts0_reg = address_test_read(SNPS_TS_0_BASE + 0x04);
+  temperature = (ts0_reg*Y/4094) - K;
+  printf("Temperature 1 read data: 0x%08X = %f\n", ts0_reg,temperature);
+  // Clear ready reg
+  ts0_reg = address_test_read(SNPS_TS_0_BASE);
+  ts0_reg = ts0_reg ^ 0x8;
+  address_test_write(SNPS_TS_0_BASE, ts0_reg);
+  while(!(address_test_read(SNPS_TS_0_BASE)&0x1000000)){;}
+  ts0_reg = address_test_read(SNPS_TS_0_BASE + 0x04);
+  temperature = (ts0_reg*Y/4094) - K;
+  printf("Temperature 2 read data: 0x%08X = %f\n", ts0_reg,temperature);
+  // Clear ready and continuous read
+  ts0_reg = address_test_read(SNPS_TS_0_BASE);
+  ts0_reg = ts0_reg ^ 0xC;
+  address_test_write(SNPS_TS_0_BASE, ts0_reg);
+  ts0_reg = address_test_read(SNPS_TS_0_BASE);
+  return 0;
+}
+int pd0_check_registers(void){
+  uint32_t pd0_reg;
+  uint32_t pd2_reg;
+  float frequency;
+  int prescaler = 32;
+  int window_size = 63;
+  float f_clk = 6;
+  puts("Testing PD0 status read/write access \n");
+  pd2_reg = address_test_read(SNPS_PD_0_BASE + 0x008);
+  printf("Config regs after reset: 0x%08X \n", pd2_reg);
+  // Enable PD
+  pd0_reg = address_test_read(SNPS_PD_0_BASE);
+  pd0_reg = pd0_reg ^ 1;
+  address_test_write(SNPS_PD_0_BASE, pd0_reg);
+  pd0_reg = address_test_read(SNPS_PD_0_BASE);
+  printf("Status register after enable: 0x%08X \n", pd0_reg);
+  while(!(address_test_read(SNPS_PD_0_BASE)&0x10)){;}
+  printf("PD reset released \n");
+  pd2_reg = pd2_reg ^ 0x1000000;
+  address_test_write(SNPS_PD_0_BASE + 0x008, pd2_reg);
+  pd2_reg = address_test_read(SNPS_PD_0_BASE + 0x008);
+  printf("Config regs after config load: 0x%08X \n", pd2_reg);
+  pd2_reg = pd2_reg ^ 0x1000000;
+  address_test_write(SNPS_PD_0_BASE + 0x008, pd2_reg);
+  pd0_reg = address_test_read(SNPS_PD_0_BASE);
+  pd0_reg = pd0_reg ^ 2;
+  address_test_write(SNPS_PD_0_BASE, pd0_reg);
+  printf("PD Run enabled \n");
+  while(!(address_test_read(SNPS_PD_0_BASE)&0x1000000)){;}
+  pd0_reg = address_test_read(SNPS_PD_0_BASE + 0x04); // Read Data register
+  frequency = pd0_reg * prescaler * f_clk / window_size;
+  printf("PD read data: 0x%08X = %f \n", pd0_reg, frequency);
+  // Clear ready reg
+  pd0_reg = address_test_read(SNPS_PD_0_BASE);
+  pd0_reg = pd0_reg ^ 0x8;
+  address_test_write(SNPS_PD_0_BASE, pd0_reg);
+  // Disable PD0
+  pd0_reg = address_test_read(SNPS_PD_0_BASE);
+  pd0_reg = pd0_reg ^ 1;
+  address_test_write(SNPS_PD_0_BASE,pd0_reg);
+  printf("Disabled PD0 \n");
+  return 0;
+}
+int snps_pvt_ts_detect(void)
+{
+  int result;
+  int volatile rdata;
+  unsigned const int ts0_id     = 0x736E7473;
+  puts("Detect if TS0 is present...");
+  hardfault_occurred = 0;
+  hardfault_expected = 1;
+  rdata = address_test_read(SNPS_TS_0_BASE+ 0xC);
+  printf("TS0 ID: 0x%08X\n", rdata);
+  hardfault_expected = 0;
+  result = hardfault_occurred? 1 : 0;
+  hardfault_occurred = 0;
+  result = rdata == ts0_id? 0: 1;
+  if (result!=0) {
+    puts("** TEST SKIPPED ** TS0 is not present.\n");
+    UartEndSimulation();
+  }
+  return(result);
+}
+int snps_pvt_pd_detect(void)
+{
+  int result;
+  int volatile rdata;
+  unsigned const int pd0_id     = 0x736E7064;
+  puts("Detect if PD0 is present...");
+  hardfault_occurred = 0;
+  hardfault_expected = 1;
+  rdata = address_test_read(SNPS_PD_0_BASE+ 0xC);
+  printf("PD0 ID: 0x%08X\n", rdata);
+  hardfault_expected = 0;
+  result = hardfault_occurred? 1 : 0;
+  hardfault_occurred = 0;
+  result = rdata == pd0_id? 0: 1;
+  if (result!=0) {
+    puts("** TEST SKIPPED ** PD0 is not present.\n");
+    UartEndSimulation();
+  }
+  return(result);
+}
+#if defined ( __CC_ARM   )
+/* Test function for write - for ARM / Keil */
+__asm void address_test_write(unsigned int addr, unsigned int wdata)
+{
+  STR    R1,[R0]
+  DSB    ; Ensure bus fault occurred before leaving this subroutine
+  BX     LR
+}
+#else
+/* Test function for write - for gcc */
+void address_test_write(unsigned int addr, unsigned int wdata) __attribute__((naked));
+void address_test_write(unsigned int addr, unsigned int wdata)
+{
+  __asm("  str   r1,[r0]\n"
+        "  dsb          \n"
+        "  bx    lr     \n"
+  );
+}
+#endif
+/* Test function for read */
+#if defined ( __CC_ARM   )
+/* Test function for read - for ARM / Keil */
+__asm unsigned int address_test_read(unsigned int addr)
+{
+  LDR    R1,[R0]
+  DSB    ; Ensure bus fault occurred before leaving this subroutine
+  MOVS   R0, R1
+  BX     LR
+}
+#else
+/* Test function for read - for gcc */
+unsigned int  address_test_read(unsigned int addr) __attribute__((naked));
+unsigned int  address_test_read(unsigned int addr)
+{
+  __asm("  ldr   r1,[r0]\n"
+        "  dsb          \n"
+        "  movs  r0, r1 \n"
+        "  bx    lr     \n"
+  );
+}
+#endif
+#if defined ( __CC_ARM   )
+/* ARM or Keil toolchain */
+__asm void HardFault_Handler(void)
+{
+  MOVS   r0, #4
+  MOV    r1, LR
+  TST    r0, r1
+  BEQ    stacking_used_MSP
+  MRS    R0, PSP ; // first parameter - stacking was using PSP
+  B      get_LR_and_branch
+stacking_used_MSP
+  MRS    R0, MSP ; // first parameter - stacking was using MSP
+get_LR_and_branch
+  MOV    R1, LR  ; // second parameter is LR current value
+  LDR    R2,=__cpp(HardFault_Handler_c)
+  BX     R2
+  ALIGN
+}
+#else
+/* gcc toolchain */
+void HardFault_Handler(void) __attribute__((naked));
+void HardFault_Handler(void)
+{
+  __asm("  movs   r0,#4\n"
+        "  mov    r1,lr\n"
+        "  tst    r0,r1\n"
+        "  beq    stacking_used_MSP\n"
+        "  mrs    r0,psp\n" /*  first parameter - stacking was using PSP */
+        "  ldr    r1,=HardFault_Handler_c  \n"
+        "  bx     r1\n"
+        "stacking_used_MSP:\n"
+        "  mrs    r0,msp\n" /*  first parameter - stacking was using PSP */
+        "  ldr    r1,=HardFault_Handler_c  \n"
+        "  bx     r1\n"
+        ".pool\n" );
+}
+#endif
+/* C part of the fault handler - common between ARM / Keil /gcc */
+void HardFault_Handler_c(unsigned int * hardfault_args, unsigned lr_value)
+{
+  unsigned int stacked_pc;
+  unsigned int stacked_r0;
+  hardfault_occurred++;
+  if (hardfault_verbose) puts ("[Hard Fault Handler]");
+  if (hardfault_expected==0) {
+    puts ("ERROR : Unexpected HardFault interrupt occurred.\n");
+    UartEndSimulation();
+    while (1);
+    }
+  stacked_r0  = ((unsigned long) hardfault_args[0]);
+  stacked_pc  = ((unsigned long) hardfault_args[6]);
+  if (hardfault_verbose)  printf(" - Stacked R0 : 0x%x\n", stacked_r0);
+  if (hardfault_verbose)  printf(" - Stacked PC : 0x%x\n", stacked_pc);
+  /* Modify R0 to a valid address */
+  hardfault_args[0] = (unsigned long) &temp_data;
+  return;
+}
--- a/testcodes/snps_pvt_tests/makefile
+++ b/testcodes/snps_pvt_tests/makefile
+#-----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+#            (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+#                ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#
+#      SVN Information
+#
+#      Checked In          : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+#
+#      Revision            : $Revision: 371321 $
+#
+#      Release Information : Cortex-M System Design Kit-r1p1-00rel0
+#-----------------------------------------------------------------------------
+#
+# Cortex-M System Design Kit software compilation make file
+#
+#-----------------------------------------------------------------------------
+#
+#  Configurations
+#
+# Choose the core instantiated, can be
+#  - CORTEX_M0
+#  - CORTEX_M0PLUS
+CPU_PRODUCT = CORTEX_M0PLUS
+TARGET = arm-none-eabi
+# Shared software directory
+SOFTWARE_DIR = $(SOCLABS_NANOSOC_TECH_DIR)/software
+CMSIS_DIR    = $(SOFTWARE_DIR)/cmsis
+CORE_DIR     = $(CMSIS_DIR)/CMSIS/Include
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+  DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0plus
+else
+  DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0
+endif
+# Program file
+TESTNAME     = snps_pvt_tests
+# Endian Option
+COMPILE_BIGEND  = 0
+# Configuration
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+  USER_DEFINE    = -DCORTEX_M0PLUS
+else
+  USER_DEFINE    = -DCORTEX_M0
+endif
+DEPS_LIST        = makefile
+# Tool chain : ds5 / gcc / keil
+TOOL_CHAIN      = ds5
+ifeq ($(TOOL_CHAIN),ds5)
+  ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+    CPU_TYPE        = --cpu Cortex-M0plus
+  else
+    CPU_TYPE        = --cpu Cortex-M0
+  endif
+endif
+ifeq ($(TOOL_CHAIN),ds6)
+  ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+    CPU_TYPE        = -mcpu=Cortex-M0plus
+  else
+    CPU_TYPE        = -mcpu=Cortex-M0
+  endif
+endif
+ifeq ($(TOOL_CHAIN),gcc)
+  ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+    CPU_TYPE        = -mcpu=cortex-m0plus
+  else
+    CPU_TYPE        = -mcpu=cortex-m0
+  endif
+endif
+# Startup code directory for DS-5
+ifeq ($(TOOL_CHAIN),ds5)
+ STARTUP_DIR  = $(DEVICE_DIR)/Source/ARM
+endif
+ifeq ($(TOOL_CHAIN),ds6)
+ STARTUP_DIR  = $(DEVICE_DIR)/Source/ARM
+endif
+# Startup code directory for gcc
+ifeq ($(TOOL_CHAIN),gcc)
+ STARTUP_DIR  = $(DEVICE_DIR)/Source/GCC
+endif
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+  STARTUP_FILE = startup_CMSDK_CM0plus
+  SYSTEM_FILE  = system_CMSDK_CM0plus
+else
+  STARTUP_FILE = startup_CMSDK_CM0
+  SYSTEM_FILE  = system_CMSDK_CM0
+endif
+# ---------------------------------------------------------------------------------------
+# D5-5 options
+# MicroLIB option
+COMPILE_MICROLIB = 0
+# Small Multiply (Cortex-M0/M0+ has small multiplier option)
+COMPILE_SMALLMUL = 0
+ifeq ($(TOOL_CHAIN),ds6)
+  ARM_TARGET = --target=arm-$(TARGET)
+  CC_TOOL   = armclang -O1
+  ASM_TOOL = armclang -masm=armasm $(ARM_TARGET) -c
+else
+  CC_TOOL   = armcc -O3
+  ASM_TOOL = armasm
+  ARM_TARGET = -Otime
+endif
+ARM_CC_OPTIONS   = $(ARM_TARGET) -c -g -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+		   -I $(SOFTWARE_DIR)/common/retarget $(USER_DEFINE)
+ARM_ASM_OPTIONS  = -g
+ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
+		   --rw_base 0x30000000 --ro_base 0x00000000 --map
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ ARM_CC_OPTIONS   += --bigend
+ ARM_ASM_OPTIONS  += --bigend
+ ARM_LINK_OPTIONS += --be8
+endif
+ifeq ($(COMPILE_MICROLIB),1)
+ # MicroLIB
+ ARM_CC_OPTIONS   += --library_type=microlib
+ ARM_ASM_OPTIONS  += --library_type=microlib --pd "__MICROLIB SETA 1"
+ ARM_LINK_OPTIONS += --library_type=microlib
+endif
+ifeq ($(COMPILE_SMALLMUL),1)
+ # In Cortex-M0, small multiply takes 32 cycles
+ ARM_CC_OPTIONS   += --multiply_latency=32
+endif
+# ---------------------------------------------------------------------------------------
+# gcc options
+GNG_CC      = $(TARGET)-gcc
+GNU_OBJDUMP = $(TARGET)-objdump
+GNU_OBJCOPY = $(TARGET)-objcopy
+LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts
+LINKER_SCRIPT = $(LINKER_SCRIPT_PATH)/cmsdk_cm0.ld
+GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE)
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ GNU_CC_FLAGS   += -mbig-endian
+endif
+# ---------------------------------------------------------------------------------------
+all: all_$(TOOL_CHAIN)
+# ---------------------------------------------------------------------------------------
+# DS-5
+all_ds5 : $(TESTNAME).hex $(TESTNAME).lst
+all_ds6 : $(TESTNAME).hex $(TESTNAME).lst
+$(TESTNAME).o :  $(SOFTWARE_DIR)/common/validation/$(TESTNAME).c $(DEPS_LIST)
+	$(CC_TOOL) $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o  $@
+$(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST)
+	$(CC_TOOL) $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o  $@
+retarget.o : $(SOFTWARE_DIR)/common/retarget/retarget.c $(DEPS_LIST)
+	$(CC_TOOL) $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o  $@
+uart_stdout.o : $(SOFTWARE_DIR)/common/retarget/uart_stdout.c $(DEPS_LIST)
+	$(CC_TOOL) $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o  $@
+$(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST)
+	$(ASM_TOOL) $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o  $@
+$(TESTNAME).ELF : $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
+	armlink $(ARM_LINK_OPTIONS) -o $@  $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
+$(TESTNAME).hex : $(TESTNAME).ELF
+	fromelf --vhx --8x1 $< --output  $@
+$(TESTNAME).lst : $(TESTNAME).ELF makefile
+	fromelf -c -d -e -s $< --output  $@
+# ---------------------------------------------------------------------------------------
+# gcc
+all_gcc:
+	$(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \
+		$(SOFTWARE_DIR)/common/validation/$(TESTNAME).c \
+		$(SOFTWARE_DIR)/common/retarget/retarget.c \
+		$(SOFTWARE_DIR)/common/retarget/uart_stdout.c \
+		$(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \
+		-I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+                -I $(SOFTWARE_DIR)/common/retarget  \
+		-L $(LINKER_SCRIPT_PATH) \
+		-D__STACK_SIZE=0x200 \
+		-D__HEAP_SIZE=0x1000 \
+		$(USER_DEFINE) -T $(LINKER_SCRIPT) -o $(TESTNAME).o
+	# Generate disassembly code
+	$(GNU_OBJDUMP) -S $(TESTNAME).o > $(TESTNAME).lst
+	# Generate binary file
+	$(GNU_OBJCOPY) -S $(TESTNAME).o -O binary $(TESTNAME).bin
+	# Generate hex file
+	$(GNU_OBJCOPY) -S $(TESTNAME).o -O verilog $(TESTNAME).hex
+# Note:
+# If the version of object copy you are using does not support verilog hex file output,
+# you can generate the hex file from binary file using the following command
+#       od -v -A n -t x1 --width=1  $(TESTNAME).bin > $(TESTNAME).hex
+# ---------------------------------------------------------------------------------------
+# Keil MDK
+all_keil:
+	@echo "Please compile your project code and press ENTER when ready"
+	@read dummy
+# ---------------------------------------------------------------------------------------
+# Binary
+all_bin: $(TESTNAME).bin
+	# Generate hex file from binary
+	od -v -A n -t x1 --width=1  $(TESTNAME).bin > $(TESTNAME).hex
+# ---------------------------------------------------------------------------------------
+# Clean
+clean :
+	@rm -rf *.o
+	@if [ -e $(TESTNAME).hex ] ; then \
+	  rm -rf $(TESTNAME).hex ; \
+	fi
+	@if [ -e $(TESTNAME).lst ] ; then \
+	  rm -rf $(TESTNAME).lst ; \
+	fi
+	@if [ -e $(TESTNAME).ELF ] ; then \
+	  rm -rf $(TESTNAME).ELF ; \
+	fi
+	@if [ -e $(TESTNAME).bin ] ; then \
+	  rm -rf $(TESTNAME).bin ; \
+	fi
+	@rm -rf *.crf
+	@rm -rf *.plg
+	@rm -rf *.tra
+	@rm -rf *.htm
+	@rm -rf *.map
+	@rm -rf *.dep
+	@rm -rf *.d
+	@rm -rf *.lnp
+	@rm -rf *.bak
+	@rm -rf *.lst
+	@rm -rf *.axf
+	@rm -rf *.sct
+	@rm -rf *.__i
+	@rm -rf *._ia
--- a/testcodes/snps_pvt_tests/snps_pvt_tests.hex
+++ b/testcodes/snps_pvt_tests/snps_pvt_tests.hex