Initial Update for 65nm and 28nm flows + synopsys SLM integration

.gitmodules

@@ -13,3 +13,6 @@
 [submodule "nanosoc/sl_ams_tech"]
 	path = nanosoc/sl_ams_tech
 	url = https://git.soton.ac.uk/soclabs/sl_ams_tech.git
+[submodule "nanosoc/synopsys_28nm_slm_integration"]
+	path = nanosoc/synopsys_28nm_slm_integration
+	url = https://git.soton.ac.uk/soclabs/synopsys_28nm_slm_integration.git

ASIC/TSMC28nm/no_pins/Synopsys_FC/design_setup.tcl

+set sc9mcpp240z_base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc9mcpp140z_base_svt_c35/r0p0
+set cln28ht_tech_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0
+
+create_lib nanosoc_chip_pads.dlib \
+    -technology $cln28ht_tech_path/milkyway/1p9m_5x1y2z_utalrdl/sc9mcpp140z_tech.tf \
+    -ref_libs {./cln28ht_sc9mcpp140z/}
+
+source $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/dc_flist.tcl
+analyze -format verilog $env(SOCLABS_PROJECT_DIR)/nanosoc_tech/nanosoc/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v
+
+elaborate nanosoc_chip_pads
+set_top_module nanosoc_chip_pads
\ No newline at end of file

ASIC/TSMC28nm/no_pins/Synopsys_FC/fc_output.txt

+ 
+                              Fusion Compiler (TM)
+
+                  Version U-2022.12 for linux64 - Dec 11, 2022
+  This release has significant feature enhancements. Please review the Release
+                       Notes associated with this release.
+
+                    Copyright (c) 1988 - 2022 Synopsys, Inc.
+   This software and the associated documentation are proprietary to Synopsys,
+ Inc. This software may only be used in accordance with the terms and conditions
+ of a written license agreement with Synopsys, Inc. All other use, reproduction,
+   or distribution of this software is strictly prohibited.  Licensed Products
+     communicate with Synopsys servers for the purpose of providing software
+    updates, detecting software piracy and verifying that customers are using
+    Licensed Products in conformity with the applicable License Key for such
+  Licensed Products. Synopsys will use information gathered in connection with
+    this process to deliver software updates and pursue software pirates and
+                                   infringers.
+
+ Inclusivity & Diversity - Visit SolvNetPlus to read the "Synopsys Statement on
+            Inclusivity and Diversity" (Refer to article 000036315 at
+                        https://solvnetplus.synopsys.com)
+
+Loading user preference file /home/dwn1c21/.synopsys_fc_gui/preferences.tcl
+Error: Message for 'CLE-10' not found
+fc_shell> exit
+Maximum memory usage for this session: 315.86 MB
+Maximum memory usage for this session including child processes: 315.86 MB
+CPU usage for this session:     11 seconds (  0.00 hours)
+Elapsed time for this session:     39 seconds (  0.01 hours)
+Thank you for using Fusion Compiler.
+

ASIC/TSMC28nm/no_pins/Synopsys_FC/lm_output.txt

+ 
+                              Library Manager (TM)
+
+                  Version U-2022.12 for linux64 - Dec 11, 2022
+  This release has significant feature enhancements. Please review the Release
+                       Notes associated with this release.
+
+                    Copyright (c) 1988 - 2022 Synopsys, Inc.
+   This software and the associated documentation are proprietary to Synopsys,
+ Inc. This software may only be used in accordance with the terms and conditions
+ of a written license agreement with Synopsys, Inc. All other use, reproduction,
+   or distribution of this software is strictly prohibited.  Licensed Products
+     communicate with Synopsys servers for the purpose of providing software
+    updates, detecting software piracy and verifying that customers are using
+    Licensed Products in conformity with the applicable License Key for such
+  Licensed Products. Synopsys will use information gathered in connection with
+    this process to deliver software updates and pursue software pirates and
+                                   infringers.
+
+ Inclusivity & Diversity - Visit SolvNetPlus to read the "Synopsys Statement on
+            Inclusivity and Diversity" (Refer to article 000036315 at
+                        https://solvnetplus.synopsys.com)
+
+Error: Message for 'CLE-10' not found
+lm_shell> set sc9mcpp140z_base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc9mcpp140z_base_svt_c35/r0p0
+/home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc9mcpp140z_base_svt_c35/r0p0
+lm_shell> set cln28ht_tech_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0
+/home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0
+lm_shell> 
+lm_shell> set cln28ht_tech_file   $cln28ht_tech_path/milkyway/1p9m_5x1y2z_utalrdl/sc9mcpp140z_tech.tf
+/home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0/milkyway/1p9m_5x1y2z_utalrdl/sc9mcpp140z_tech.tf
+lm_shell> set cln28ht_lef_file    $cln28ht_tech_path/lef/1p9m_5x1y2z_utalrdl/sc9mcpp140z_tech.lef
+/home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0/lef/1p9m_5x1y2z_utalrdl/sc9mcpp140z_tech.lef
+lm_shell> 
+lm_shell> set sc9mcpp140z_lef_file    $sc9mcpp140z_base_path/lef/sc9mcpp140z_cln28ht_base_svt_c35.lef
+/home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc9mcpp140z_base_svt_c35/r0p0/lef/sc9mcpp140z_cln28ht_base_svt_c35.lef
+lm_shell> set sc9mcpp140z_gds_file    $sc9mcpp140z_base_path/gds2/sc9mcpp140z_cln28ht_base_svt_c35.gds2
+/home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc9mcpp140z_base_svt_c35/r0p0/gds2/sc9mcpp140z_cln28ht_base_svt_c35.gds2
+lm_shell> set sc9mcpp140z_db_file     $sc9mcpp140z_base_path/db/sc9mcpp140z_cln28ht_base_svt_c35_ssg_cworstt_max_0p81v_125c.db
+/home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc9mcpp140z_base_svt_c35/r0p0/db/sc9mcpp140z_cln28ht_base_svt_c35_ssg_cworstt_max_0p81v_125c.db
+lm_shell> set sc9mcpp140z_antenna_file   $sc9mcpp140z_base_path/milkyway/1p9m_5x1y2z_utalrdl/sc9mcpp140z_cln28ht_base_svt_c35_antenna.clf
+/home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc9mcpp140z_base_svt_c35/r0p0/milkyway/1p9m_5x1y2z_utalrdl/sc9mcpp140z_cln28ht_base_svt_c35_antenna.clf
+lm_shell> exit
+Maximum memory usage for this session: 82.41 MB
+CPU usage for this session:      2 seconds (  0.00 hours)
+Elapsed time for this session:     14 seconds (  0.00 hours)
+Thank you for using Library Manager.
+

ASIC/TSMC28nm/no_pins/Synopsys_FC/synopsys_lib_conversion.tcl

+set sc9mcpp140z_base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/sc9mcpp140z_base_svt_c35/r0p0
+set cln28ht_tech_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln28ht/arm_tech/r1p0
+
+set cln28ht_tech_file   $cln28ht_tech_path/milkyway/1p9m_5x1y2z_utalrdl/sc9mcpp140z_tech.tf
+set cln28ht_lef_file    $cln28ht_tech_path/lef/1p9m_5x1y2z_utalrdl/sc9mcpp140z_tech.lef
+
+set sc9mcpp140z_lef_file    $sc9mcpp140z_base_path/lef/sc9mcpp140z_cln28ht_base_svt_c35.lef
+set sc9mcpp140z_gds_file    $sc9mcpp140z_base_path/gds2/sc9mcpp140z_cln28ht_base_svt_c35.gds2
+set sc9mcpp140z_db_file     $sc9mcpp140z_base_path/db/sc9mcpp140z_cln28ht_base_svt_c35_ssg_cworstt_max_0p81v_125c.db
+set sc9mcpp140z_antenna_file   $sc9mcpp140z_base_path/milkyway/1p9m_5x1y2z_utalrdl/sc9mcpp140z_cln28ht_base_svt_c35_antenna.clf
+
+create_physical_lib -technology $cln28ht_tech_file cln28ht
+read_lef -library cln28ht $sc9mcpp140z_lef_file
+read_gds -library cln28ht $sc9mcpp140z_gds_file
+set_cell_site -site_def unit
+update_physical_properties -library cln28ht -format clf -file $sc9mcpp140z_antenna_file
+
+update_physical_properties -library cln28ht -format db -file $sc9mcpp140z_db_file
+create_frame
+
+set_app_options -name
+
+write_physical_lib -output cln28ht.ndm
+report_lib -all cln28ht 
+
+set_check_library_options -logic_vs_physical -physical 
+check_library -physical_library_name cln28ht -logic_library_name $sc9mcpp140z_db_file
\ No newline at end of file

ASIC/TSMC28nm/rom_via.spec

+# user spec file, compiler rom_via_hdd_2_svt_mvt, version r0p0
+
+activity_factor = 5
+back_biasing = off
+bits = 32
+bmux = on
+bus_notation = on
+check_instname = off
+code_file = $SOCLABS_NANOSOC_TECH_DIR/testcodes/bootloader/bootloader.bin
+corners = ffg_cbestt_0p77v_0p77v_0c,ffg_cbestt_0p77v_0p77v_125c,ffg_cbestt_0p77v_0p77v_m40c,ffg_cbestt_0p88v_0p88v_0c,ffg_cbestt_0p88v_0p88v_125c,ffg_cbestt_0p88v_0p88v_m40c,ffg_cbestt_0p99v_0p99v_0c,ffg_cbestt_0p99v_0p99v_125c,ffg_cbestt_0p99v_0p99v_m40c,ffg_cbestt_1p05v_1p05v_0c,ffg_cbestt_1p05v_1p05v_125c,ffg_cbestt_1p05v_1p05v_m40c,ffg_ctypical_0p70v_0p70v_85c,ffg_ctypical_0p90v_0p90v_85c,ffg_ctypical_0p99v_0p99v_125c,ffg_ctypical_1p00v_1p00v_85c,ffg_ctypical_1p05v_1p05v_125c,ssg_cworstt_0p63v_0p63v_0c,ssg_cworstt_0p63v_0p63v_125c,ssg_cworstt_0p63v_0p63v_m40c,ssg_cworstt_0p72v_0p72v_0c,ssg_cworstt_0p72v_0p72v_125c,ssg_cworstt_0p72v_0p72v_m40c,ssg_cworstt_0p81v_0p81v_0c,ssg_cworstt_0p81v_0p81v_125c,ssg_cworstt_0p81v_0p81v_m40c,ssg_cworstt_0p90v_0p90v_0c,ssg_cworstt_0p90v_0p90v_125c,ssg_cworstt_0p90v_0p90v_m40c,tt_ctypical_0p63v_0p63v_0c,tt_ctypical_0p70v_0p70v_85c,tt_ctypical_0p72v_0p72v_0c,tt_ctypical_0p80v_0p80v_85c,tt_ctypical_0p81v_0p81v_0c,tt_ctypical_0p90v_0p90v_0c,tt_ctypical_0p90v_0p90v_125c,tt_ctypical_0p90v_0p90v_25c,tt_ctypical_0p90v_0p90v_85c,tt_ctypical_1p00v_1p00v_125c,tt_ctypical_1p00v_1p00v_85c,tt_ctypical_1p05v_1p05v_85c
+cust_comment = This\ is\ a\ memory\ instance
+diodes = on
+drive = 6
+ema = on
+frequency = 400
+instname = rom_via
+left_bus_delim = [
+libertyviewstyle = nldm
+libname = rom_via
+mode = ones
+mux = 8
+mvt = LL
+name_case = upper
+pipeline = off
+power_type = otc
+pwr_gnd_rename = vdde:VDDE,vsse:VSSE
+right_bus_delim = ]
+ser = none
+site_def = off
+top_layer = m5-m10
+words = 256

ASIC/TSMC28nm/sram_16k.spec

+# user spec file, compiler sram_sp_hde_hvt_mvt, version r0p0
+
+EOL_guardband = 0
+activity_factor = 10
+atf = off
+back_biasing = off
+bits = 32
+bmux = off
+bus_notation = on
+check_instname = on
+compiler_type = sp
+corners = ffg_cbestt_0p99v_0p99v_125c,ffg_cbestt_0p99v_0p99v_m40c,ssg_cworstt_0p81v_0p81v_125c,ssg_cworstt_0p81v_0p81v_m40c,tt_ctypical_0p90v_0p90v_85c
+cust_comment = 
+diodes = on
+drive = 6
+ema = on
+fci_type = not_fci
+flexible_banking = 4
+frequency = 400
+instname = sram_16k
+left_bus_delim = [
+libertyviewstyle = nldm
+libname = SRAM_16K
+lren_bankmask = off
+mux = 8
+mvt = LL
+name_case = upper
+pipeline = off
+power_gating = off
+power_type = otc
+prefix = 
+pwr_gnd_rename = vddpe:VDD,vddce:VDD,vsse:VSS
+rcols = 2
+redundancy = off
+retention = on
+right_bus_delim = ]
+rows_p_bl = 256
+rrows = 0
+scan = off
+ser = none
+site_def = off
+wa = on
+words = 4096
+wp_size = 1
+write_mask = on
+write_thru = off