Rm nanosoc pads from ASIC flist mv to genus flows

.gitignore

@@ -15,10 +15,16 @@ ASIC/*/Cadence/scripts/*.rpt
 ASIC/*/Cadence/scripts/*.tstamp
 
 ASIC/*/Cadence/scripts/.cadence
+ASIC/*/Cadence/scripts/.*
+ASIC/*/Cadence/scripts/*.spec
+ASIC/*/Cadence/scripts/*.sdf
+ASIC/*/Cadence/scripts/*.gif
+ASIC/*/Cadence/scripts/*.lef
+ASIC/*/Cadence/scripts/result
 ASIC/*/Cadence/scripts/nanosoc_chip_pads
 ASIC/*/Cadence/scripts/timingReports
 ASIC/*/Cadence/scripts/*.db*
-ASIC/*/Cadence/scripts/*.rpt
+ASIC/*/Cadence/scripts/*.rpt*
 ASIC/*/Cadence/scripts/*.checkFPlan
 ASIC/*/Cadence/scripts/*.ptiavg
 ASIC/*/Cadence/scripts/*.ptifiles

ASIC/28pin/Cadence/scripts/genus.tcl

@@ -10,6 +10,7 @@ set_db [get_db library_domains domain1] .library "$BASE_LIB $RF_16K_LIB $RF_08K_
 read_power_intent -cpf -module nanosoc_chip_pads ../cpf/nanosoc.cpf
 
 source $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/genus_flist.tcl
+read_hdl -define POWER_PINS $env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_28pin.v
 elaborate nanosoc_chip_pads
 
 apply_power_intent

ASIC/60pin/Cadence/scripts/genus.tcl

@@ -9,6 +9,7 @@ set_db [get_db library_domains domain1] .library "$BASE_LIB $RF_LIB $ROM_LIB $IO
 read_power_intent -cpf -module nanosoc_chip_pads nanosoc.cpf
 
 source $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/genus_flist.tcl
+read_hdl -define POWER_PINS $env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_60pin.v
 elaborate nanosoc_chip_pads
 
 apply_power_intent

flist/nanosoc_ASIC.flist

@@ -19,7 +19,7 @@
 
 // NanoSoC Chip Pads Level
 // $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_28pin.v
-$(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_40pin.v
+// $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_44pin.v
 // $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_60pin.v
 
 // Include NanoSoC IP