diff --git a/.gitignore b/.gitignore
index 65b4d8bc0af7b79ef079b88f58cfb0b68098d4ed..b7ac34e947fe04a2aa58380e336bb19537b5da34 100644
--- a/.gitignore
+++ b/.gitignore
@@ -15,10 +15,16 @@ ASIC/*/Cadence/scripts/*.rpt
 ASIC/*/Cadence/scripts/*.tstamp
 
 ASIC/*/Cadence/scripts/.cadence
+ASIC/*/Cadence/scripts/.*
+ASIC/*/Cadence/scripts/*.spec
+ASIC/*/Cadence/scripts/*.sdf
+ASIC/*/Cadence/scripts/*.gif
+ASIC/*/Cadence/scripts/*.lef
+ASIC/*/Cadence/scripts/result
 ASIC/*/Cadence/scripts/nanosoc_chip_pads
 ASIC/*/Cadence/scripts/timingReports
 ASIC/*/Cadence/scripts/*.db*
-ASIC/*/Cadence/scripts/*.rpt
+ASIC/*/Cadence/scripts/*.rpt*
 ASIC/*/Cadence/scripts/*.checkFPlan
 ASIC/*/Cadence/scripts/*.ptiavg
 ASIC/*/Cadence/scripts/*.ptifiles
diff --git a/ASIC/28pin/Cadence/scripts/genus.tcl b/ASIC/28pin/Cadence/scripts/genus.tcl
index cdd5fa7905b4734f93a66dc504a9c24235899e29..65781dcf02b52cf70dcb984f87928490d0941464 100644
--- a/ASIC/28pin/Cadence/scripts/genus.tcl
+++ b/ASIC/28pin/Cadence/scripts/genus.tcl
@@ -10,6 +10,7 @@ set_db [get_db library_domains domain1] .library "$BASE_LIB $RF_16K_LIB $RF_08K_
 read_power_intent -cpf -module nanosoc_chip_pads ../cpf/nanosoc.cpf
 
 source $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/genus_flist.tcl
+read_hdl -define POWER_PINS $env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_28pin.v
 elaborate nanosoc_chip_pads
 
 apply_power_intent
diff --git a/ASIC/60pin/Cadence/scripts/genus.tcl b/ASIC/60pin/Cadence/scripts/genus.tcl
index f14ee75bd119c3493172ba074fa775ed2e1a4f21..e6ff8ac946e8f81281944b2c5a2767449779e63c 100644
--- a/ASIC/60pin/Cadence/scripts/genus.tcl
+++ b/ASIC/60pin/Cadence/scripts/genus.tcl
@@ -9,6 +9,7 @@ set_db [get_db library_domains domain1] .library "$BASE_LIB $RF_LIB $ROM_LIB $IO
 read_power_intent -cpf -module nanosoc_chip_pads nanosoc.cpf
 
 source $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/genus_flist.tcl
+read_hdl -define POWER_PINS $env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_60pin.v
 elaborate nanosoc_chip_pads
 
 apply_power_intent
diff --git a/flist/nanosoc_ASIC.flist b/flist/nanosoc_ASIC.flist
index 9699ae142b54720d1a2c0bf3e1f63aac175d06a4..1fe143c29dd81106062ff6b6381193db8f6b98fe 100644
--- a/flist/nanosoc_ASIC.flist
+++ b/flist/nanosoc_ASIC.flist
@@ -19,7 +19,7 @@
 
 // NanoSoC Chip Pads Level
 // $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_28pin.v
-$(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_40pin.v
+// $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_44pin.v
 // $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_60pin.v
 
 // Include NanoSoC IP