Renamed system directory to nanosoc

.gitlab-ci.yml

@@ -26,14 +26,14 @@ compile-bootrom:
   stage: compile
   script:
     - source ./set_env.sh
-    - mkdir -p $SOCLABS_NANOSOC_TECH_DIR/system/src/bootrom
-    - make -C $SOCLABS_NANOSOC_TECH_DIR/system bootrom SIM_TOP_DIR=$SOCLABS_NANOSOC_TECH_DIR/sim BOOTROM_BUILD_DIR=$SOCLABS_NANOSOC_TECH_DIR/system/src/bootrom TOOL_CHAIN=ds5
+    - mkdir -p $SOCLABS_NANOSOC_TECH_DIR/nanosoc/src/bootrom
+    - make -C $SOCLABS_NANOSOC_TECH_DIR/system bootrom SIM_TOP_DIR=$SOCLABS_NANOSOC_TECH_DIR/sim BOOTROM_BUILD_DIR=$SOCLABS_NANOSOC_TECH_DIR/nanosoc/src/bootrom TOOL_CHAIN=ds5
   artifacts:
     paths:
       - ./sim/bootloader/bootloader.hex
-      - ./system/testcodes/bootloader/bootloader.hex
-      - ./system/src/bootrom/verilog/bootrom.v
-      - ./system/src/bootrom/bintxt/bootrom.bintxt
+      - ./nanosoc/testcodes/bootloader/bootloader.hex
+      - ./nanosoc/src/bootrom/verilog/bootrom.v
+      - ./nanosoc/src/bootrom/bintxt/bootrom.bintxt
   tags:
     - ds5
 
@@ -50,7 +50,7 @@ build-job-Z2:       # This job runs in the build stage, which runs first.
   stage: build
   script:
     # move to fpga_imp directory and run the fpga build script for pynq z2
-    - cd ./system/fpga_imp/
+    - cd ./nanosoc/fpga_imp/
     - source ../../set_env.sh
     - if source ./build_fpga_pynq_z2.scr; then echo "Vivado Finished"; fi
     - FILE=./pynq_export/pz2/pynq/overlays/soclabs/design_1.bit 
@@ -63,8 +63,8 @@ build-job-Z2:       # This job runs in the build stage, which runs first.
   artifacts:
     paths:
       # Keep the generated bit and hwh file from fpga build script
-      - ./system/fpga_imp/pynq_export/pz2/pynq/overlays/soclabs/design_1.bit
-      - ./system/fpga_imp/pynq_export/pz2/pynq/overlays/soclabs/design_1.hwh
+      - ./nanosoc/fpga_imp/pynq_export/pz2/pynq/overlays/soclabs/design_1.bit
+      - ./nanosoc/fpga_imp/pynq_export/pz2/pynq/overlays/soclabs/design_1.hwh
   tags:
     - Vivado2021.1
 
@@ -72,7 +72,7 @@ build-job-ZCU104:       # This job runs in the build stage, which runs first.
   stage: build
   script:
    # move to fpga_imp directory and run the fpga build script for pynq z2 
-    - cd ./system/fpga_imp/
+    - cd ./nanosoc/fpga_imp/
     - source ../../set_env.sh
     - if source ./build_fpga_pynq_zcu104.scr; then echo "Vivado Finished"; fi
     - FILE=./pynq_export/pz104/pynq/overlays/soclabs/design_1.bit 
@@ -85,8 +85,8 @@ build-job-ZCU104:       # This job runs in the build stage, which runs first.
   artifacts:
     paths:
     # Keep the generated bit and hwh file from fpga build script
-      - ./system/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.bit
-      - ./system/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.hwh
+      - ./nanosoc/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.bit
+      - ./nanosoc/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.hwh
   tags:
     - Vivado2021.1
 
@@ -97,7 +97,7 @@ build-job-ZCU104:       # This job runs in the build stage, which runs first.
 #    - echo "Deploying application to Z2"
 #    # use smbclient to transfer accross the bit, hwh and python script files to the z2 xilinx board
 #    # could probably set this up as scp with RSA keys in future
-#    - smbclient //192.168.2.99/xilinx -m SMB3 -U xilinx%xilinx -c 'cd ./pynq/overlays/soclabs/ ; put ./system/fpga_imp/pynq_export/pz2/pynq/overlays/#soclabs/design_1.bit ./design_1.bit' -E 2>errorlog
+#    - smbclient //192.168.2.99/xilinx -m SMB3 -U xilinx%xilinx -c 'cd ./pynq/overlays/soclabs/ ; put ./nanosoc/fpga_imp/pynq_export/pz2/pynq/overlays/#soclabs/design_1.bit ./design_1.bit' -E 2>errorlog
 #    - if (grep -r "Connection to 192.168.2.99 failed" ./errorlog)
 #    - then
 #    -   echo "Connection to Z2 Board Failed"
@@ -106,7 +106,7 @@ build-job-ZCU104:       # This job runs in the build stage, which runs first.
 #    -   echo "Connection to Z2 Board successful"
 #    - fi
 #    - rm errorlog
-#    - smbclient //192.168.2.99/xilinx -m SMB3 -U xilinx%xilinx -c 'cd ./pynq/overlays/soclabs/ ; put ./system/fpga_imp/pynq_export/pz2/pynq/overlays/#soclabs/design_1.hwh ./design_1.hwh' -E 2>errorlog
+#    - smbclient //192.168.2.99/xilinx -m SMB3 -U xilinx%xilinx -c 'cd ./pynq/overlays/soclabs/ ; put ./nanosoc/fpga_imp/pynq_export/pz2/pynq/overlays/#soclabs/design_1.hwh ./design_1.hwh' -E 2>errorlog
 #    - if (grep -r "Connection to 192.168.2.99 failed" ./errorlog)
 #    - then
 #    -   echo "Connection to Z2 Board Failed"
@@ -115,7 +115,7 @@ build-job-ZCU104:       # This job runs in the build stage, which runs first.
 #    -   echo "Connection to Z2 Board successful"
 #    - fi
 #    - rm errorlog
-#    - cd ./system/fpga_imp/CI_verification
+#    - cd ./nanosoc/fpga_imp/CI_verification
 #    - smbclient //192.168.2.99/xilinx -m SMB3 -U xilinx%xilinx -c 'put ./load_bitfile.py ./load_bitfile.py' -E 2>errorlog
 #    - if (grep -r "Connection to 192.168.2.99 failed" ./errorlog)
 #    - then
@@ -174,11 +174,11 @@ deploy-job-ZCU104:      # This job runs in the deploy stage.
     - screen -r zynq -X stuff "./ZCU104_connect.sh\n"
     - sleep 10
     # use scp to copy over bit files and python script
-    - screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/nanosoc_tech/system/fpga_imp/CI_verification/load_bitfile.py ./ \n"
+    - screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/nanosoc_tech/nanosoc/fpga_imp/CI_verification/load_bitfile.py ./ \n"
     - sleep 2
-    - screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/nanosoc_tech/system/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.bit ./pynq/overlays/soclabs/design_1.bit \n"
+    - screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/nanosoc_tech/nanosoc/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.bit ./pynq/overlays/soclabs/design_1.bit \n"
     - sleep 2
-    - screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/nanosoc_tech/system/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.hwh ./pynq/overlays/soclabs/design_1.hwh \n"
+    - screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/nanosoc_tech/nanosoc/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.hwh ./pynq/overlays/soclabs/design_1.hwh \n"
     - sleep 2
     # Need root access to load the overlay onto the FPGA
     - screen -r zynq -X stuff "sudo su\n"
@@ -196,7 +196,7 @@ deploy-job-ZCU104:      # This job runs in the deploy stage.
     - screen -r zynq -X stuff "deactivate \n"
     - screen -r zynq -X stuff "exit \n"
     # test the screenlog for "Overlay Loaded"
-    - cp ./system/fpga_imp/CI_verification/test_bitfile_ZCU104.sh ./
+    - cp ./nanosoc/fpga_imp/CI_verification/test_bitfile_ZCU104.sh ./
     - chmod +x test_bitfile_ZCU104.sh
     - ./test_bitfile_ZCU104.sh
 

.gitmodules

-[submodule "system/socdebug_tech"]
-	path = system/socdebug_tech
+[submodule "nanosoc/socdebug_tech"]
+	path = nanosoc/socdebug_tech
 	url = https://git.soton.ac.uk/soclabs/socdebug_tech.git
-[submodule "system/sldma230_tech"]
-	path = system/sldma230_tech
+[submodule "nanosoc/sldma230_tech"]
+	path = nanosoc/sldma230_tech
 	url = https://git.soton.ac.uk/soclabs/sldma230_tech.git
-[submodule "system/slcorem0_tech"]
-	path = system/slcorem0_tech
+[submodule "nanosoc/slcorem0_tech"]
+	path = nanosoc/slcorem0_tech
 	url = https://git.soton.ac.uk/soclabs/slcorem0_tech.git

flist/nanosoc.flist

@@ -33,4 +33,4 @@
 -f $(SOCLABS_SLDMA230_TECH_DIR)/flist/sldma230_ip.flist
 
 // DMA Subystem
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_subsystems/dma/dma230/verilog/nanosoc_ss_dma.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_subsystems/dma/dma230/verilog/nanosoc_ss_dma.v

flist/nanosoc_busmatrix_ip.flist

@@ -16,27 +16,27 @@
 +libext+.v+.vlib
 
 // =============    NanoSoC BusMatrix IP search path    =============
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_BOOTROM_0.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_DMEM_0.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_H.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_L.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXP.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_IMEM_0.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSIO.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSTABLE.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_default_slave.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_inititator_input.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_CPU_0.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DEBUG.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_0.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_1.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_BOOTROM_0.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_DMEM_0.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_H.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_L.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXP.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_IMEM_0.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSIO.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSTABLE.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_BOOTROM_0.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_DMEM_0.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_H.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_L.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXP.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_IMEM_0.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSIO.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSTABLE.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_default_slave.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_inititator_input.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_CPU_0.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DEBUG.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_0.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_1.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_BOOTROM_0.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_DMEM_0.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_H.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_L.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXP.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_IMEM_0.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSIO.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSTABLE.v
\ No newline at end of file

flist/nanosoc_ip.flist

@@ -18,52 +18,52 @@
 // =============    NanoSoC IP search path    =============
 
 // NanoSoC Chip Pads Level
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v
 
 // NanoSoC Chip Level
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_chip/chip/verilog/nanosoc_chip.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_chip/chip/verilog/nanosoc_chip.v
 
 // NanoSoC System Level
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_system/verilog/nanosoc_system.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_system/verilog/nanosoc_system.v
 
 // NanoSoC Subsystems
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_subsystems/cpu/verilog/nanosoc_ss_cpu.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_subsystems/debug/verilog/nanosoc_ss_debug.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_subsystems/expansion/verilog/nanosoc_ss_expansion.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_subsystems/interconnect/verilog/nanosoc_ss_interconnect.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_subsystems/cpu/verilog/nanosoc_ss_cpu.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_subsystems/debug/verilog/nanosoc_ss_debug.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_subsystems/expansion/verilog/nanosoc_ss_expansion.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_subsystems/interconnect/verilog/nanosoc_ss_interconnect.v
 
 // Bus Matrix
 -f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_busmatrix_ip.flist
 
 // NanoSoC Regions - Bootrom
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/bootrom_0/verilog/nanosoc_bootrom_cpu_0.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/bootrom_0/verilog/nanosoc_region_bootrom_0.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/bootrom_0/verilog/nanosoc_bootrom_cpu_0.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/bootrom_0/verilog/nanosoc_region_bootrom_0.v
 
 // NanoSoC Regions - CPU Memories
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/dmem_0/verilog/nanosoc_region_dmem_0.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/dmem_0/verilog/nanosoc_region_dmem_0.v
 
 // TODO: Use ROM Memory for IMEM - switch back to SRAM
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/imem_0/rom/verilog/nanosoc_region_imem_0.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/imem_0/rom/verilog/nanosoc_region_imem_0.v
 
 // NanoSoC Regions - Expansion Regions
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/exp/verilog/nanosoc_region_exp.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/expram_h/verilog/nanosoc_region_expram_h.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/expram_l/verilog/nanosoc_region_expram_l.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/exp/verilog/nanosoc_region_exp.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/expram_h/verilog/nanosoc_region_expram_h.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/expram_l/verilog/nanosoc_region_expram_l.v
 
 // NanoSoC Regions - Sysio Region
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/sysio/verilog/nanosoc_sysctrl.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/sysio/verilog/nanosoc_sysio_apb_ss.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysctrl.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_apb_ss.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v
 
 // NanoSoC Regions - SysTable Region
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/systable/verilog/nanosoc_coresight_systable.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/systable/verilog/nanosoc_region_systable.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/systable/verilog/nanosoc_coresight_systable.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/systable/verilog/nanosoc_region_systable.v
 
 // NanoSoC Control
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_control/verilog/nanosoc_clkctrl.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_control/verilog/nanosoc_pin_mux.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_control/verilog/nanosoc_clkctrl.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_control/verilog/nanosoc_pin_mux.v
 
 
 

flist/nanosoc_qs.flist

@@ -30,4 +30,4 @@
 -f $(SOCLABS_SOCDEBUG_TECH_DIR)/flist/socdebug.flist
 
 // DMA Subystem
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_subsystems/dma/no_dmac/verilog/nanosoc_ss_dma.v
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_subsystems/dma/no_dmac/verilog/nanosoc_ss_dma.v
\ No newline at end of file

hal/nanosoc_ip.bb

@@ -16,11 +16,11 @@ bb_list
 {
     // Exclude Bus Matrix as Generated from Arm IP
     designunit = nanosoc_busmatrix_lite;
-    file = $SOCLABS_NANOSOC_TECH_DIR/system/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v;
+    file = $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v;
     
     // Temporarily Exclude SoCDebug
     designunit = socdebug_ahb;
-    file = $SOCLABS_NANOSOC_TECH_DIR/system/socdebug_tech/controller/verilog/socdebug_ahb.v;
+    file = $SOCLABS_NANOSOC_TECH_DIR/nanosoc/socdebug_tech/controller/verilog/socdebug_ahb.v;
     
     // Temporarily Exclude Accelerator Subsystem (just linting NanoSoC)
     designunit = accelerator_subsystem;

system/nanosoc_busmatrix/makefile → nanosoc/nanosoc_busmatrix/makefile

@@ -15,7 +15,7 @@
 MATRIX_NAME ?= nanosoc
 
 # Top-level directory of Bus Matrix
-BUILD_DIR  ?= $(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_busmatrix
+BUILD_DIR  ?= $(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_busmatrix
 
 # Directory location of BuildBusMatrix Script
 SOURCE_DIR  = $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_busmatrix