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Commit a6a5c6e6 authored by dwf1m12's avatar dwf1m12
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remove hard fault limits to memory bank regions for baseline

parent 4674470e
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......@@ -43,14 +43,14 @@
#include "CMSDK_CM4.h"
#endif
#define SRAM_BASE_ADDR 0x20000000
#define SRAM_SIZE 0x10000
#define SRAM_BASE_ADDR 0x30000000
#define SRAM_SIZE 0x4000
#define ROM_BASE_ADDR 0x00000000
#define ROM_SIZE 0x10000
#define ROM_BASE_ADDR 0x20000000
#define ROM_SIZE 0x4000
#define BOOT_BASE_ADDR 0x01000000
#define BOOT_SIZE 0x4000
#define BOOT_BASE_ADDR 0x10000000
#define BOOT_SIZE 0x400
#define BOOT_ALIAS_SIZE 0x10000
#define APB_IO_BASE_ADDR 0x40000000
......@@ -143,14 +143,14 @@ int rom_test(void)
if (hardfault_occurred!=0) err_code |= 1<<1;
/* Test addresses beyond ROM boundary */
hardfault_occurred = 0;
hardfault_expected = 1;
temp_data = address_test_read(((unsigned)(ROM_BASE_ADDR-4)));
if (hardfault_occurred==0) err_code |= 1<<2;
hardfault_occurred = 0;
hardfault_expected = 1;
temp_data = address_test_read(ROM_BASE_ADDR+ROM_SIZE);
if (hardfault_occurred==0) err_code |= 1<<3;
// hardfault_occurred = 0;
// hardfault_expected = 1;
// temp_data = address_test_read(((unsigned)(ROM_BASE_ADDR-4)));
// if (hardfault_occurred==0) err_code |= 1<<2;
// hardfault_occurred = 0;
// hardfault_expected = 1;
// temp_data = address_test_read(ROM_BASE_ADDR+ROM_SIZE);
// if (hardfault_occurred==0) err_code |= 1<<3;
if (err_code> 0) {
puts (" Failed\n");
......@@ -187,21 +187,21 @@ int boot_rom_test(void)
if (hardfault_occurred!=0) err_code |= 1<<0;
/* Test addresses beyond Boot loader ROM boundary */
hardfault_occurred = 0;
hardfault_expected = 1;
temp_data = address_test_read(BOOT_BASE_ADDR-4);
if (hardfault_occurred==0) err_code |= 1<<1;
hardfault_occurred = 0;
hardfault_expected = 0; /* 64KB range is allocated for boot ROM,
but only 4K is used. Access over 4KB range wraps round */
temp_data = address_test_read(BOOT_BASE_ADDR+BOOT_SIZE);
if (hardfault_occurred!=0) err_code |= 1<<2;
hardfault_occurred = 0;
hardfault_expected = 1; /* Check beyond alias range */
temp_data = address_test_read(BOOT_BASE_ADDR+BOOT_ALIAS_SIZE);
if (hardfault_occurred==0) err_code |= 1<<3;
// hardfault_occurred = 0;
// hardfault_expected = 1;
// temp_data = address_test_read(BOOT_BASE_ADDR-4);
// if (hardfault_occurred==0) err_code |= 1<<1;
// hardfault_occurred = 0;
// hardfault_expected = 0; /* 64KB range is allocated for boot ROM,
// but only 4K is used. Access over 4KB range wraps round */
// temp_data = address_test_read(BOOT_BASE_ADDR+BOOT_SIZE);
// if (hardfault_occurred!=0) err_code |= 1<<2;
// hardfault_occurred = 0;
// hardfault_expected = 1; /* Check beyond alias range */
// temp_data = address_test_read(BOOT_BASE_ADDR+BOOT_ALIAS_SIZE);
// if (hardfault_occurred==0) err_code |= 1<<3;
if (err_code> 0) {
puts (" Failed\n");
......@@ -230,15 +230,15 @@ int sram_test(void)
/* Test addresses beyond SRAM boundary */
hardfault_occurred = 0;
hardfault_expected = 1;
temp_data = address_test_read(SRAM_BASE_ADDR-4);
if (hardfault_occurred==0) err_code |= 1<<2;
// hardfault_occurred = 0;
// hardfault_expected = 1;
// temp_data = address_test_read(SRAM_BASE_ADDR-4);
// if (hardfault_occurred==0) err_code |= 1<<2;
hardfault_occurred = 0;
hardfault_expected = 1;
temp_data = address_test_read(SRAM_BASE_ADDR+SRAM_SIZE);
if (hardfault_occurred==0) err_code |= 1<<3;
// hardfault_occurred = 0;
// hardfault_expected = 1;
// temp_data = address_test_read(SRAM_BASE_ADDR+SRAM_SIZE);
// if (hardfault_occurred==0) err_code |= 1<<3;
hardfault_occurred = 0;
hardfault_expected = 0;
......@@ -306,10 +306,10 @@ int apb_io_test(void)
if (hardfault_occurred!=0) err_code |= 1<<1;
/* Test addresses beyond IO boundary */
hardfault_occurred = 0;
hardfault_expected = 1;
temp_data = address_test_read(APB_IO_BASE_ADDR-4);
if (hardfault_occurred==0) err_code |= 1<<2;
// hardfault_occurred = 0;
// hardfault_expected = 1;
// temp_data = address_test_read(APB_IO_BASE_ADDR-4);
// if (hardfault_occurred==0) err_code |= 1<<2;
/* Address above APB IO space is AHB GPIO, not test here */
......
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