debug and update APB tests and RTL to validate in nanosoc

Cortex-M0/nanosoc/software/common/validation/apb_mux_tests.c

@@ -129,7 +129,7 @@ int main (void)
   puts ("13: APB expansion port 13");
     if ( ID_Check(&blank_id[0],         0x4000D000          ) == 1 ) err_code |= 1<<13;
   puts ("14: APB expansion port 14");
-    if ( ID_Check(&blank_id[0],         0x4000E000          ) == 1 ) err_code |= 1<<14;
+    if ( ID_Check(&apb_uart_id[0],      CMSDK_USRT2_BASE    ) == 1 ) err_code |= 1<<14;
   puts ("15: APB expansion port 15 (optional DMA controller)");
     if ( ID_Check(&pl230_udma_id[0],    CMSDK_PL230_BASE    ) == 1 ) err_code |= 1<<15;
 

Cortex-M0/nanosoc/systems/mcu/testcodes/apb_mux_tests/makefile

@@ -108,7 +108,7 @@ ARM_CC_OPTIONS   = -c -O3 -g -Otime -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
 		   -I $(SOFTWARE_DIR)/common/retarget $(USER_DEFINE)
 ARM_ASM_OPTIONS  = -g
 ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
-		   --rw_base 0x20000000 --ro_base 0x00000000 --map
+		   --rw_base 0x30000000 --ro_base 0x00000000 --map
 
 ifeq ($(COMPILE_BIGEND),1)
  # Big Endian

Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip.v

@@ -1490,6 +1490,10 @@ localparam AWRAM9 = 14; // 16KB
  
  assign exp12_pready = 1'b1;
  assign exp13_pready = 1'b1;
+ assign exp12_pslverr = 1'b0;
+ assign exp13_pslverr = 1'b0;
+ assign exp12_prdata = 32'h0;
+ assign exp13_prdata = 32'h0;
  
 
   // Serial wire debug is used.  nTRST, TDI and TDO are not needed