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Commit a26a980b authored by dam1n19's avatar dam1n19
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Updated apb_mux_test

parent 1d6d4681
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1 merge request!1changed imem to rom to allow initial program loading, updated bootloader code...
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nanosoc/nanosoc_subsystems/dma/dma230/verilog/nanosoc_ss_dma.v
+ 14
− 0
View file @ a26a980b
...@@ -43,6 +43,8 @@ module nanosoc_ss_dma #( ...@@ -43,6 +43,8 @@ module nanosoc_ss_dma #(
input wire [DMAC_0_CFG_ADDR_W-1:0] DMAC_0_PADDR, // APB address input wire [DMAC_0_CFG_ADDR_W-1:0] DMAC_0_PADDR, // APB address
input wire [SYS_DATA_W-1:0] DMAC_0_PWDATA, // APB write data input wire [SYS_DATA_W-1:0] DMAC_0_PWDATA, // APB write data
output wire [SYS_DATA_W-1:0] DMAC_0_PRDATA, // APB read data output wire [SYS_DATA_W-1:0] DMAC_0_PRDATA, // APB read data
output wire DMAC_0_PREADY, // APB Ready
output wire DMAC_0_PSLVERR, // APB Slave Error
// DMAC 0 DMA Request and Status Port // DMAC 0 DMA Request and Status Port
input wire [DMAC_0_CHANNEL_NUM-1:0] DMAC_0_DMA_REQ, // DMA transfer request input wire [DMAC_0_CHANNEL_NUM-1:0] DMAC_0_DMA_REQ, // DMA transfer request
...@@ -69,6 +71,8 @@ module nanosoc_ss_dma #( ...@@ -69,6 +71,8 @@ module nanosoc_ss_dma #(
input wire [DMAC_1_CFG_ADDR_W-1:0] DMAC_1_PADDR, // APB address input wire [DMAC_1_CFG_ADDR_W-1:0] DMAC_1_PADDR, // APB address
input wire [SYS_DATA_W-1:0] DMAC_1_PWDATA, // APB write data input wire [SYS_DATA_W-1:0] DMAC_1_PWDATA, // APB write data
output wire [SYS_DATA_W-1:0] DMAC_1_PRDATA, // APB read data output wire [SYS_DATA_W-1:0] DMAC_1_PRDATA, // APB read data
output wire DMAC_1_PREADY, // APB Ready
output wire DMAC_1_PSLVERR, // APB Slave Error
// DMAC 1 DMA Request and Status Port // DMAC 1 DMA Request and Status Port
input wire [DMAC_1_CHANNEL_NUM-1:0] DMAC_1_DMA_REQ, // DMA transfer request input wire [DMAC_1_CHANNEL_NUM-1:0] DMAC_1_DMA_REQ, // DMA transfer request
...@@ -117,6 +121,12 @@ module nanosoc_ss_dma #( ...@@ -117,6 +121,12 @@ module nanosoc_ss_dma #(
.DMA_ERR(DMAC_0_DMA_ERR) .DMA_ERR(DMAC_0_DMA_ERR)
); );
// APB Assignments
//--------------------------
assign DMAC_0_PREADY = 1'b1;
assign DMAC_0_PSLVERR = 1'b0;
// ------------------------------- // -------------------------------
// DMA Controller 1 Instantiation - Not implemented // DMA Controller 1 Instantiation - Not implemented
// ------------------------------- // -------------------------------
...@@ -132,9 +142,13 @@ module nanosoc_ss_dma #( ...@@ -132,9 +142,13 @@ module nanosoc_ss_dma #(
// APB Tie-off signals // APB Tie-off signals
assign DMAC_1_PRDATA = 32'd0; assign DMAC_1_PRDATA = 32'd0;
assign DMAC_1_PREADY = 1'b1;
assign DMAC_1_PSLVERR = 1'b1;
// DMA Status Tie-off signals // DMA Status Tie-off signals
assign DMAC_1_DMA_DONE = {DMAC_1_CHANNEL_NUM{1'b0}}; assign DMAC_1_DMA_DONE = {DMAC_1_CHANNEL_NUM{1'b0}};
assign DMAC_1_DMA_ERR = 1'b0; assign DMAC_1_DMA_ERR = 1'b0;
endmodule endmodule
\ No newline at end of file
nanosoc/nanosoc_system/verilog/nanosoc_system.v
+ 4
− 8
View file @ a26a980b
...@@ -442,14 +442,6 @@ module nanosoc_system #( ...@@ -442,14 +442,6 @@ module nanosoc_system #(
assign DMAC_1_DMA_REQ = {DMAC_1_CHANNEL_NUM{1'b0}}; assign DMAC_1_DMA_REQ = {DMAC_1_CHANNEL_NUM{1'b0}};
// APB Assignments
//--------------------------
assign DMAC_0_PREADY = 1'b1;
assign DMAC_0_PSLVERR = 1'b0;
assign DMAC_1_PREADY = 1'b1;
assign DMAC_1_PSLVERR = 1'b0;
// Instantiate Subsystem // Instantiate Subsystem
//-------------------------- //--------------------------
...@@ -489,6 +481,8 @@ module nanosoc_system #( ...@@ -489,6 +481,8 @@ module nanosoc_system #(
.DMAC_0_PADDR(SYSIO_PADDR), .DMAC_0_PADDR(SYSIO_PADDR),
.DMAC_0_PWDATA(SYSIO_PWDATA), .DMAC_0_PWDATA(SYSIO_PWDATA),
.DMAC_0_PRDATA(DMAC_0_PRDATA), .DMAC_0_PRDATA(DMAC_0_PRDATA),
.DMAC_0_PREADY(DMAC_0_PREADY),
.DMAC_0_PSLVERR(DMAC_0_PSLVERR),
// DMAC 0 DMA Request and Status Port // DMAC 0 DMA Request and Status Port
.DMAC_0_DMA_REQ(DMAC_0_DMA_REQ), .DMAC_0_DMA_REQ(DMAC_0_DMA_REQ),
...@@ -515,6 +509,8 @@ module nanosoc_system #( ...@@ -515,6 +509,8 @@ module nanosoc_system #(
.DMAC_1_PADDR(SYSIO_PADDR), .DMAC_1_PADDR(SYSIO_PADDR),
.DMAC_1_PWDATA(SYSIO_PWDATA), .DMAC_1_PWDATA(SYSIO_PWDATA),
.DMAC_1_PRDATA(DMAC_1_PRDATA), .DMAC_1_PRDATA(DMAC_1_PRDATA),
.DMAC_1_PREADY(DMAC_1_PREADY),
.DMAC_1_PSLVERR(DMAC_1_PSLVERR),
// DMAC 1 DMA Request and Status Port // DMAC 1 DMA Request and Status Port
.DMAC_1_DMA_REQ(DMAC_1_DMA_REQ), .DMAC_1_DMA_REQ(DMAC_1_DMA_REQ),
......
software/common/validation/apb_mux_tests.c
+ 18
− 18
View file @ a26a980b
...@@ -106,31 +106,31 @@ int main (void) ...@@ -106,31 +106,31 @@ int main (void)
if ( ID_Check(&apb_timer_id[0], CMSDK_TIMER1_BASE ) == 1 ) err_code |= 1<<1; if ( ID_Check(&apb_timer_id[0], CMSDK_TIMER1_BASE ) == 1 ) err_code |= 1<<1;
puts ("2: dual timer"); puts ("2: dual timer");
if ( ID_Check(&apb_dualtimer_id[0], CMSDK_DUALTIMER_BASE) == 1 ) err_code |= 1<<2; if ( ID_Check(&apb_dualtimer_id[0], CMSDK_DUALTIMER_BASE) == 1 ) err_code |= 1<<2;
puts ("3: blank"); puts ("3: blank - default slave (generates slave error)");
if ( ID_Check(&blank_id[0], 0x40003000 ) == 1 ) err_code |= 1<<3; // if ( ID_Check(&blank_id[0], 0x40003000 ) == 1 ) err_code |= 1<<3;
puts ("4: UART 0"); puts ("4: UART 0 - Not Implemented");
if ( ID_Check(&apb_uart_id[0], CMSDK_UART0_BASE ) == 1 ) err_code |= 1<<4; // if ( ID_Check(&apb_uart_id[0], CMSDK_UART0_BASE ) == 1 ) err_code |= 1<<4;
puts ("5: UART 1"); puts ("5: UART 1 - Not Implemented");
if ( ID_Check(&apb_uart_id[0], CMSDK_UART1_BASE ) == 1 ) err_code |= 1<<5; // if ( ID_Check(&apb_uart_id[0], CMSDK_UART1_BASE ) == 1 ) err_code |= 1<<5;
puts ("6: UART 2"); puts ("6: UART 2");
if ( ID_Check(&apb_uart_id[0], CMSDK_UART2_BASE ) == 1 ) err_code |= 1<<6; if ( ID_Check(&apb_uart_id[0], CMSDK_UART2_BASE ) == 1 ) err_code |= 1<<6;
puts ("7: blank"); puts ("7: blank - default slave (generates slave error)");
if ( ID_Check(&blank_id[0], 0x40007000 ) == 1 ) err_code |= 1<<7; // if ( ID_Check(&blank_id[0], 0x40007000 ) == 1 ) err_code |= 1<<7;
puts ("8: Watchdog"); puts ("8: Watchdog");
if ( ID_Check(&apb_watchdog_id[0], CMSDK_WATCHDOG_BASE ) == 1 ) err_code |= 1<<8; if ( ID_Check(&apb_watchdog_id[0], CMSDK_WATCHDOG_BASE ) == 1 ) err_code |= 1<<8;
puts ("9: blank"); puts ("9: blank - default slave (generates slave error)");
if ( ID_Check(&blank_id[0], 0x40009000 ) == 1 ) err_code |= 1<<9; // if ( ID_Check(&blank_id[0], 0x40009000 ) == 1 ) err_code |= 1<<9;
puts ("10: blank"); puts ("10: blank - default slave (generates slave error)");
if ( ID_Check(&blank_id[0], 0x4000A000 ) == 1 ) err_code |= 1<<10; // if ( ID_Check(&blank_id[0], 0x4000A000 ) == 1 ) err_code |= 1<<10;
puts ("11: APB test slave"); puts ("11: APB test slave");
if ( APB_test_slave_Check( 0x4000B000 ) == 1 ) err_code |= 1<<11; if ( APB_test_slave_Check( 0x4000B000 ) == 1 ) err_code |= 1<<11;
puts ("12: APB expansion port 12"); puts ("12: DMAC 1 (Not Implemented) - Slave Error");
if ( ID_Check(&blank_id[0], 0x4000C000 ) == 1 ) err_code |= 1<<12; // if ( ID_Check(&blank_id[0], 0x4000C000 ) == 1 ) err_code |= 1<<12;
puts ("13: APB expansion port 13"); puts ("13: blank - default slave (generates slave error)");
if ( ID_Check(&blank_id[0], 0x4000D000 ) == 1 ) err_code |= 1<<13; // if ( ID_Check(&blank_id[0], 0x4000D000 ) == 1 ) err_code |= 1<<13;
puts ("14: APB expansion port 14"); puts ("14: Debug USRT");
if ( ID_Check(&apb_uart_id[0], CMSDK_USRT2_BASE ) == 1 ) err_code |= 1<<14; if ( ID_Check(&apb_uart_id[0], CMSDK_USRT2_BASE ) == 1 ) err_code |= 1<<14;
puts ("15: APB expansion port 15 (optional DMA controller)"); puts ("15: DMAC 0 (PL230)");
if ( ID_Check(&pl230_udma_id[0], CMSDK_PL230_BASE ) == 1 ) err_code |= 1<<15; if ( ID_Check(&pl230_udma_id[0], CMSDK_PL230_BASE ) == 1 ) err_code |= 1<<15;
......
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