diff --git a/nanosoc/nanosoc_subsystems/dma/dma230/verilog/nanosoc_ss_dma.v b/nanosoc/nanosoc_subsystems/dma/dma230/verilog/nanosoc_ss_dma.v
index 734083ba70dff67db5864efe02f5962c14c816de..3102dc43475ab75cefa99bff7c6ae0ab77f9604a 100644
--- a/nanosoc/nanosoc_subsystems/dma/dma230/verilog/nanosoc_ss_dma.v
+++ b/nanosoc/nanosoc_subsystems/dma/dma230/verilog/nanosoc_ss_dma.v
@@ -43,6 +43,8 @@ module nanosoc_ss_dma #(
input wire [DMAC_0_CFG_ADDR_W-1:0] DMAC_0_PADDR, // APB address
input wire [SYS_DATA_W-1:0] DMAC_0_PWDATA, // APB write data
output wire [SYS_DATA_W-1:0] DMAC_0_PRDATA, // APB read data
+ output wire DMAC_0_PREADY, // APB Ready
+ output wire DMAC_0_PSLVERR, // APB Slave Error
// DMAC 0 DMA Request and Status Port
input wire [DMAC_0_CHANNEL_NUM-1:0] DMAC_0_DMA_REQ, // DMA transfer request
@@ -69,6 +71,8 @@ module nanosoc_ss_dma #(
input wire [DMAC_1_CFG_ADDR_W-1:0] DMAC_1_PADDR, // APB address
input wire [SYS_DATA_W-1:0] DMAC_1_PWDATA, // APB write data
output wire [SYS_DATA_W-1:0] DMAC_1_PRDATA, // APB read data
+ output wire DMAC_1_PREADY, // APB Ready
+ output wire DMAC_1_PSLVERR, // APB Slave Error
// DMAC 1 DMA Request and Status Port
input wire [DMAC_1_CHANNEL_NUM-1:0] DMAC_1_DMA_REQ, // DMA transfer request
@@ -117,6 +121,12 @@ module nanosoc_ss_dma #(
.DMA_ERR(DMAC_0_DMA_ERR)
);
+ // APB Assignments
+ //--------------------------
+ assign DMAC_0_PREADY = 1'b1;
+ assign DMAC_0_PSLVERR = 1'b0;
+
+
// -------------------------------
// DMA Controller 1 Instantiation - Not implemented
// -------------------------------
@@ -132,9 +142,13 @@ module nanosoc_ss_dma #(
// APB Tie-off signals
assign DMAC_1_PRDATA = 32'd0;
+ assign DMAC_1_PREADY = 1'b1;
+ assign DMAC_1_PSLVERR = 1'b1;
// DMA Status Tie-off signals
assign DMAC_1_DMA_DONE = {DMAC_1_CHANNEL_NUM{1'b0}};
assign DMAC_1_DMA_ERR = 1'b0;
+
+
endmodule
\ No newline at end of file
diff --git a/nanosoc/nanosoc_system/verilog/nanosoc_system.v b/nanosoc/nanosoc_system/verilog/nanosoc_system.v
index c3d2ab99b4e383b4e6bab300b2f287da05a59f38..92651e5678e94a6ac99c6f6717db84b716a8d996 100644
--- a/nanosoc/nanosoc_system/verilog/nanosoc_system.v
+++ b/nanosoc/nanosoc_system/verilog/nanosoc_system.v
@@ -442,14 +442,6 @@ module nanosoc_system #(
assign DMAC_1_DMA_REQ = {DMAC_1_CHANNEL_NUM{1'b0}};
- // APB Assignments
- //--------------------------
- assign DMAC_0_PREADY = 1'b1;
- assign DMAC_0_PSLVERR = 1'b0;
-
- assign DMAC_1_PREADY = 1'b1;
- assign DMAC_1_PSLVERR = 1'b0;
-
// Instantiate Subsystem
//--------------------------
@@ -489,6 +481,8 @@ module nanosoc_system #(
.DMAC_0_PADDR(SYSIO_PADDR),
.DMAC_0_PWDATA(SYSIO_PWDATA),
.DMAC_0_PRDATA(DMAC_0_PRDATA),
+ .DMAC_0_PREADY(DMAC_0_PREADY),
+ .DMAC_0_PSLVERR(DMAC_0_PSLVERR),
// DMAC 0 DMA Request and Status Port
.DMAC_0_DMA_REQ(DMAC_0_DMA_REQ),
@@ -515,6 +509,8 @@ module nanosoc_system #(
.DMAC_1_PADDR(SYSIO_PADDR),
.DMAC_1_PWDATA(SYSIO_PWDATA),
.DMAC_1_PRDATA(DMAC_1_PRDATA),
+ .DMAC_1_PREADY(DMAC_1_PREADY),
+ .DMAC_1_PSLVERR(DMAC_1_PSLVERR),
// DMAC 1 DMA Request and Status Port
.DMAC_1_DMA_REQ(DMAC_1_DMA_REQ),
diff --git a/software/common/validation/apb_mux_tests.c b/software/common/validation/apb_mux_tests.c
index c1edb227b63c1fc85c816b63a5e4e048a0625e09..a350c60056073024d36abf0c137cbc560aa08497 100644
--- a/software/common/validation/apb_mux_tests.c
+++ b/software/common/validation/apb_mux_tests.c
@@ -106,31 +106,31 @@ int main (void)
if ( ID_Check(&apb_timer_id[0], CMSDK_TIMER1_BASE ) == 1 ) err_code |= 1<<1;
puts ("2: dual timer");
if ( ID_Check(&apb_dualtimer_id[0], CMSDK_DUALTIMER_BASE) == 1 ) err_code |= 1<<2;
- puts ("3: blank");
- if ( ID_Check(&blank_id[0], 0x40003000 ) == 1 ) err_code |= 1<<3;
- puts ("4: UART 0");
- if ( ID_Check(&apb_uart_id[0], CMSDK_UART0_BASE ) == 1 ) err_code |= 1<<4;
- puts ("5: UART 1");
- if ( ID_Check(&apb_uart_id[0], CMSDK_UART1_BASE ) == 1 ) err_code |= 1<<5;
+ puts ("3: blank - default slave (generates slave error)");
+ // if ( ID_Check(&blank_id[0], 0x40003000 ) == 1 ) err_code |= 1<<3;
+ puts ("4: UART 0 - Not Implemented");
+ // if ( ID_Check(&apb_uart_id[0], CMSDK_UART0_BASE ) == 1 ) err_code |= 1<<4;
+ puts ("5: UART 1 - Not Implemented");
+ // if ( ID_Check(&apb_uart_id[0], CMSDK_UART1_BASE ) == 1 ) err_code |= 1<<5;
puts ("6: UART 2");
if ( ID_Check(&apb_uart_id[0], CMSDK_UART2_BASE ) == 1 ) err_code |= 1<<6;
- puts ("7: blank");
- if ( ID_Check(&blank_id[0], 0x40007000 ) == 1 ) err_code |= 1<<7;
+ puts ("7: blank - default slave (generates slave error)");
+ // if ( ID_Check(&blank_id[0], 0x40007000 ) == 1 ) err_code |= 1<<7;
puts ("8: Watchdog");
if ( ID_Check(&apb_watchdog_id[0], CMSDK_WATCHDOG_BASE ) == 1 ) err_code |= 1<<8;
- puts ("9: blank");
- if ( ID_Check(&blank_id[0], 0x40009000 ) == 1 ) err_code |= 1<<9;
- puts ("10: blank");
- if ( ID_Check(&blank_id[0], 0x4000A000 ) == 1 ) err_code |= 1<<10;
+ puts ("9: blank - default slave (generates slave error)");
+ // if ( ID_Check(&blank_id[0], 0x40009000 ) == 1 ) err_code |= 1<<9;
+ puts ("10: blank - default slave (generates slave error)");
+ // if ( ID_Check(&blank_id[0], 0x4000A000 ) == 1 ) err_code |= 1<<10;
puts ("11: APB test slave");
if ( APB_test_slave_Check( 0x4000B000 ) == 1 ) err_code |= 1<<11;
- puts ("12: APB expansion port 12");
- if ( ID_Check(&blank_id[0], 0x4000C000 ) == 1 ) err_code |= 1<<12;
- puts ("13: APB expansion port 13");
- if ( ID_Check(&blank_id[0], 0x4000D000 ) == 1 ) err_code |= 1<<13;
- puts ("14: APB expansion port 14");
+ puts ("12: DMAC 1 (Not Implemented) - Slave Error");
+ // if ( ID_Check(&blank_id[0], 0x4000C000 ) == 1 ) err_code |= 1<<12;
+ puts ("13: blank - default slave (generates slave error)");
+ // if ( ID_Check(&blank_id[0], 0x4000D000 ) == 1 ) err_code |= 1<<13;
+ puts ("14: Debug USRT");
if ( ID_Check(&apb_uart_id[0], CMSDK_USRT2_BASE ) == 1 ) err_code |= 1<<14;
- puts ("15: APB expansion port 15 (optional DMA controller)");
+ puts ("15: DMAC 0 (PL230)");
if ( ID_Check(&pl230_udma_id[0], CMSDK_PL230_BASE ) == 1 ) err_code |= 1<<15;