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Commit 916c2ada authored by dam1n19's avatar dam1n19
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Updated NanoSoC Verification Structure

parent 95c9e5c1
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1 merge request!1changed imem to rom to allow initial program loading, updated bootloader code...
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flist/nanosoc_ip.flist
+ 3
− 1
View file @ 916c2ada
...@@ -42,7 +42,9 @@ $(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/bootrom_0/verilog/nanosoc_reg ...@@ -42,7 +42,9 @@ $(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/bootrom_0/verilog/nanosoc_reg
// NanoSoC Regions - CPU Memories // NanoSoC Regions - CPU Memories
$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/dmem_0/verilog/nanosoc_region_dmem_0.v $(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/dmem_0/verilog/nanosoc_region_dmem_0.v
$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/imem_0/verilog/nanosoc_region_imem_0.v
// TODO: Use ROM Memory for IMEM - switch back to SRAM
$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/imem_0/rom/verilog/nanosoc_region_imem_0.v
// NanoSoC Regions - Expansion Regions // NanoSoC Regions - Expansion Regions
$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/exp/verilog/nanosoc_region_exp.v $(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/exp/verilog/nanosoc_region_exp.v
......
hal/nanosoc_ip.bb
+ 4
− 0
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...@@ -21,4 +21,8 @@ bb_list ...@@ -21,4 +21,8 @@ bb_list
// Temporarily Exclude SoCDebug // Temporarily Exclude SoCDebug
designunit = socdebug_ahb; designunit = socdebug_ahb;
file = $SOCLABS_NANOSOC_TECH_DIR/system/socdebug_tech/controller/verilog/socdebug_ahb.v; file = $SOCLABS_NANOSOC_TECH_DIR/system/socdebug_tech/controller/verilog/socdebug_ahb.v;
// Temporarily Exclude Accelerator Subsystem (just linting NanoSoC)
designunit = accelerator_subsystem;
file = $SOCLABS_PROJECT_DIR/system/src/accelerator_subsystem.v;
} }
\ No newline at end of file
makefile
+ 19
− 10
View file @ 916c2ada
...@@ -123,21 +123,30 @@ LINT_INFO_SOCDEBUG_DIR = $(SOCLABS_SOCDEBUG_TECH_DIR)/hal ...@@ -123,21 +123,30 @@ LINT_INFO_SOCDEBUG_DIR = $(SOCLABS_SOCDEBUG_TECH_DIR)/hal
LINT_TOP = nanosoc_chip_pads LINT_TOP = nanosoc_chip_pads
# MTI option # MTI option
MTI_OPTIONS = +acc MTI_VC_OPTIONS = +acc
MTI_OPTIONS += -suppress 2892 MTI_VC_OPTIONS += -suppress 2892
MTI_VC_OPTIONS = -f $(TBENCH_VC) $(ACCELERATOR_VC) $(ADP_OPTIONS) MTI_VC_OPTIONS += -f $(TBENCH_VC) $(ADP_OPTIONS)
MTI_RUN_OPTIONS = -voptargs=+acc
# VCS option # VCS option
VCS_OPTIONS = +vcs+lic+wait +v2k +lint=all,noTMR,noVCDE -debug VCS_OPTIONS = +vcs+lic+wait +v2k +lint=all,noTMR,noVCDE -debug
VCS_SIM_OPTION = +vcs+lic+wait +vcs+flush+log -assert nopostproc VCS_SIM_OPTION = +vcs+lic+wait +vcs+flush+log -assert nopostproc
VCS_VC_OPTIONS = -f $(TBENCH_VC) $(ACCELERATOR_VC) $(ADP_OPTIONS) VCS_VC_OPTIONS = -f $(TBENCH_VC) $(ADP_OPTIONS)
# XM verilog option # XM verilog option
XMSIM_OPTIONS = -unbuffered -64bit -status -LICQUEUE -f xmsim.args -cdslib cds.lib -hdlvar hdl.var -NBASYNC XMSIM_OPTIONS = -unbuffered -64bit -status -LICQUEUE -f xmsim.args -cdslib cds.lib -hdlvar hdl.var -NBASYNC
XM_VC_OPTIONS = -f $(TBENCH_VC) $(ACCELERATOR_VC) $(ADP_OPTIONS) XM_VC_OPTIONS = -f $(TBENCH_VC) $(ADP_OPTIONS)
HAL_BLACK_BOX = -design_info $(LINT_INFO_DIR)/nanosoc_ip.bb
HAL_BLACK_BOX += -design_info $(LINT_INFO_DIR)/corstone101_ip.bb
HAL_BLACK_BOX += -design_info $(LINT_INFO_SLCOREM0_DIR)/cortexm0_ip.bb
HAL_BLACK_BOX += -design_info $(LINT_INFO_SLDMA230_DIR)/pl230_ip.bb
HAL_BLACK_BOX = -design_info $(LINT_INFO_DIR)/nanosoc_ip.bb -design_info $(LINT_INFO_DIR)/corstone101_ip.bb -design_info $(LINT_INFO_SLCOREM0_DIR)/cortexm0_ip.bb -design_info $(LINT_INFO_SLDMA230_DIR)/pl230_ip.bb HAL_WAIVE = -design_info $(LINT_INFO_DIR)/nanosoc_ip.waive
HAL_WAIVE = -design_info $(LINT_INFO_DIR)/nanosoc_ip.waive -design_info $(LINT_INFO_SLCOREM0_DIR)/slcorem0_ip.waive -design_info $(LINT_INFO_SLDMA230_DIR)/sldma230_ip.waive -design_info $(LINT_INFO_SOCDEBUG_DIR)/socdebug_controller_ip.waive HAL_WAIVE += -design_info $(LINT_INFO_SLCOREM0_DIR)/slcorem0_ip.waive
HAL_WAIVE += -design_info $(LINT_INFO_SLDMA230_DIR)/sldma230_ip.waive
HAL_WAIVE += -design_info $(LINT_INFO_SOCDEBUG_DIR)/socdebug_controller_ip.waive
# Debug Tester image # Debug Tester image
DEBUGTESTER = debugtester DEBUGTESTER = debugtester
...@@ -264,7 +273,7 @@ compile_mti : bootrom ...@@ -264,7 +273,7 @@ compile_mti : bootrom
else \ else \
vlib work; \ vlib work; \
fi fi
cd $(SIM_DIR); vlog -incr -lint +v2k $(MTI_OPTIONS) $(MTI_VC_OPTIONS) $(DEFINES_VC) | tee compile_mti.log cd $(SIM_DIR); vlog -incr -lint +v2k $(MTI_VC_OPTIONS) $(DEFINES_VC) | tee compile_mti.log
# Run simulation in batch mode # Run simulation in batch mode
run_mti : code compile_mti run_mti : code compile_mti
...@@ -274,11 +283,11 @@ run_mti : code compile_mti ...@@ -274,11 +283,11 @@ run_mti : code compile_mti
@echo "run -all" > $(SIM_DIR)/run.tcl.tmp @echo "run -all" > $(SIM_DIR)/run.tcl.tmp
@echo "quit -f" >> $(SIM_DIR)/run.tcl.tmp @echo "quit -f" >> $(SIM_DIR)/run.tcl.tmp
@mv $(SIM_DIR)/run.tcl.tmp $(SIM_DIR)/run.tcl @mv $(SIM_DIR)/run.tcl.tmp $(SIM_DIR)/run.tcl
cd $(SIM_DIR); vsim $(MTI_OPTIONS) -c $(TB_TOP) -do run.tcl | tee logs/run_$(TESTNAME).log ; cd $(SIM_DIR); vsim $(MTI_RUN_OPTIONS) -c $(TB_TOP) -do run.tcl | tee logs/run_$(TESTNAME).log ;
# Run simulation in interactive mode # Run simulation in interactive mode
sim_mti : code compile_mti sim_mti : code compile_mti
cd $(SIM_DIR); vsim $(MTI_OPTIONS) -gui $(TB_TOP) & cd $(SIM_DIR); vsim $(MTI_RUN_OPTIONS) -gui $(TB_TOP) &
# Create work directory # Create work directory
lib_mti : lib_mti :
......
system/nanosoc_regions/exp/verilog/nanosoc_region_exp.v
+ 2
− 2
View file @ 916c2ada
...@@ -41,7 +41,7 @@ module nanosoc_region_exp #( ...@@ -41,7 +41,7 @@ module nanosoc_region_exp #(
accelerator_subsystem #( accelerator_subsystem #(
.SYS_ADDR_W (SYS_ADDR_W), .SYS_ADDR_W (SYS_ADDR_W),
.SYS_DATA_W (SYS_DATA_W) .SYS_DATA_W (SYS_DATA_W)
) u_accelerator_ss ( ) u_ss_accelerator (
.HCLK(HCLK), .HCLK(HCLK),
.HRESETn(HRESETn), .HRESETn(HRESETn),
.HSEL(HSEL), .HSEL(HSEL),
...@@ -61,7 +61,7 @@ module nanosoc_region_exp #( ...@@ -61,7 +61,7 @@ module nanosoc_region_exp #(
); );
`else `else
// Default slave - if no expansion region // Default slave - if no expansion region
cmsdk_ahb_default_slave u_accelerator_ss_default ( cmsdk_ahb_default_slave u_ss_accelerator_default (
.HCLK (HCLK), .HCLK (HCLK),
.HRESETn (HRESETn), .HRESETn (HRESETn),
.HSEL (HSEL), .HSEL (HSEL),
......
system/nanosoc_regions/imem_0/ram/verilog/nanosoc_region_imem_0.v 0 → 100644
+ 62
− 0
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//-----------------------------------------------------------------------------
// Nanosoc CPU Instruction Memory Region (IMEM) - SRAM
// - Region Mapped to: 0x20000000-0x2fffffff
// - Memory Exhibits Wrapping Behaviour
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
module nanosoc_region_imem_0 #(
parameter SYS_ADDR_W = 32, // System Address Width
parameter SYS_DATA_W = 32, // System Data Width
parameter IMEM_RAM_ADDR_W = 14, // Width of IMEM RAM Address - Default 16KB
parameter IMEM_RAM_DATA_W = 32, // Width of IMEM RAM Data Bus - Default 32 bits
parameter IMEM_RAM_FPGA_IMG = "image.hex" // Image to Preload into SRAM
)(
input wire HCLK,
input wire HRESETn,
// AHB connection to Initiator
input wire HSEL,
input wire [SYS_ADDR_W-1:0] HADDR,
input wire [1:0] HTRANS,
input wire [2:0] HSIZE,
input wire [3:0] HPROT,
input wire HWRITE,
input wire HREADY,
input wire [SYS_DATA_W-1:0] HWDATA,
output wire HREADYOUT,
output wire HRESP,
output wire [SYS_DATA_W-1:0] HRDATA
);
// SRAM Instantiation
sl_ahb_sram #(
.SYS_DATA_W (SYS_DATA_W),
.RAM_ADDR_W (IMEM_RAM_ADDR_W),
.RAM_DATA_W (IMEM_RAM_DATA_W),
) u_imem_0 (
// AHB Inputs
.HCLK (HCLK),
.HRESETn (HRESETn),
.HSEL (HSEL),
.HADDR (HADDR [IMEM_RAM_ADDR_W-1:0]),
.HTRANS (HTRANS),
.HSIZE (HSIZE),
.HWRITE (HWRITE),
.HWDATA (HWDATA),
.HREADY (HREADY),
// AHB Outputs
.HREADYOUT (HREADYOUT),
.HRDATA (HRDATA),
.HRESP (HRESP)
);
endmodule
\ No newline at end of file
system/nanosoc_regions/imem_0/rom/verilog/nanosoc_region_imem_0.v 0 → 100644
+ 63
− 0
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//-----------------------------------------------------------------------------
// Nanosoc CPU Instruction Memory Region (IMEM) - ROM
// - Region Mapped to: 0x20000000-0x2fffffff
// - Memory Exhibits Wrapping Behaviour
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
module nanosoc_region_imem_0 #(
parameter SYS_ADDR_W = 32, // System Address Width
parameter SYS_DATA_W = 32, // System Data Width
parameter IMEM_RAM_ADDR_W = 14, // Width of IMEM RAM Address - Default 16KB
parameter IMEM_RAM_DATA_W = 32, // Width of IMEM RAM Data Bus - Default 32 bits
parameter IMEM_RAM_FPGA_IMG = "image.hex" // Image to Preload into SRAM
)(
input wire HCLK,
input wire HRESETn,
// AHB connection to Initiator
input wire HSEL,
input wire [SYS_ADDR_W-1:0] HADDR,
input wire [1:0] HTRANS,
input wire [2:0] HSIZE,
input wire [3:0] HPROT,
input wire HWRITE,
input wire HREADY,
input wire [SYS_DATA_W-1:0] HWDATA,
output wire HREADYOUT,
output wire HRESP,
output wire [SYS_DATA_W-1:0] HRDATA
);
// ROM Instantiation
sl_ahb_rom #(
.SYS_DATA_W (SYS_DATA_W),
.RAM_ADDR_W (IMEM_RAM_ADDR_W),
.RAM_DATA_W (IMEM_RAM_DATA_W),
.FILENAME (IMEM_RAM_FPGA_IMG)
) u_imem_0 (
// AHB Inputs
.HCLK (HCLK),
.HRESETn (HRESETn),
.HSEL (HSEL),
.HADDR (HADDR [IMEM_RAM_ADDR_W-1:0]),
.HTRANS (HTRANS),
.HSIZE (HSIZE),
.HWRITE (HWRITE),
.HWDATA (HWDATA),
.HREADY (HREADY),
// AHB Outputs
.HREADYOUT (HREADYOUT),
.HRDATA (HRDATA),
.HRESP (HRESP)
);
endmodule
\ No newline at end of file
system/nanosoc_regions/imem_0/verilog/nanosoc_region_imem_0.v deleted 100644 → 0
+ 0
− 64
View file @ 95c9e5c1
//-----------------------------------------------------------------------------
// Nanosoc CPU Instruction Memory Region (IMEM)
// - Region Mapped to: 0x20000000-0x2fffffff
// - Memory Exhibits Wrapping Behaviour
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
module nanosoc_region_imem_0 #(
parameter SYS_ADDR_W = 32, // System Address Width
parameter SYS_DATA_W = 32, // System Data Width
parameter IMEM_RAM_ADDR_W = 14, // Width of IMEM RAM Address - Default 16KB
parameter IMEM_RAM_DATA_W = 32, // Width of IMEM RAM Data Bus - Default 32 bits
parameter IMEM_RAM_FPGA_IMG = "image.hex" // Image to Preload into SRAM
)(
input wire HCLK,
input wire HRESETn,
// AHB connection to Initiator
input wire HSEL,
input wire [SYS_ADDR_W-1:0] HADDR,
input wire [1:0] HTRANS,
input wire [2:0] HSIZE,
input wire [3:0] HPROT,
input wire HWRITE,
input wire HREADY,
input wire [SYS_DATA_W-1:0] HWDATA,
output wire HREADYOUT,
output wire HRESP,
output wire [SYS_DATA_W-1:0] HRDATA
);
// SRAM Instantiation
// sl_ahb_sram #(
sl_ahb_rom #(
.SYS_DATA_W (SYS_DATA_W),
.RAM_ADDR_W (IMEM_RAM_ADDR_W),
.RAM_DATA_W (IMEM_RAM_DATA_W),
.FILENAME (IMEM_RAM_FPGA_IMG)
) u_imem_0 (
// AHB Inputs
.HCLK (HCLK),
.HRESETn (HRESETn),
.HSEL (HSEL),
.HADDR (HADDR [IMEM_RAM_ADDR_W-1:0]),
.HTRANS (HTRANS),
.HSIZE (HSIZE),
.HWRITE (HWRITE),
.HWDATA (HWDATA),
.HREADY (HREADY),
// AHB Outputs
.HREADYOUT (HREADYOUT),
.HRDATA (HRDATA),
.HRESP (HRESP)
);
endmodule
\ No newline at end of file
system/nanosoc_system/verilog/nanosoc_system.v
+ 6
− 6
View file @ 916c2ada
...@@ -257,7 +257,7 @@ module nanosoc_system #( ...@@ -257,7 +257,7 @@ module nanosoc_system #(
.IMEM_RAM_FPGA_IMG (IMEM_RAM_FPGA_IMG), .IMEM_RAM_FPGA_IMG (IMEM_RAM_FPGA_IMG),
.DMEM_RAM_ADDR_W (DMEM_RAM_ADDR_W), .DMEM_RAM_ADDR_W (DMEM_RAM_ADDR_W),
.DMEM_RAM_DATA_W (DMEM_RAM_DATA_W) .DMEM_RAM_DATA_W (DMEM_RAM_DATA_W)
) u_cpu_ss ( ) u_ss_cpu (
// System Input Clocks and Resets // System Input Clocks and Resets
.SYS_FCLK(SYS_FCLK), .SYS_FCLK(SYS_FCLK),
.SYS_SYSRESETn(SYS_SYSRESETn), .SYS_SYSRESETn(SYS_SYSRESETn),
...@@ -448,7 +448,7 @@ module nanosoc_system #( ...@@ -448,7 +448,7 @@ module nanosoc_system #(
.DMAC_1_CFG_ADDR_W(DMAC_1_CFG_ADDR_W), .DMAC_1_CFG_ADDR_W(DMAC_1_CFG_ADDR_W),
.DMAC_0_CHANNEL_NUM(DMAC_0_CHANNEL_NUM), .DMAC_0_CHANNEL_NUM(DMAC_0_CHANNEL_NUM),
.DMAC_1_CHANNEL_NUM(DMAC_1_CHANNEL_NUM) .DMAC_1_CHANNEL_NUM(DMAC_1_CHANNEL_NUM)
) u_dma_ss ( ) u_ss_dma (
// System AHB Clocks and Resets // System AHB Clocks and Resets
.SYS_HCLK(SYS_HCLK), .SYS_HCLK(SYS_HCLK),
.SYS_HRESETn(SYS_HRESETn), .SYS_HRESETn(SYS_HRESETn),
...@@ -561,7 +561,7 @@ module nanosoc_system #( ...@@ -561,7 +561,7 @@ module nanosoc_system #(
.FT1248_WIDTH(FT1248_WIDTH), .FT1248_WIDTH(FT1248_WIDTH),
.FT1248_CLKON(FT1248_CLKON), .FT1248_CLKON(FT1248_CLKON),
.FT1248_CLKDIV(FT1248_CLKDIV) .FT1248_CLKDIV(FT1248_CLKDIV)
) u_debug_ss ( ) u_ss_debug (
// System Clocks and Resets // System Clocks and Resets
.SYS_HCLK(SYS_HCLK), .SYS_HCLK(SYS_HCLK),
.SYS_HRESETn(SYS_HRESETn), .SYS_HRESETn(SYS_HRESETn),
...@@ -686,7 +686,7 @@ module nanosoc_system #( ...@@ -686,7 +686,7 @@ module nanosoc_system #(
// SRAM High Parameters // SRAM High Parameters
.EXPRAM_H_RAM_ADDR_W(EXPRAM_H_RAM_ADDR_W), .EXPRAM_H_RAM_ADDR_W(EXPRAM_H_RAM_ADDR_W),
.EXPRAM_H_RAM_DATA_W(EXPRAM_H_RAM_DATA_W) .EXPRAM_H_RAM_DATA_W(EXPRAM_H_RAM_DATA_W)
) u_expansion_ss ( ) u_ss_expansion (
// System Clocks and Resets // System Clocks and Resets
.SYS_HCLK(SYS_HCLK), .SYS_HCLK(SYS_HCLK),
.SYS_HRESETn(SYS_HRESETn), .SYS_HRESETn(SYS_HRESETn),
...@@ -818,7 +818,7 @@ module nanosoc_system #( ...@@ -818,7 +818,7 @@ module nanosoc_system #(
.NANOSOC_PARTNUMBER(NANOSOC_PARTNUMBER), .NANOSOC_PARTNUMBER(NANOSOC_PARTNUMBER),
.NANOSOC_REVISION(NANOSOC_REVISION), .NANOSOC_REVISION(NANOSOC_REVISION),
.CLKGATE_PRESENT(CLKGATE_PRESENT) .CLKGATE_PRESENT(CLKGATE_PRESENT)
) u_systemctrl_ss ( ) u_ss_systemctrl (
// Free-running and Crystal Clock Output // Free-running and Crystal Clock Output
.SYS_CLK (SYS_CLK), // System Input Clock .SYS_CLK (SYS_CLK), // System Input Clock
.SYS_FCLK(SYS_FCLK), // Free-running system clock .SYS_FCLK(SYS_FCLK), // Free-running system clock
...@@ -947,7 +947,7 @@ module nanosoc_system #( ...@@ -947,7 +947,7 @@ module nanosoc_system #(
nanosoc_ss_interconnect #( nanosoc_ss_interconnect #(
.SYS_ADDR_W (SYS_ADDR_W), // System Address Width .SYS_ADDR_W (SYS_ADDR_W), // System Address Width
.SYS_DATA_W (SYS_DATA_W) // System Data Width .SYS_DATA_W (SYS_DATA_W) // System Data Width
) u_interconnect_ss ( ) u_ss_interconnect (
// System Clocks, Resets, and Control // System Clocks, Resets, and Control
.SYS_HCLK(SYS_HCLK), .SYS_HCLK(SYS_HCLK),
.SYS_HRESETn(SYS_HRESETn), .SYS_HRESETn(SYS_HRESETn),
......
verif/verilog/nanosoc_tb.v → verif/tb/verilog/nanosoc_tb.v
+ 27
− 25
View file @ 916c2ada
...@@ -389,7 +389,7 @@ nanosoc_ft1248x1_track ...@@ -389,7 +389,7 @@ nanosoc_ft1248x1_track
`ifdef CORTEX_M0 `ifdef CORTEX_M0
`ifdef USE_TARMAC `ifdef USE_TARMAC
`define ARM_CM0IK_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_system.u_cpu_ss.u_cpu_0.u_slcorem0_integration.u_cortexm0 `define ARM_CM0IK_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_system.u_ss_cpu.u_cpu_0.u_slcorem0_integration.u_cortexm0
CORTEXM0 CORTEXM0
#(.ACG(1), .AHBSLV(0), .BE(0), .BKPT(4), #(.ACG(1), .AHBSLV(0), .BE(0), .BKPT(4),
...@@ -523,7 +523,7 @@ nanosoc_ft1248x1_track ...@@ -523,7 +523,7 @@ nanosoc_ft1248x1_track
// - log the RTL Inuts/outputs/internal-state of this traccking DMAC // - log the RTL Inuts/outputs/internal-state of this traccking DMAC
// -------------------------------------------------------------------------------- // --------------------------------------------------------------------------------
`define DMAC_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_system.u_dma_ss.u_dmac_0.u_pl230_udma `define DMAC_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_system.u_ss_dma.u_dmac_0.u_pl230_udma
pl230_udma u_track_pl230_udma ( pl230_udma u_track_pl230_udma (
// Clock and Reset // Clock and Reset
...@@ -597,29 +597,31 @@ nanosoc_ft1248x1_track ...@@ -597,29 +597,31 @@ nanosoc_ft1248x1_track
// Tracking Accelerator logging support // Tracking Accelerator logging support
// -------------------------------------------------------------------------------- // --------------------------------------------------------------------------------
// `define ACC_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_nanosoc_exp_wrapper `define ACC_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_system.u_ss_expansion.u_region_exp
// nanosoc_acc_log_to_file #(.FILENAME("logs/acc_exp.log"),.TIMESTAMP(1)) nanosoc_accelerator_ss_logger #(
// u_nanosoc_acc_log_to_file ( .FILENAME("logs/acc_exp.log"),
// .HCLK (`ACC_PATH.HCLK ), .TIMESTAMP(1)
// .HRESETn (`ACC_PATH.HRESETn ), ) u_accelerator_ss_logger (
// .HSEL_i (`ACC_PATH.HSEL_i ), .HCLK (`ACC_PATH.HCLK ),
// .HADDR_i (`ACC_PATH.HADDR_i ), .HRESETn (`ACC_PATH.HRESETn ),
// .HTRANS_i (`ACC_PATH.HTRANS_i ), .HSEL_i (`ACC_PATH.HSEL ),
// .HWRITE_i (`ACC_PATH.HWRITE_i ), .HADDR_i (`ACC_PATH.HADDR ),
// .HSIZE_i (`ACC_PATH.HSIZE_i ), .HTRANS_i (`ACC_PATH.HTRANS ),
// .HPROT_i (`ACC_PATH.HPROT_i ), .HWRITE_i (`ACC_PATH.HWRITE ),
// .HWDATA_i (`ACC_PATH.HWDATA_i ), .HSIZE_i (`ACC_PATH.HSIZE ),
// .HREADY_i (`ACC_PATH.HREADY_i ), .HPROT_i (`ACC_PATH.HPROT ),
// .HRDATA_o (`ACC_PATH.HRDATA_o ), .HWDATA_i (`ACC_PATH.HWDATA ),
// .HREADYOUT_o (`ACC_PATH.HREADYOUT_o ), .HREADY_i (`ACC_PATH.HREADY ),
// .HRESP_o (`ACC_PATH.HRESP_o ), .HRDATA_o (`ACC_PATH.HRDATA ),
// .exp_drq_ip_o (`ACC_PATH.exp_drq_ip_o ), .HREADYOUT_o (`ACC_PATH.HREADYOUT ),
// .exp_dlast_ip_i (`ACC_PATH.exp_dlast_ip_i), .HRESP_o (`ACC_PATH.HRESP ),
// .exp_drq_op_o (`ACC_PATH.exp_drq_op_o ), .exp_drq_ip_o (`ACC_PATH.EXP_DRQ[0] ),
// .exp_dlast_op_i (`ACC_PATH.exp_dlast_op_i), .exp_dlast_ip_i (`ACC_PATH.EXP_DLAST[0] ),
// .exp_irq_o (`ACC_PATH.exp_irq_o ) .exp_drq_op_o (`ACC_PATH.EXP_DRQ[1] ),
// ); .exp_dlast_op_i (`ACC_PATH.EXP_DLAST[1] ),
.exp_irq_o (`ACC_PATH.EXP_IRQ )
);
// -------------------------------------------------------------------------------- // --------------------------------------------------------------------------------
......
verif/verilog/nanosoc_tb_qs.v → verif/tb/verilog/nanosoc_tb_qs.v
+ 27
− 100
View file @ 916c2ada
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
// NanoSoC Testbench adpated from example Cortex-M0 controller testbench // NanoSoC Testbench adpated from example Cortex-M0 controller testbench - QUICKSTART
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. // A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
// //
// Contributors // Contributors
...@@ -389,7 +389,7 @@ nanosoc_ft1248x1_track ...@@ -389,7 +389,7 @@ nanosoc_ft1248x1_track
`ifdef CORTEX_M0 `ifdef CORTEX_M0
`ifdef USE_TARMAC `ifdef USE_TARMAC
`define ARM_CM0IK_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_system.u_cpu_ss.u_cpu_0.u_slcorem0_integration.u_cortexm0 `define ARM_CM0IK_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_system.u_ss_cpu.u_cpu_0.u_slcorem0_integration.u_cortexm0
CORTEXM0 CORTEXM0
#(.ACG(1), .AHBSLV(0), .BE(0), .BKPT(4), #(.ACG(1), .AHBSLV(0), .BE(0), .BKPT(4),
...@@ -517,109 +517,36 @@ nanosoc_ft1248x1_track ...@@ -517,109 +517,36 @@ nanosoc_ft1248x1_track
`endif // USE_TARMAC `endif // USE_TARMAC
`endif // CORTEX_M0 `endif // CORTEX_M0
// --------------------------------------------------------------------------------
// Tracking DMA logging support
// - Track inputs to on-chip PL230 DMAC and replicate state and outputs in testbench
// - log the RTL Inuts/outputs/internal-state of this traccking DMAC
// --------------------------------------------------------------------------------
// `define DMAC_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_system.u_dma_ss.u_dmac_0.u_pl230_udma
// pl230_udma u_track_pl230_udma (
// // Clock and Reset
// .hclk (`DMAC_PATH.hclk),
// .hresetn (`DMAC_PATH.hresetn),
// // DMA Control
// .dma_req (`DMAC_PATH.dma_req),
// .dma_sreq (`DMAC_PATH.dma_sreq),
// .dma_waitonreq (`DMAC_PATH.dma_waitonreq),
// .dma_stall (`DMAC_PATH.dma_stall),
// .dma_active ( ),
// .dma_done ( ),
// .dma_err ( ),
// // AHB-Lite Master Interface
// .hready (`DMAC_PATH.hready),
// .hresp (`DMAC_PATH.hresp),
// .hrdata (`DMAC_PATH.hrdata),
// .htrans ( ),
// .hwrite ( ),
// .haddr ( ),
// .hsize ( ),
// .hburst ( ),
// .hmastlock ( ),
// .hprot ( ),
// .hwdata ( ),
// // APB Slave Interface
// .pclken (`DMAC_PATH.pclken),
// .psel (`DMAC_PATH.psel),
// .pen (`DMAC_PATH.pen),
// .pwrite (`DMAC_PATH.pwrite),
// .paddr (`DMAC_PATH.paddr),
// .pwdata (`DMAC_PATH.pwdata),
// .prdata ( )
// );
// `define DMAC_TRACK_PATH u_track_pl230_udma
// nanosoc_dma_log_to_file #(.FILENAME("logs/dma230.log"),.NUM_CHNLS(2),.NUM_CHNL_BITS(1),.TIMESTAMP(1))
// u_nanosoc_dma_log_to_file (
// .hclk (`DMAC_TRACK_PATH.hclk),
// .hresetn (`DMAC_TRACK_PATH.hresetn),
// // AHB-Lite Master Interface
// .hready (`DMAC_TRACK_PATH.hready),
// .hresp (`DMAC_TRACK_PATH.hresp),
// .hrdata (`DMAC_TRACK_PATH.hrdata),
// .htrans (`DMAC_TRACK_PATH.htrans),
// .hwrite (`DMAC_TRACK_PATH.hwrite),
// .haddr (`DMAC_TRACK_PATH.haddr),
// .hsize (`DMAC_TRACK_PATH.hsize),
// .hburst (`DMAC_TRACK_PATH.hburst),
// .hprot (`DMAC_TRACK_PATH.hprot),
// .hwdata (`DMAC_TRACK_PATH.hwdata),
// // APB control interface
// .pclken (`DMAC_TRACK_PATH.pclken),
// .psel (`DMAC_TRACK_PATH.psel),
// .pen (`DMAC_TRACK_PATH.pen),
// .pwrite (`DMAC_TRACK_PATH.pwrite),
// .paddr (`DMAC_TRACK_PATH.paddr),
// .pwdata (`DMAC_TRACK_PATH.pwdata),
// .prdata (`DMAC_TRACK_PATH.prdata),
// // DMA Control
// .dma_req (`DMAC_TRACK_PATH.dma_req),
// .dma_active (`DMAC_TRACK_PATH.dma_active),
// .dma_done (`DMAC_TRACK_PATH.dma_done),
// // DMA state from tracking RTL model
// .dma_chnl (`DMAC_TRACK_PATH.u_pl230_ahb_ctrl.current_chnl),
// .dma_ctrl_state(`DMAC_TRACK_PATH.u_pl230_ahb_ctrl.ctrl_state)
// );
// -------------------------------------------------------------------------------- // --------------------------------------------------------------------------------
// Tracking Accelerator logging support // Tracking Accelerator logging support
// -------------------------------------------------------------------------------- // --------------------------------------------------------------------------------
// `define ACC_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_nanosoc_exp_wrapper `define ACC_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_system.u_ss_expansion.u_region_exp
// nanosoc_acc_log_to_file #(.FILENAME("logs/acc_exp.log"),.TIMESTAMP(1)) nanosoc_accelerator_ss_logger #(
// u_nanosoc_acc_log_to_file ( .FILENAME("logs/acc_exp.log"),
// .HCLK (`ACC_PATH.HCLK ), .TIMESTAMP(1)
// .HRESETn (`ACC_PATH.HRESETn ), ) u_accelerator_ss_logger (
// .HSEL_i (`ACC_PATH.HSEL_i ), .HCLK (`ACC_PATH.HCLK ),
// .HADDR_i (`ACC_PATH.HADDR_i ), .HRESETn (`ACC_PATH.HRESETn ),
// .HTRANS_i (`ACC_PATH.HTRANS_i ), .HSEL_i (`ACC_PATH.HSEL ),
// .HWRITE_i (`ACC_PATH.HWRITE_i ), .HADDR_i (`ACC_PATH.HADDR ),
// .HSIZE_i (`ACC_PATH.HSIZE_i ), .HTRANS_i (`ACC_PATH.HTRANS ),
// .HPROT_i (`ACC_PATH.HPROT_i ), .HWRITE_i (`ACC_PATH.HWRITE ),
// .HWDATA_i (`ACC_PATH.HWDATA_i ), .HSIZE_i (`ACC_PATH.HSIZE ),
// .HREADY_i (`ACC_PATH.HREADY_i ), .HPROT_i (`ACC_PATH.HPROT ),
// .HRDATA_o (`ACC_PATH.HRDATA_o ), .HWDATA_i (`ACC_PATH.HWDATA ),
// .HREADYOUT_o (`ACC_PATH.HREADYOUT_o ), .HREADY_i (`ACC_PATH.HREADY ),
// .HRESP_o (`ACC_PATH.HRESP_o ), .HRDATA_o (`ACC_PATH.HRDATA ),
// .exp_drq_ip_o (`ACC_PATH.exp_drq_ip_o ), .HREADYOUT_o (`ACC_PATH.HREADYOUT ),
// .exp_dlast_ip_i (`ACC_PATH.exp_dlast_ip_i), .HRESP_o (`ACC_PATH.HRESP ),
// .exp_drq_op_o (`ACC_PATH.exp_drq_op_o ), .exp_drq_ip_o (`ACC_PATH.EXP_DRQ[0] ),
// .exp_dlast_op_i (`ACC_PATH.exp_dlast_op_i), .exp_dlast_ip_i (`ACC_PATH.EXP_DLAST[0] ),
// .exp_irq_o (`ACC_PATH.exp_irq_o ) .exp_drq_op_o (`ACC_PATH.EXP_DRQ[1] ),
// ); .exp_dlast_op_i (`ACC_PATH.EXP_DLAST[1] ),
.exp_irq_o (`ACC_PATH.EXP_IRQ )
);
// -------------------------------------------------------------------------------- // --------------------------------------------------------------------------------
......
verif/verilog/nanosoc_acc_log_to_file.v → verif/trace/verilog/nanosoc_accelerator_ss_logger.v
+ 55
− 53
View file @ 916c2ada
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
// AHB transaction logger, developed for DMA integration testing // NanoSoC Accelerator Subsystem AHB Transaction Logger
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. // A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
// //
// Contributors // Contributors
...@@ -9,31 +9,32 @@ ...@@ -9,31 +9,32 @@
// Copyright (C) 2023, SoC Labs (www.soclabs.org) // Copyright (C) 2023, SoC Labs (www.soclabs.org)
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
module nanosoc_acc_log_to_file module nanosoc_accelerator_ss_logger #(
#(parameter FILENAME = "accelerator.log", parameter FILENAME = "accelerator.log",
parameter AHBADDRWIDTH = 29, parameter SYS_ADDR_W = 32,
parameter CFGNUMIRQ = 1, parameter SYS_DATA_W = 32,
parameter TIMESTAMP = 1) parameter IRQ_NUM = 4,
( parameter TIMESTAMP = 1
)(
input wire HCLK, // Clock input wire HCLK, // Clock
input wire HRESETn, // Reset input wire HRESETn, // Reset
input wire HSEL_i, // Device select input wire HSEL_i, // Device select
input wire [AHBADDRWIDTH-1:0] HADDR_i, // Address for byte select input wire [SYS_ADDR_W-1:0] HADDR_i, // Address for byte select
input wire [1:0] HTRANS_i, // Transfer control input wire [1:0] HTRANS_i, // Transfer control
input wire [2:0] HSIZE_i, // Transfer size input wire [2:0] HSIZE_i, // Transfer size
input wire [3:0] HPROT_i, // Protection control input wire [3:0] HPROT_i, // Protection control
input wire HWRITE_i, // Write control input wire HWRITE_i, // Write control
input wire HREADY_i, // Transfer phase done input wire HREADY_i, // Transfer phase done
input wire [31:0] HWDATA_i, // Write data input wire [SYS_DATA_W-1:0] HWDATA_i, // Write data
input wire HREADYOUT_o, // Device ready input wire HREADYOUT_o, // Device ready
input wire [31:0] HRDATA_o, // Read data output input wire [SYS_DATA_W-1:0] HRDATA_o, // Read data output
input wire HRESP_o, // Device response input wire HRESP_o, // Device response
// stream data // AXI-Stream Data
input wire exp_drq_ip_o, // (to) DMAC input burst request input wire exp_drq_ip_o, // (to) DMAC input burst request
input wire exp_dlast_ip_i, // (from) DMAC input burst end (last transfer) input wire exp_dlast_ip_i, // (from) DMAC input burst end (last transfer)
input wire exp_drq_op_o, // (to) DMAC output dma burst request input wire exp_drq_op_o, // (to) DMAC output dma burst request
input wire exp_dlast_op_i, // (from) DMAC output burst end (last transfer) input wire exp_dlast_op_i, // (from) DMAC output burst end (last transfer)
input wire [CFGNUMIRQ-1:0] exp_irq_o input wire [IRQ_NUM-1:0] exp_irq_o
); );
...@@ -44,7 +45,7 @@ module nanosoc_acc_log_to_file ...@@ -44,7 +45,7 @@ module nanosoc_acc_log_to_file
// -------------------------------------------------------------------------- // --------------------------------------------------------------------------
reg sel_r; reg sel_r;
reg [AHBADDRWIDTH-1:0] addr_r; reg [SYS_ADDR_W-1:0] addr_r;
reg wcyc_r; reg wcyc_r;
reg rcyc_r; reg rcyc_r;
reg [3:0] byte4_r; reg [3:0] byte4_r;
...@@ -80,7 +81,8 @@ module nanosoc_acc_log_to_file ...@@ -80,7 +81,8 @@ module nanosoc_acc_log_to_file
byte4_r <= (HSEL_i & HTRANS_i[1]) ? byte_nxt[3:0] : 4'b0000; byte4_r <= (HSEL_i & HTRANS_i[1]) ? byte_nxt[3:0] : 4'b0000;
end end
wire [31:0] hdata = (wcyc_r)? HWDATA_i : HRDATA_o; wire [SYS_DATA_W-1:0] hdata;
assign hdata = (wcyc_r)? HWDATA_i : HRDATA_o;
//---------------------------------------------- //----------------------------------------------
//-- File I/O //-- File I/O
...@@ -93,13 +95,13 @@ module nanosoc_acc_log_to_file ...@@ -93,13 +95,13 @@ module nanosoc_acc_log_to_file
reg exp_dlast_ip_i_prev; reg exp_dlast_ip_i_prev;
reg exp_drq_op_o_prev; reg exp_drq_op_o_prev;
reg exp_dlast_op_i_prev; reg exp_dlast_op_i_prev;
reg [CFGNUMIRQ-1:0] exp_irq_prev; reg [IRQ_NUM-1:0] exp_irq_prev;
wire exp_drq_ip_change; wire exp_drq_ip_change;
wire exp_dlast_ip_change; wire exp_dlast_ip_change;
wire exp_drq_op_change; wire exp_drq_op_change;
wire exp_dlast_op_change; wire exp_dlast_op_change;
wire [CFGNUMIRQ-1:0] exp_irq_change; wire [IRQ_NUM-1:0] exp_irq_change;
wire irq_change; wire irq_change;
wire drq_change; wire drq_change;
wire any_change; wire any_change;
...@@ -118,7 +120,7 @@ module nanosoc_acc_log_to_file ...@@ -118,7 +120,7 @@ module nanosoc_acc_log_to_file
exp_dlast_ip_i_prev <= 1'b0; exp_dlast_ip_i_prev <= 1'b0;
exp_drq_op_o_prev <= 1'b0; exp_drq_op_o_prev <= 1'b0;
exp_dlast_op_i_prev <= 1'b0; exp_dlast_op_i_prev <= 1'b0;
exp_irq_prev <= {CFGNUMIRQ{1'b0}}; exp_irq_prev <= {IRQ_NUM{1'b0}};
end else if (HREADY_i) end else if (HREADY_i)
begin begin
......
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