diff --git a/flist/nanosoc_ip.flist b/flist/nanosoc_ip.flist
index 4c6e3e16689ce62077e5e51dcf940f908540b56c..a0d3f72c4edea362f575444f5962f782b2f5adb5 100644
--- a/flist/nanosoc_ip.flist
+++ b/flist/nanosoc_ip.flist
@@ -42,7 +42,9 @@ $(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/bootrom_0/verilog/nanosoc_reg
// NanoSoC Regions - CPU Memories
$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/dmem_0/verilog/nanosoc_region_dmem_0.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/imem_0/verilog/nanosoc_region_imem_0.v
+
+// TODO: Use ROM Memory for IMEM - switch back to SRAM
+$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/imem_0/rom/verilog/nanosoc_region_imem_0.v
// NanoSoC Regions - Expansion Regions
$(SOCLABS_NANOSOC_TECH_DIR)/system/nanosoc_regions/exp/verilog/nanosoc_region_exp.v
diff --git a/hal/nanosoc_ip.bb b/hal/nanosoc_ip.bb
index dd10f58e1bc460785ce5bea9f1809ca228df140a..0c16ed00565caafe62fd36a2aeebe47a245eecc6 100644
--- a/hal/nanosoc_ip.bb
+++ b/hal/nanosoc_ip.bb
@@ -21,4 +21,8 @@ bb_list
// Temporarily Exclude SoCDebug
designunit = socdebug_ahb;
file = $SOCLABS_NANOSOC_TECH_DIR/system/socdebug_tech/controller/verilog/socdebug_ahb.v;
+
+ // Temporarily Exclude Accelerator Subsystem (just linting NanoSoC)
+ designunit = accelerator_subsystem;
+ file = $SOCLABS_PROJECT_DIR/system/src/accelerator_subsystem.v;
}
\ No newline at end of file
diff --git a/makefile b/makefile
index df5aa1e0d99c125cb391ad6b6948c615c215c9a7..a33b48702a635ce57e48661b0bb669c56ef088e2 100644
--- a/makefile
+++ b/makefile
@@ -123,21 +123,30 @@ LINT_INFO_SOCDEBUG_DIR = $(SOCLABS_SOCDEBUG_TECH_DIR)/hal
LINT_TOP = nanosoc_chip_pads
# MTI option
-MTI_OPTIONS = +acc
-MTI_OPTIONS += -suppress 2892
-MTI_VC_OPTIONS = -f $(TBENCH_VC) $(ACCELERATOR_VC) $(ADP_OPTIONS)
+MTI_VC_OPTIONS = +acc
+MTI_VC_OPTIONS += -suppress 2892
+MTI_VC_OPTIONS += -f $(TBENCH_VC) $(ADP_OPTIONS)
+
+MTI_RUN_OPTIONS = -voptargs=+acc
# VCS option
VCS_OPTIONS = +vcs+lic+wait +v2k +lint=all,noTMR,noVCDE -debug
VCS_SIM_OPTION = +vcs+lic+wait +vcs+flush+log -assert nopostproc
-VCS_VC_OPTIONS = -f $(TBENCH_VC) $(ACCELERATOR_VC) $(ADP_OPTIONS)
+VCS_VC_OPTIONS = -f $(TBENCH_VC) $(ADP_OPTIONS)
# XM verilog option
XMSIM_OPTIONS = -unbuffered -64bit -status -LICQUEUE -f xmsim.args -cdslib cds.lib -hdlvar hdl.var -NBASYNC
-XM_VC_OPTIONS = -f $(TBENCH_VC) $(ACCELERATOR_VC) $(ADP_OPTIONS)
+XM_VC_OPTIONS = -f $(TBENCH_VC) $(ADP_OPTIONS)
+
+HAL_BLACK_BOX = -design_info $(LINT_INFO_DIR)/nanosoc_ip.bb
+HAL_BLACK_BOX += -design_info $(LINT_INFO_DIR)/corstone101_ip.bb
+HAL_BLACK_BOX += -design_info $(LINT_INFO_SLCOREM0_DIR)/cortexm0_ip.bb
+HAL_BLACK_BOX += -design_info $(LINT_INFO_SLDMA230_DIR)/pl230_ip.bb
-HAL_BLACK_BOX = -design_info $(LINT_INFO_DIR)/nanosoc_ip.bb -design_info $(LINT_INFO_DIR)/corstone101_ip.bb -design_info $(LINT_INFO_SLCOREM0_DIR)/cortexm0_ip.bb -design_info $(LINT_INFO_SLDMA230_DIR)/pl230_ip.bb
-HAL_WAIVE = -design_info $(LINT_INFO_DIR)/nanosoc_ip.waive -design_info $(LINT_INFO_SLCOREM0_DIR)/slcorem0_ip.waive -design_info $(LINT_INFO_SLDMA230_DIR)/sldma230_ip.waive -design_info $(LINT_INFO_SOCDEBUG_DIR)/socdebug_controller_ip.waive
+HAL_WAIVE = -design_info $(LINT_INFO_DIR)/nanosoc_ip.waive
+HAL_WAIVE += -design_info $(LINT_INFO_SLCOREM0_DIR)/slcorem0_ip.waive
+HAL_WAIVE += -design_info $(LINT_INFO_SLDMA230_DIR)/sldma230_ip.waive
+HAL_WAIVE += -design_info $(LINT_INFO_SOCDEBUG_DIR)/socdebug_controller_ip.waive
# Debug Tester image
DEBUGTESTER = debugtester
@@ -264,7 +273,7 @@ compile_mti : bootrom
else \
vlib work; \
fi
- cd $(SIM_DIR); vlog -incr -lint +v2k $(MTI_OPTIONS) $(MTI_VC_OPTIONS) $(DEFINES_VC) | tee compile_mti.log
+ cd $(SIM_DIR); vlog -incr -lint +v2k $(MTI_VC_OPTIONS) $(DEFINES_VC) | tee compile_mti.log
# Run simulation in batch mode
run_mti : code compile_mti
@@ -274,11 +283,11 @@ run_mti : code compile_mti
@echo "run -all" > $(SIM_DIR)/run.tcl.tmp
@echo "quit -f" >> $(SIM_DIR)/run.tcl.tmp
@mv $(SIM_DIR)/run.tcl.tmp $(SIM_DIR)/run.tcl
- cd $(SIM_DIR); vsim $(MTI_OPTIONS) -c $(TB_TOP) -do run.tcl | tee logs/run_$(TESTNAME).log ;
+ cd $(SIM_DIR); vsim $(MTI_RUN_OPTIONS) -c $(TB_TOP) -do run.tcl | tee logs/run_$(TESTNAME).log ;
# Run simulation in interactive mode
sim_mti : code compile_mti
- cd $(SIM_DIR); vsim $(MTI_OPTIONS) -gui $(TB_TOP) &
+ cd $(SIM_DIR); vsim $(MTI_RUN_OPTIONS) -gui $(TB_TOP) &
# Create work directory
lib_mti :
diff --git a/system/nanosoc_regions/exp/verilog/nanosoc_region_exp.v b/system/nanosoc_regions/exp/verilog/nanosoc_region_exp.v
index 186f9f1616c7c09af558055198bec471e4ab18a6..0a1ad683b42d99b5b8c6f514c3fe13959119deb9 100644
--- a/system/nanosoc_regions/exp/verilog/nanosoc_region_exp.v
+++ b/system/nanosoc_regions/exp/verilog/nanosoc_region_exp.v
@@ -41,7 +41,7 @@ module nanosoc_region_exp #(
accelerator_subsystem #(
.SYS_ADDR_W (SYS_ADDR_W),
.SYS_DATA_W (SYS_DATA_W)
- ) u_accelerator_ss (
+ ) u_ss_accelerator (
.HCLK(HCLK),
.HRESETn(HRESETn),
.HSEL(HSEL),
@@ -61,7 +61,7 @@ module nanosoc_region_exp #(
);
`else
// Default slave - if no expansion region
- cmsdk_ahb_default_slave u_accelerator_ss_default (
+ cmsdk_ahb_default_slave u_ss_accelerator_default (
.HCLK (HCLK),
.HRESETn (HRESETn),
.HSEL (HSEL),
diff --git a/system/nanosoc_regions/imem_0/ram/verilog/nanosoc_region_imem_0.v b/system/nanosoc_regions/imem_0/ram/verilog/nanosoc_region_imem_0.v
new file mode 100644
index 0000000000000000000000000000000000000000..fc45b844a4c97c76df96528f52e369a1e78e56b3
--- /dev/null
+++ b/system/nanosoc_regions/imem_0/ram/verilog/nanosoc_region_imem_0.v
@@ -0,0 +1,62 @@
+//-----------------------------------------------------------------------------
+// Nanosoc CPU Instruction Memory Region (IMEM) - SRAM
+// - Region Mapped to: 0x20000000-0x2fffffff
+// - Memory Exhibits Wrapping Behaviour
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module nanosoc_region_imem_0 #(
+ parameter SYS_ADDR_W = 32, // System Address Width
+ parameter SYS_DATA_W = 32, // System Data Width
+ parameter IMEM_RAM_ADDR_W = 14, // Width of IMEM RAM Address - Default 16KB
+ parameter IMEM_RAM_DATA_W = 32, // Width of IMEM RAM Data Bus - Default 32 bits
+ parameter IMEM_RAM_FPGA_IMG = "image.hex" // Image to Preload into SRAM
+)(
+ input wire HCLK,
+ input wire HRESETn,
+
+ // AHB connection to Initiator
+ input wire HSEL,
+ input wire [SYS_ADDR_W-1:0] HADDR,
+ input wire [1:0] HTRANS,
+ input wire [2:0] HSIZE,
+ input wire [3:0] HPROT,
+ input wire HWRITE,
+ input wire HREADY,
+ input wire [SYS_DATA_W-1:0] HWDATA,
+
+ output wire HREADYOUT,
+ output wire HRESP,
+ output wire [SYS_DATA_W-1:0] HRDATA
+);
+
+ // SRAM Instantiation
+ sl_ahb_sram #(
+ .SYS_DATA_W (SYS_DATA_W),
+ .RAM_ADDR_W (IMEM_RAM_ADDR_W),
+ .RAM_DATA_W (IMEM_RAM_DATA_W),
+ ) u_imem_0 (
+ // AHB Inputs
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ .HSEL (HSEL),
+ .HADDR (HADDR [IMEM_RAM_ADDR_W-1:0]),
+ .HTRANS (HTRANS),
+ .HSIZE (HSIZE),
+ .HWRITE (HWRITE),
+ .HWDATA (HWDATA),
+ .HREADY (HREADY),
+
+ // AHB Outputs
+ .HREADYOUT (HREADYOUT),
+ .HRDATA (HRDATA),
+ .HRESP (HRESP)
+ );
+
+endmodule
\ No newline at end of file
diff --git a/system/nanosoc_regions/imem_0/rom/verilog/nanosoc_region_imem_0.v b/system/nanosoc_regions/imem_0/rom/verilog/nanosoc_region_imem_0.v
new file mode 100644
index 0000000000000000000000000000000000000000..70e74e8f654ccee94ec6ef5ecf9aa417196f84d0
--- /dev/null
+++ b/system/nanosoc_regions/imem_0/rom/verilog/nanosoc_region_imem_0.v
@@ -0,0 +1,63 @@
+//-----------------------------------------------------------------------------
+// Nanosoc CPU Instruction Memory Region (IMEM) - ROM
+// - Region Mapped to: 0x20000000-0x2fffffff
+// - Memory Exhibits Wrapping Behaviour
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module nanosoc_region_imem_0 #(
+ parameter SYS_ADDR_W = 32, // System Address Width
+ parameter SYS_DATA_W = 32, // System Data Width
+ parameter IMEM_RAM_ADDR_W = 14, // Width of IMEM RAM Address - Default 16KB
+ parameter IMEM_RAM_DATA_W = 32, // Width of IMEM RAM Data Bus - Default 32 bits
+ parameter IMEM_RAM_FPGA_IMG = "image.hex" // Image to Preload into SRAM
+)(
+ input wire HCLK,
+ input wire HRESETn,
+
+ // AHB connection to Initiator
+ input wire HSEL,
+ input wire [SYS_ADDR_W-1:0] HADDR,
+ input wire [1:0] HTRANS,
+ input wire [2:0] HSIZE,
+ input wire [3:0] HPROT,
+ input wire HWRITE,
+ input wire HREADY,
+ input wire [SYS_DATA_W-1:0] HWDATA,
+
+ output wire HREADYOUT,
+ output wire HRESP,
+ output wire [SYS_DATA_W-1:0] HRDATA
+);
+
+ // ROM Instantiation
+ sl_ahb_rom #(
+ .SYS_DATA_W (SYS_DATA_W),
+ .RAM_ADDR_W (IMEM_RAM_ADDR_W),
+ .RAM_DATA_W (IMEM_RAM_DATA_W),
+ .FILENAME (IMEM_RAM_FPGA_IMG)
+ ) u_imem_0 (
+ // AHB Inputs
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ .HSEL (HSEL),
+ .HADDR (HADDR [IMEM_RAM_ADDR_W-1:0]),
+ .HTRANS (HTRANS),
+ .HSIZE (HSIZE),
+ .HWRITE (HWRITE),
+ .HWDATA (HWDATA),
+ .HREADY (HREADY),
+
+ // AHB Outputs
+ .HREADYOUT (HREADYOUT),
+ .HRDATA (HRDATA),
+ .HRESP (HRESP)
+ );
+
+endmodule
\ No newline at end of file
diff --git a/system/nanosoc_regions/imem_0/verilog/nanosoc_region_imem_0.v b/system/nanosoc_regions/imem_0/verilog/nanosoc_region_imem_0.v
deleted file mode 100644
index fced8f0f4f88d0550551f4917bce6576633a58cf..0000000000000000000000000000000000000000
--- a/system/nanosoc_regions/imem_0/verilog/nanosoc_region_imem_0.v
+++ /dev/null
@@ -1,64 +0,0 @@
-//-----------------------------------------------------------------------------
-// Nanosoc CPU Instruction Memory Region (IMEM)
-// - Region Mapped to: 0x20000000-0x2fffffff
-// - Memory Exhibits Wrapping Behaviour
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-
-module nanosoc_region_imem_0 #(
- parameter SYS_ADDR_W = 32, // System Address Width
- parameter SYS_DATA_W = 32, // System Data Width
- parameter IMEM_RAM_ADDR_W = 14, // Width of IMEM RAM Address - Default 16KB
- parameter IMEM_RAM_DATA_W = 32, // Width of IMEM RAM Data Bus - Default 32 bits
- parameter IMEM_RAM_FPGA_IMG = "image.hex" // Image to Preload into SRAM
- )(
- input wire HCLK,
- input wire HRESETn,
-
- // AHB connection to Initiator
- input wire HSEL,
- input wire [SYS_ADDR_W-1:0] HADDR,
- input wire [1:0] HTRANS,
- input wire [2:0] HSIZE,
- input wire [3:0] HPROT,
- input wire HWRITE,
- input wire HREADY,
- input wire [SYS_DATA_W-1:0] HWDATA,
-
- output wire HREADYOUT,
- output wire HRESP,
- output wire [SYS_DATA_W-1:0] HRDATA
- );
-
- // SRAM Instantiation
- // sl_ahb_sram #(
- sl_ahb_rom #(
- .SYS_DATA_W (SYS_DATA_W),
- .RAM_ADDR_W (IMEM_RAM_ADDR_W),
- .RAM_DATA_W (IMEM_RAM_DATA_W),
- .FILENAME (IMEM_RAM_FPGA_IMG)
- ) u_imem_0 (
- // AHB Inputs
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HSEL (HSEL),
- .HADDR (HADDR [IMEM_RAM_ADDR_W-1:0]),
- .HTRANS (HTRANS),
- .HSIZE (HSIZE),
- .HWRITE (HWRITE),
- .HWDATA (HWDATA),
- .HREADY (HREADY),
-
- // AHB Outputs
- .HREADYOUT (HREADYOUT),
- .HRDATA (HRDATA),
- .HRESP (HRESP)
- );
-
-endmodule
\ No newline at end of file
diff --git a/system/nanosoc_system/verilog/nanosoc_system.v b/system/nanosoc_system/verilog/nanosoc_system.v
index 253ced92f01cfb6c968bc5a77371fd1624d43d41..c5fe7fbb09e3d276fe8d6f4ecc0d61d9fa820add 100644
--- a/system/nanosoc_system/verilog/nanosoc_system.v
+++ b/system/nanosoc_system/verilog/nanosoc_system.v
@@ -257,7 +257,7 @@ module nanosoc_system #(
.IMEM_RAM_FPGA_IMG (IMEM_RAM_FPGA_IMG),
.DMEM_RAM_ADDR_W (DMEM_RAM_ADDR_W),
.DMEM_RAM_DATA_W (DMEM_RAM_DATA_W)
- ) u_cpu_ss (
+ ) u_ss_cpu (
// System Input Clocks and Resets
.SYS_FCLK(SYS_FCLK),
.SYS_SYSRESETn(SYS_SYSRESETn),
@@ -448,7 +448,7 @@ module nanosoc_system #(
.DMAC_1_CFG_ADDR_W(DMAC_1_CFG_ADDR_W),
.DMAC_0_CHANNEL_NUM(DMAC_0_CHANNEL_NUM),
.DMAC_1_CHANNEL_NUM(DMAC_1_CHANNEL_NUM)
- ) u_dma_ss (
+ ) u_ss_dma (
// System AHB Clocks and Resets
.SYS_HCLK(SYS_HCLK),
.SYS_HRESETn(SYS_HRESETn),
@@ -561,7 +561,7 @@ module nanosoc_system #(
.FT1248_WIDTH(FT1248_WIDTH),
.FT1248_CLKON(FT1248_CLKON),
.FT1248_CLKDIV(FT1248_CLKDIV)
- ) u_debug_ss (
+ ) u_ss_debug (
// System Clocks and Resets
.SYS_HCLK(SYS_HCLK),
.SYS_HRESETn(SYS_HRESETn),
@@ -686,7 +686,7 @@ module nanosoc_system #(
// SRAM High Parameters
.EXPRAM_H_RAM_ADDR_W(EXPRAM_H_RAM_ADDR_W),
.EXPRAM_H_RAM_DATA_W(EXPRAM_H_RAM_DATA_W)
- ) u_expansion_ss (
+ ) u_ss_expansion (
// System Clocks and Resets
.SYS_HCLK(SYS_HCLK),
.SYS_HRESETn(SYS_HRESETn),
@@ -818,7 +818,7 @@ module nanosoc_system #(
.NANOSOC_PARTNUMBER(NANOSOC_PARTNUMBER),
.NANOSOC_REVISION(NANOSOC_REVISION),
.CLKGATE_PRESENT(CLKGATE_PRESENT)
- ) u_systemctrl_ss (
+ ) u_ss_systemctrl (
// Free-running and Crystal Clock Output
.SYS_CLK (SYS_CLK), // System Input Clock
.SYS_FCLK(SYS_FCLK), // Free-running system clock
@@ -947,7 +947,7 @@ module nanosoc_system #(
nanosoc_ss_interconnect #(
.SYS_ADDR_W (SYS_ADDR_W), // System Address Width
.SYS_DATA_W (SYS_DATA_W) // System Data Width
- ) u_interconnect_ss (
+ ) u_ss_interconnect (
// System Clocks, Resets, and Control
.SYS_HCLK(SYS_HCLK),
.SYS_HRESETn(SYS_HRESETn),
diff --git a/verif/verilog/nanosoc_clkreset.v b/verif/control/verilog/nanosoc_clkreset.v
similarity index 100%
rename from verif/verilog/nanosoc_clkreset.v
rename to verif/control/verilog/nanosoc_clkreset.v
diff --git a/verif/verilog/nanosoc_tb.v b/verif/tb/verilog/nanosoc_tb.v
similarity index 95%
rename from verif/verilog/nanosoc_tb.v
rename to verif/tb/verilog/nanosoc_tb.v
index 80022c0770e1ae7745a2bd27e9a281836759e161..352a378ea75e220d6bc52a8c2bcbc846375e5fc0 100644
--- a/verif/verilog/nanosoc_tb.v
+++ b/verif/tb/verilog/nanosoc_tb.v
@@ -389,7 +389,7 @@ nanosoc_ft1248x1_track
`ifdef CORTEX_M0
`ifdef USE_TARMAC
-`define ARM_CM0IK_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_system.u_cpu_ss.u_cpu_0.u_slcorem0_integration.u_cortexm0
+`define ARM_CM0IK_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_system.u_ss_cpu.u_cpu_0.u_slcorem0_integration.u_cortexm0
CORTEXM0
#(.ACG(1), .AHBSLV(0), .BE(0), .BKPT(4),
@@ -523,7 +523,7 @@ nanosoc_ft1248x1_track
// - log the RTL Inuts/outputs/internal-state of this traccking DMAC
// --------------------------------------------------------------------------------
-`define DMAC_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_system.u_dma_ss.u_dmac_0.u_pl230_udma
+`define DMAC_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_system.u_ss_dma.u_dmac_0.u_pl230_udma
pl230_udma u_track_pl230_udma (
// Clock and Reset
@@ -597,29 +597,31 @@ nanosoc_ft1248x1_track
// Tracking Accelerator logging support
// --------------------------------------------------------------------------------
-// `define ACC_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_nanosoc_exp_wrapper
-
-// nanosoc_acc_log_to_file #(.FILENAME("logs/acc_exp.log"),.TIMESTAMP(1))
-// u_nanosoc_acc_log_to_file (
-// .HCLK (`ACC_PATH.HCLK ),
-// .HRESETn (`ACC_PATH.HRESETn ),
-// .HSEL_i (`ACC_PATH.HSEL_i ),
-// .HADDR_i (`ACC_PATH.HADDR_i ),
-// .HTRANS_i (`ACC_PATH.HTRANS_i ),
-// .HWRITE_i (`ACC_PATH.HWRITE_i ),
-// .HSIZE_i (`ACC_PATH.HSIZE_i ),
-// .HPROT_i (`ACC_PATH.HPROT_i ),
-// .HWDATA_i (`ACC_PATH.HWDATA_i ),
-// .HREADY_i (`ACC_PATH.HREADY_i ),
-// .HRDATA_o (`ACC_PATH.HRDATA_o ),
-// .HREADYOUT_o (`ACC_PATH.HREADYOUT_o ),
-// .HRESP_o (`ACC_PATH.HRESP_o ),
-// .exp_drq_ip_o (`ACC_PATH.exp_drq_ip_o ),
-// .exp_dlast_ip_i (`ACC_PATH.exp_dlast_ip_i),
-// .exp_drq_op_o (`ACC_PATH.exp_drq_op_o ),
-// .exp_dlast_op_i (`ACC_PATH.exp_dlast_op_i),
-// .exp_irq_o (`ACC_PATH.exp_irq_o )
-// );
+ `define ACC_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_system.u_ss_expansion.u_region_exp
+
+ nanosoc_accelerator_ss_logger #(
+ .FILENAME("logs/acc_exp.log"),
+ .TIMESTAMP(1)
+ ) u_accelerator_ss_logger (
+ .HCLK (`ACC_PATH.HCLK ),
+ .HRESETn (`ACC_PATH.HRESETn ),
+ .HSEL_i (`ACC_PATH.HSEL ),
+ .HADDR_i (`ACC_PATH.HADDR ),
+ .HTRANS_i (`ACC_PATH.HTRANS ),
+ .HWRITE_i (`ACC_PATH.HWRITE ),
+ .HSIZE_i (`ACC_PATH.HSIZE ),
+ .HPROT_i (`ACC_PATH.HPROT ),
+ .HWDATA_i (`ACC_PATH.HWDATA ),
+ .HREADY_i (`ACC_PATH.HREADY ),
+ .HRDATA_o (`ACC_PATH.HRDATA ),
+ .HREADYOUT_o (`ACC_PATH.HREADYOUT ),
+ .HRESP_o (`ACC_PATH.HRESP ),
+ .exp_drq_ip_o (`ACC_PATH.EXP_DRQ[0] ),
+ .exp_dlast_ip_i (`ACC_PATH.EXP_DLAST[0] ),
+ .exp_drq_op_o (`ACC_PATH.EXP_DRQ[1] ),
+ .exp_dlast_op_i (`ACC_PATH.EXP_DLAST[1] ),
+ .exp_irq_o (`ACC_PATH.EXP_IRQ )
+ );
// --------------------------------------------------------------------------------
diff --git a/verif/verilog/nanosoc_tb_qs.v b/verif/tb/verilog/nanosoc_tb_qs.v
similarity index 83%
rename from verif/verilog/nanosoc_tb_qs.v
rename to verif/tb/verilog/nanosoc_tb_qs.v
index d8fa516d8b18ecffb59a8daa6d2658f62e910023..fc3bd4b19b587bba39a41cc91092285a49acd47d 100644
--- a/verif/verilog/nanosoc_tb_qs.v
+++ b/verif/tb/verilog/nanosoc_tb_qs.v
@@ -1,5 +1,5 @@
//-----------------------------------------------------------------------------
-// NanoSoC Testbench adpated from example Cortex-M0 controller testbench
+// NanoSoC Testbench adpated from example Cortex-M0 controller testbench - QUICKSTART
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
@@ -389,7 +389,7 @@ nanosoc_ft1248x1_track
`ifdef CORTEX_M0
`ifdef USE_TARMAC
-`define ARM_CM0IK_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_system.u_cpu_ss.u_cpu_0.u_slcorem0_integration.u_cortexm0
+`define ARM_CM0IK_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_system.u_ss_cpu.u_cpu_0.u_slcorem0_integration.u_cortexm0
CORTEXM0
#(.ACG(1), .AHBSLV(0), .BE(0), .BKPT(4),
@@ -517,109 +517,36 @@ nanosoc_ft1248x1_track
`endif // USE_TARMAC
`endif // CORTEX_M0
- // --------------------------------------------------------------------------------
- // Tracking DMA logging support
- // - Track inputs to on-chip PL230 DMAC and replicate state and outputs in testbench
- // - log the RTL Inuts/outputs/internal-state of this traccking DMAC
- // --------------------------------------------------------------------------------
-
-// `define DMAC_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_system.u_dma_ss.u_dmac_0.u_pl230_udma
-
-// pl230_udma u_track_pl230_udma (
-// // Clock and Reset
-// .hclk (`DMAC_PATH.hclk),
-// .hresetn (`DMAC_PATH.hresetn),
-// // DMA Control
-// .dma_req (`DMAC_PATH.dma_req),
-// .dma_sreq (`DMAC_PATH.dma_sreq),
-// .dma_waitonreq (`DMAC_PATH.dma_waitonreq),
-// .dma_stall (`DMAC_PATH.dma_stall),
-// .dma_active ( ),
-// .dma_done ( ),
-// .dma_err ( ),
-// // AHB-Lite Master Interface
-// .hready (`DMAC_PATH.hready),
-// .hresp (`DMAC_PATH.hresp),
-// .hrdata (`DMAC_PATH.hrdata),
-// .htrans ( ),
-// .hwrite ( ),
-// .haddr ( ),
-// .hsize ( ),
-// .hburst ( ),
-// .hmastlock ( ),
-// .hprot ( ),
-// .hwdata ( ),
-// // APB Slave Interface
-// .pclken (`DMAC_PATH.pclken),
-// .psel (`DMAC_PATH.psel),
-// .pen (`DMAC_PATH.pen),
-// .pwrite (`DMAC_PATH.pwrite),
-// .paddr (`DMAC_PATH.paddr),
-// .pwdata (`DMAC_PATH.pwdata),
-// .prdata ( )
-// );
-
-// `define DMAC_TRACK_PATH u_track_pl230_udma
-
-// nanosoc_dma_log_to_file #(.FILENAME("logs/dma230.log"),.NUM_CHNLS(2),.NUM_CHNL_BITS(1),.TIMESTAMP(1))
-// u_nanosoc_dma_log_to_file (
-// .hclk (`DMAC_TRACK_PATH.hclk),
-// .hresetn (`DMAC_TRACK_PATH.hresetn),
-// // AHB-Lite Master Interface
-// .hready (`DMAC_TRACK_PATH.hready),
-// .hresp (`DMAC_TRACK_PATH.hresp),
-// .hrdata (`DMAC_TRACK_PATH.hrdata),
-// .htrans (`DMAC_TRACK_PATH.htrans),
-// .hwrite (`DMAC_TRACK_PATH.hwrite),
-// .haddr (`DMAC_TRACK_PATH.haddr),
-// .hsize (`DMAC_TRACK_PATH.hsize),
-// .hburst (`DMAC_TRACK_PATH.hburst),
-// .hprot (`DMAC_TRACK_PATH.hprot),
-// .hwdata (`DMAC_TRACK_PATH.hwdata),
-// // APB control interface
-// .pclken (`DMAC_TRACK_PATH.pclken),
-// .psel (`DMAC_TRACK_PATH.psel),
-// .pen (`DMAC_TRACK_PATH.pen),
-// .pwrite (`DMAC_TRACK_PATH.pwrite),
-// .paddr (`DMAC_TRACK_PATH.paddr),
-// .pwdata (`DMAC_TRACK_PATH.pwdata),
-// .prdata (`DMAC_TRACK_PATH.prdata),
-// // DMA Control
-// .dma_req (`DMAC_TRACK_PATH.dma_req),
-// .dma_active (`DMAC_TRACK_PATH.dma_active),
-// .dma_done (`DMAC_TRACK_PATH.dma_done),
-// // DMA state from tracking RTL model
-// .dma_chnl (`DMAC_TRACK_PATH.u_pl230_ahb_ctrl.current_chnl),
-// .dma_ctrl_state(`DMAC_TRACK_PATH.u_pl230_ahb_ctrl.ctrl_state)
-// );
// --------------------------------------------------------------------------------
// Tracking Accelerator logging support
// --------------------------------------------------------------------------------
-// `define ACC_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_nanosoc_exp_wrapper
-
-// nanosoc_acc_log_to_file #(.FILENAME("logs/acc_exp.log"),.TIMESTAMP(1))
-// u_nanosoc_acc_log_to_file (
-// .HCLK (`ACC_PATH.HCLK ),
-// .HRESETn (`ACC_PATH.HRESETn ),
-// .HSEL_i (`ACC_PATH.HSEL_i ),
-// .HADDR_i (`ACC_PATH.HADDR_i ),
-// .HTRANS_i (`ACC_PATH.HTRANS_i ),
-// .HWRITE_i (`ACC_PATH.HWRITE_i ),
-// .HSIZE_i (`ACC_PATH.HSIZE_i ),
-// .HPROT_i (`ACC_PATH.HPROT_i ),
-// .HWDATA_i (`ACC_PATH.HWDATA_i ),
-// .HREADY_i (`ACC_PATH.HREADY_i ),
-// .HRDATA_o (`ACC_PATH.HRDATA_o ),
-// .HREADYOUT_o (`ACC_PATH.HREADYOUT_o ),
-// .HRESP_o (`ACC_PATH.HRESP_o ),
-// .exp_drq_ip_o (`ACC_PATH.exp_drq_ip_o ),
-// .exp_dlast_ip_i (`ACC_PATH.exp_dlast_ip_i),
-// .exp_drq_op_o (`ACC_PATH.exp_drq_op_o ),
-// .exp_dlast_op_i (`ACC_PATH.exp_dlast_op_i),
-// .exp_irq_o (`ACC_PATH.exp_irq_o )
-// );
+ `define ACC_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_system.u_ss_expansion.u_region_exp
+
+ nanosoc_accelerator_ss_logger #(
+ .FILENAME("logs/acc_exp.log"),
+ .TIMESTAMP(1)
+ ) u_accelerator_ss_logger (
+ .HCLK (`ACC_PATH.HCLK ),
+ .HRESETn (`ACC_PATH.HRESETn ),
+ .HSEL_i (`ACC_PATH.HSEL ),
+ .HADDR_i (`ACC_PATH.HADDR ),
+ .HTRANS_i (`ACC_PATH.HTRANS ),
+ .HWRITE_i (`ACC_PATH.HWRITE ),
+ .HSIZE_i (`ACC_PATH.HSIZE ),
+ .HPROT_i (`ACC_PATH.HPROT ),
+ .HWDATA_i (`ACC_PATH.HWDATA ),
+ .HREADY_i (`ACC_PATH.HREADY ),
+ .HRDATA_o (`ACC_PATH.HRDATA ),
+ .HREADYOUT_o (`ACC_PATH.HREADYOUT ),
+ .HRESP_o (`ACC_PATH.HRESP ),
+ .exp_drq_ip_o (`ACC_PATH.EXP_DRQ[0] ),
+ .exp_dlast_ip_i (`ACC_PATH.EXP_DLAST[0] ),
+ .exp_drq_op_o (`ACC_PATH.EXP_DRQ[1] ),
+ .exp_dlast_op_i (`ACC_PATH.EXP_DLAST[1] ),
+ .exp_irq_o (`ACC_PATH.EXP_IRQ )
+ );
// --------------------------------------------------------------------------------
diff --git a/verif/verilog/nanosoc_acc_log_to_file.v b/verif/trace/verilog/nanosoc_accelerator_ss_logger.v
similarity index 66%
rename from verif/verilog/nanosoc_acc_log_to_file.v
rename to verif/trace/verilog/nanosoc_accelerator_ss_logger.v
index 8a03a47a5d59124247ad257c4fc7d16d91fa73d0..6c8bce957c22ffc314c9f14d9b8ece00426c0a69 100644
--- a/verif/verilog/nanosoc_acc_log_to_file.v
+++ b/verif/trace/verilog/nanosoc_accelerator_ss_logger.v
@@ -1,5 +1,5 @@
//-----------------------------------------------------------------------------
-// AHB transaction logger, developed for DMA integration testing
+// NanoSoC Accelerator Subsystem AHB Transaction Logger
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
@@ -9,32 +9,33 @@
// Copyright (C) 2023, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
-module nanosoc_acc_log_to_file
- #(parameter FILENAME = "accelerator.log",
- parameter AHBADDRWIDTH = 29,
- parameter CFGNUMIRQ = 1,
- parameter TIMESTAMP = 1)
- (
- input wire HCLK, // Clock
- input wire HRESETn, // Reset
- input wire HSEL_i, // Device select
- input wire [AHBADDRWIDTH-1:0] HADDR_i, // Address for byte select
- input wire [1:0] HTRANS_i, // Transfer control
- input wire [2:0] HSIZE_i, // Transfer size
- input wire [3:0] HPROT_i, // Protection control
- input wire HWRITE_i, // Write control
- input wire HREADY_i, // Transfer phase done
- input wire [31:0] HWDATA_i, // Write data
- input wire HREADYOUT_o, // Device ready
- input wire [31:0] HRDATA_o, // Read data output
- input wire HRESP_o, // Device response
-// stream data
- input wire exp_drq_ip_o, // (to) DMAC input burst request
- input wire exp_dlast_ip_i,// (from) DMAC input burst end (last transfer)
- input wire exp_drq_op_o, // (to) DMAC output dma burst request
- input wire exp_dlast_op_i,// (from) DMAC output burst end (last transfer)
- input wire [CFGNUMIRQ-1:0] exp_irq_o
- );
+module nanosoc_accelerator_ss_logger #(
+ parameter FILENAME = "accelerator.log",
+ parameter SYS_ADDR_W = 32,
+ parameter SYS_DATA_W = 32,
+ parameter IRQ_NUM = 4,
+ parameter TIMESTAMP = 1
+)(
+ input wire HCLK, // Clock
+ input wire HRESETn, // Reset
+ input wire HSEL_i, // Device select
+ input wire [SYS_ADDR_W-1:0] HADDR_i, // Address for byte select
+ input wire [1:0] HTRANS_i, // Transfer control
+ input wire [2:0] HSIZE_i, // Transfer size
+ input wire [3:0] HPROT_i, // Protection control
+ input wire HWRITE_i, // Write control
+ input wire HREADY_i, // Transfer phase done
+ input wire [SYS_DATA_W-1:0] HWDATA_i, // Write data
+ input wire HREADYOUT_o, // Device ready
+ input wire [SYS_DATA_W-1:0] HRDATA_o, // Read data output
+ input wire HRESP_o, // Device response
+ // AXI-Stream Data
+ input wire exp_drq_ip_o, // (to) DMAC input burst request
+ input wire exp_dlast_ip_i, // (from) DMAC input burst end (last transfer)
+ input wire exp_drq_op_o, // (to) DMAC output dma burst request
+ input wire exp_dlast_op_i, // (from) DMAC output burst end (last transfer)
+ input wire [IRQ_NUM-1:0] exp_irq_o
+);
// AHB transction de-pipelining
@@ -43,12 +44,12 @@ module nanosoc_acc_log_to_file
// Internal regs/wires
// --------------------------------------------------------------------------
- reg sel_r;
- reg [AHBADDRWIDTH-1:0] addr_r;
- reg wcyc_r;
- reg rcyc_r;
- reg [3:0] byte4_r;
- reg [3:0] dma_ctrl_state_r;
+ reg sel_r;
+ reg [SYS_ADDR_W-1:0] addr_r;
+ reg wcyc_r;
+ reg rcyc_r;
+ reg [3:0] byte4_r;
+ reg [3:0] dma_ctrl_state_r;
// --------------------------------------------------------------------------
// AHB slave byte buffer interface, support for unaligned data transfers
@@ -80,31 +81,32 @@ module nanosoc_acc_log_to_file
byte4_r <= (HSEL_i & HTRANS_i[1]) ? byte_nxt[3:0] : 4'b0000;
end
- wire [31:0] hdata = (wcyc_r)? HWDATA_i : HRDATA_o;
+ wire [SYS_DATA_W-1:0] hdata;
+ assign hdata = (wcyc_r)? HWDATA_i : HRDATA_o;
//----------------------------------------------
//-- File I/O
//----------------------------------------------
- integer fd; // channel descriptor for cmd file input
- integer ch;
-
- reg exp_drq_ip_o_prev;
- reg exp_dlast_ip_i_prev;
- reg exp_drq_op_o_prev;
- reg exp_dlast_op_i_prev;
- reg [CFGNUMIRQ-1:0] exp_irq_prev;
-
- wire exp_drq_ip_change;
- wire exp_dlast_ip_change;
- wire exp_drq_op_change;
- wire exp_dlast_op_change;
- wire [CFGNUMIRQ-1:0] exp_irq_change;
- wire irq_change;
- wire drq_change;
- wire any_change;
+ integer fd; // channel descriptor for cmd file input
+ integer ch;
+
+ reg exp_drq_ip_o_prev;
+ reg exp_dlast_ip_i_prev;
+ reg exp_drq_op_o_prev;
+ reg exp_dlast_op_i_prev;
+ reg [IRQ_NUM-1:0] exp_irq_prev;
+
+ wire exp_drq_ip_change;
+ wire exp_dlast_ip_change;
+ wire exp_drq_op_change;
+ wire exp_dlast_op_change;
+ wire [IRQ_NUM-1:0] exp_irq_change;
+ wire irq_change;
+ wire drq_change;
+ wire any_change;
- reg [31:0] cyc_count;
+ reg [31:0] cyc_count;
`define EOF -1
reg [7:0] ctrl_reg;
@@ -118,7 +120,7 @@ module nanosoc_acc_log_to_file
exp_dlast_ip_i_prev <= 1'b0;
exp_drq_op_o_prev <= 1'b0;
exp_dlast_op_i_prev <= 1'b0;
- exp_irq_prev <= {CFGNUMIRQ{1'b0}};
+ exp_irq_prev <= {IRQ_NUM{1'b0}};
end else if (HREADY_i)
begin
diff --git a/verif/verilog/nanosoc_axi_stream_io_8_buffer.v b/verif/trace/verilog/nanosoc_axi_stream_io_8_buffer.v
similarity index 100%
rename from verif/verilog/nanosoc_axi_stream_io_8_buffer.v
rename to verif/trace/verilog/nanosoc_axi_stream_io_8_buffer.v
diff --git a/verif/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v b/verif/trace/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
similarity index 100%
rename from verif/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
rename to verif/trace/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
diff --git a/verif/verilog/nanosoc_axi_stream_io_8_txd_from_file.v b/verif/trace/verilog/nanosoc_axi_stream_io_8_txd_from_file.v
similarity index 100%
rename from verif/verilog/nanosoc_axi_stream_io_8_txd_from_file.v
rename to verif/trace/verilog/nanosoc_axi_stream_io_8_txd_from_file.v
diff --git a/verif/verilog/nanosoc_dma_log_to_file.v b/verif/trace/verilog/nanosoc_dma_log_to_file.v
similarity index 100%
rename from verif/verilog/nanosoc_dma_log_to_file.v
rename to verif/trace/verilog/nanosoc_dma_log_to_file.v
diff --git a/verif/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v b/verif/trace/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v
similarity index 100%
rename from verif/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v
rename to verif/trace/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v
diff --git a/verif/verilog/nanosoc_ft1248x1_track.v b/verif/trace/verilog/nanosoc_ft1248x1_track.v
similarity index 100%
rename from verif/verilog/nanosoc_ft1248x1_track.v
rename to verif/trace/verilog/nanosoc_ft1248x1_track.v
diff --git a/verif/verilog/nanosoc_track_tb_iostream.v b/verif/trace/verilog/nanosoc_track_tb_iostream.v
similarity index 100%
rename from verif/verilog/nanosoc_track_tb_iostream.v
rename to verif/trace/verilog/nanosoc_track_tb_iostream.v
diff --git a/verif/verilog/nanosoc_uart_capture.v b/verif/trace/verilog/nanosoc_uart_capture.v
similarity index 100%
rename from verif/verilog/nanosoc_uart_capture.v
rename to verif/trace/verilog/nanosoc_uart_capture.v