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Commit 7b575353 authored by dam1n19's avatar dam1n19
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SOC1-230: Wired Expansion Subsystem

parent 493f3f49
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1 merge request!1changed imem to rom to allow initial program loading, updated bootloader code...
......@@ -15,62 +15,152 @@ module nanosoc_ss_expansion #(
parameter SYS_DATA_W = 32, // System Data Width
// SRAM Low Parameters
parameter SRAM_L_RAM_ADDR_W = 14, // Width of IMEM RAM Address - Default 16KB
parameter SRAM_L_RAM_DATA_W = 32, // Width of IMEM RAM Data Bus - Default 32 bits
parameter EXPRAM_L_RAM_ADDR_W = 14, // Width of IMEM RAM Address - Default 16KB
parameter EXPRAM_L_RAM_DATA_W = 32, // Width of IMEM RAM Data Bus - Default 32 bits
// SRAM High Parameters
parameter SRAM_H_RAM_ADDR_W = 14, // Width of IMEM RAM Address - Default 16KB
parameter SRAM_H_RAM_DATA_W = 32 // Width of IMEM RAM Data Bus - Default 32 bits
parameter EXPRAM_H_RAM_ADDR_W = 14, // Width of IMEM RAM Address - Default 16KB
parameter EXPRAM_H_RAM_DATA_W = 32 // Width of IMEM RAM Data Bus - Default 32 bits
)(
// System Clocks and Resets
input wire SYS_HCLK,
input wire SYS_HRESETn,
// Expansion Region AHB Port
input wire EXP_HSELS,
input wire [SYS_ADDR_W-1:0] EXP_HADDRS,
input wire [1:0] EXP_HTRANSS,
input wire [2:0] EXP_HSIZES,
input wire [3:0] EXP_HPROTS,
input wire EXP_HWRITES,
input wire EXP_HREADYS,
input wire [31:0] EXP_HWDATAS,
output wire EXP_HREADYOUTS,
output wire EXP_HRESPS,
output wire [31:0] EXP_HRDATAS,
input wire EXP_HSEL,
input wire [SYS_ADDR_W-1:0] EXP_HADDR,
input wire [1:0] EXP_HTRANS,
input wire [2:0] EXP_HSIZE,
input wire [3:0] EXP_HPROT,
input wire EXP_HWRITE,
input wire EXP_HREADY,
input wire [31:0] EXP_HWDATA,
output wire EXP_HREADYOUT,
output wire EXP_HRESP,
output wire [31:0] EXP_HRDATA,
// SRAM Low Region AHB Port
input wire EXPSRAM_L_HSELS,
input wire [SYS_ADDR_W-1:0] EXPSRAM_L_HADDRS,
input wire [1:0] EXPSRAM_L_HTRANSS,
input wire [2:0] EXPSRAM_L_HSIZES,
input wire [3:0] EXPSRAM_L_HPROTS,
input wire EXPSRAM_L_HWRITES,
input wire EXPSRAM_L_HREADYS,
input wire [31:0] EXPSRAM_L_HWDATAS,
output wire EXPSRAM_L_HREADYOUTS,
output wire EXPSRAM_L_HRESPS,
output wire [31:0] EXPSRAM_L_HRDATAS,
input wire EXPSRAM_L_HSEL,
input wire [SYS_ADDR_W-1:0] EXPSRAM_L_HADDR,
input wire [1:0] EXPSRAM_L_HTRANS,
input wire [2:0] EXPSRAM_L_HSIZE,
input wire [3:0] EXPSRAM_L_HPROT,
input wire EXPSRAM_L_HWRITE,
input wire EXPSRAM_L_HREADY,
input wire [31:0] EXPSRAM_L_HWDATA,
output wire EXPSRAM_L_HREADYOUT,
output wire EXPSRAM_L_HRESP,
output wire [31:0] EXPSRAM_L_HRDATA,
// SRAM High Region AHB Port
input wire EXPSRAM_H_HSELS,
input wire [SYS_ADDR_W-1:0] EXPSRAM_H_HADDRS,
input wire [1:0] EXPSRAM_H_HTRANSS,
input wire [2:0] EXPSRAM_H_HSIZES,
input wire [3:0] EXPSRAM_H_HPROTS,
input wire EXPSRAM_H_HWRITES,
input wire EXPSRAM_H_HREADYS,
input wire [31:0] EXPSRAM_H_HWDATAS,
output wire EXPSRAM_H_HREADYOUTS,
output wire EXPSRAM_H_HRESPS,
output wire [31:0] EXPSRAM_H_HRDATAS
// Interrupt Interfaces
// DMA Request Interfaces
input wire EXPSRAM_H_HSEL,
input wire [SYS_ADDR_W-1:0] EXPSRAM_H_HADDR,
input wire [1:0] EXPSRAM_H_HTRANS,
input wire [2:0] EXPSRAM_H_HSIZE,
input wire [3:0] EXPSRAM_H_HPROT,
input wire EXPSRAM_H_HWRITE,
input wire EXPSRAM_H_HREADY,
input wire [31:0] EXPSRAM_H_HWDATA,
output wire EXPSRAM_H_HREADYOUT,
output wire EXPSRAM_H_HRESP,
output wire [31:0] EXPSRAM_H_HRDATA,
// Interrupt and DMAC Connections
output wire [3:0] EXP_IRQ,
output wire [1:0] EXP_DRQ,
input wire [1:0] EXP_DLAST
);
// -------------------------------
// Expansion Region Instantiation
// -------------------------------
nanosoc_region_exp #(
.SYS_ADDR_W(SYS_ADDR_W),
.SYS_DATA_W(SYS_DATA_W)
) u_region_exp (
// Clock and Reset
.HCLK(HCLK),
.HRESETn(HRESETn),
// AHB Subordinate Port
.HSEL(EXP_HSEL),
.HADDR(EXP_HADDR),
.HTRANS(EXP_HTRANS),
.HSIZE(EXP_HSIZE),
.HPROT(EXP_HPROT),
.HWRITE(EXP_HWRITE),
.HREADY(EXP_HREADY),
.HWDATA(EXP_HWDATA),
// AHB Master Interface
.HREADYOUT(EXP_HREADYOUT),
.HRESP(EXP_HRESP),
.HRDATA(EXP_HRDATA),
// Interrupt and DMAC Connections
.EXP_IRQ(EXP_IRQ),
.EXP_DRQ(EXP_DRQ),
.EXP_DLAST(EXP_DLAST)
);
// ----------------------------------------
// Expansion SRAM Low Region Instantiation
// ----------------------------------------
nanosoc_region_expram_l #(
.SYS_ADDR_W (SYS_ADDR_W),
.SYS_DATA_W (SYS_DATA_W),
.EXPRAM_L_RAM_ADDR_W (EXPRAM_L_RAM_ADDR_W),
.EXPRAM_L_RAM_DATA_W (EXPRAM_L_RAM_DATA_W)
) u_region_expram_l (
// Clock and Reset
.HCLK(SYS_HCLK),
.HRESETn(SYS_HRESETn),
// AHB connection to Initiator
.HSEL(EXPRAM_L_HSEL),
.HADDR(EXPRAM_L_HADDR),
.HTRANS(EXPRAM_L_HTRANS),
.HSIZE(EXPRAM_L_HSIZE),
.HPROT(EXPRAM_L_HPROT),
.HWRITE(EXPRAM_L_HWRITE),
.HREADY(EXPRAM_L_HREADY),
.HWDATA(EXPRAM_L_HWDATA),
// AHB Master Interface
.HREADYOUT(EXPRAM_L_HREADYOUT),
.HRESP(EXPRAM_L_HRESP),
.HRDATA(EXPRAM_L_HRDATA)
);
// -----------------------------------------
// Expansion SRAM High Region Instantiation
// -----------------------------------------
nanosoc_region_expram_h #(
.SYS_ADDR_W (SYS_ADDR_W),
.SYS_DATA_W (SYS_DATA_W),
.EXPRAM_H_RAM_ADDR_W (EXPRAM_H_RAM_ADDR_W),
.EXPRAM_H_RAM_DATA_W (EXPRAM_H_RAM_DATA_W)
) u_region_expram_h (
// Clock and Reset
.HCLK(SYS_HCLK),
.HRESETn(SYS_HRESETn),
// AHB connection to Initiator
.HSEL(EXPRAM_H_HSEL),
.HADDR(EXPRAM_H_HADDR),
.HTRANS(EXPRAM_H_HTRANS),
.HSIZE(EXPRAM_H_HSIZE),
.HPROT(EXPRAM_H_HPROT),
.HWRITE(EXPRAM_H_HWRITE),
.HREADY(EXPRAM_H_HREADY),
.HWDATA(EXPRAM_H_HWDATA),
// AHB Master Interface
.HREADYOUT(EXPRAM_H_HREADYOUT),
.HRESP(EXPRAM_H_HRESP),
.HRDATA(EXPRAM_H_HRDATA)
);
endmodule
\ No newline at end of file
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