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SoCLabs
NanoSoC Tech
Commits
493f3f49
Commit
493f3f49
authored
2 years ago
by
dam1n19
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SOC1-230
: Updated expansion region
parent
c357b19d
Branches
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No related tags found
1 merge request
!1
changed imem to rom to allow initial program loading, updated bootloader code...
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system/nanosoc_regions/exp/verilog/nanosoc_region_exp.v
+55
-17
55 additions, 17 deletions
system/nanosoc_regions/exp/verilog/nanosoc_region_exp.v
system/slcore_m0_tech
+1
-1
1 addition, 1 deletion
system/slcore_m0_tech
with
56 additions
and
18 deletions
system/nanosoc_regions/exp/verilog/nanosoc_region_exp.v
+
55
−
17
View file @
493f3f49
...
...
@@ -16,23 +16,61 @@ module nanosoc_region_exp #(
input
wire
HCLK
,
// Clock
input
wire
HRESETn
,
// Reset
// AHB
connection to Initiat
or
input
wire
HSEL
S
,
input
wire
[
SYS_ADDR_W
-
1
:
0
]
HADDR
S
,
input
wire
[
1
:
0
]
HTRANS
S
,
input
wire
[
2
:
0
]
HSIZE
S
,
input
wire
[
3
:
0
]
HPROT
S
,
input
wire
HWRITE
S
,
input
wire
HREADY
S
,
input
wire
[
3
1
:
0
]
HWDATA
S
,
// AHB
Subortinate P
or
t
input
wire
HSEL
,
input
wire
[
SYS_ADDR_W
-
1
:
0
]
HADDR
,
input
wire
[
1
:
0
]
HTRANS
,
input
wire
[
2
:
0
]
HSIZE
,
input
wire
[
3
:
0
]
HPROT
,
input
wire
HWRITE
,
input
wire
HREADY
,
input
wire
[
SYS_DATA_W
-
1
:
0
]
HWDATA
,
output
wire
HREADYOUT
S
,
output
wire
HRESP
S
,
output
wire
[
3
1
:
0
]
HRDATA
S
,
output
wire
HREADYOUT
,
output
wire
HRESP
,
output
wire
[
SYS_DATA_W
-
1
:
0
]
HRDATA
,
// Interrupt Connections
output
wire
ip_data_req
,
output
wire
op_data_req
// Interrupt and DMAC Connections
output
wire
[
3
:
0
]
EXP_IRQ
,
output
wire
[
1
:
0
]
EXP_DRQ
,
input
wire
[
1
:
0
]
EXP_DLAST
);
`ifdef
ACCELERATOR_SUBSYSTEM
// Instantiate Accelerator Subsystem
accelerator_subsystem
#(
.
SYS_ADDR_W
(
SYS_ADDR_W
),
.
SYS_DATA_W
(
SYS_DATA_W
)
)
u_accelerator_ss
(
.
HSEL
(
HSEL
),
.
HADDR
(
HADDR
),
.
HTRANS
(
HTRANS
),
.
HSIZE
(
HSIZE
),
.
HPROT
(
HPROT
),
.
HWRITE
(
HWRITE
),
.
HREADY
(
HREADY
),
.
HWDATA
(
HWDATA
),
.
HREADYOUT
(
HREADYOUT
),
.
HRESP
(
HRESP
),
.
HRDATA
(
HRDATA
),
.
EXP_IRQ
(
EXP_IRQ
),
.
EXP_DRQ
(
EXP_DRQ
),
.
EXP_DLAST
(
EXP_DLAST
)
);
`else
// Default slave - if no expansion region
cmsdk_ahb_default_slave
u_accelerator_ss_default
(
.
HCLK
(
HCLK
),
.
HRESETn
(
HRESETn
),
.
HSEL
(
HSEL
),
.
HTRANS
(
HTRANS
),
.
HREADY
(
HREADY
),
.
HREADYOUT
(
HREADYOUTS
),
.
HRESP
(
HRESPS
)
);
assign
HRDATA
=
32'heaedeaed
;
// Tie off Expansion Address Expansion Data
assign
EXP_IRQ
=
4'b0
;
assign
EXP_DRQ
=
2'b0
;
`endif
endmodule
\ No newline at end of file
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slcore_m0_tech
@
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