SOC1-230: Updated expansion region

system/nanosoc_regions/exp/verilog/nanosoc_region_exp.v

@@ -16,23 +16,61 @@ module nanosoc_region_exp #(
     input  wire                  HCLK,       // Clock
     input  wire                  HRESETn,    // Reset
 
-    // AHB connection to Initiator
-    input  wire                   HSELS,
-    input  wire  [SYS_ADDR_W-1:0] HADDRS,
-    input  wire             [1:0] HTRANSS,
-    input  wire             [2:0] HSIZES,
-    input  wire             [3:0] HPROTS,
-    input  wire                   HWRITES,
-    input  wire                   HREADYS,
-    input  wire            [31:0] HWDATAS,
+    // AHB Subortinate Port
+    input  wire                   HSEL,
+    input  wire  [SYS_ADDR_W-1:0] HADDR,
+    input  wire             [1:0] HTRANS,
+    input  wire             [2:0] HSIZE,
+    input  wire             [3:0] HPROT,
+    input  wire                   HWRITE,
+    input  wire                   HREADY,
+    input  wire  [SYS_DATA_W-1:0] HWDATA,
 
-    output wire                   HREADYOUTS,
-    output wire                   HRESPS,
-    output wire            [31:0] HRDATAS,
+    output wire                   HREADYOUT,
+    output wire                   HRESP,
+    output wire  [SYS_DATA_W-1:0] HRDATA,
     
-    // Interrupt Connections
-    output wire                   ip_data_req,
-    output wire                   op_data_req
+    // Interrupt and DMAC Connections
+    output wire             [3:0] EXP_IRQ,
+    output wire             [1:0] EXP_DRQ,
+    input  wire             [1:0] EXP_DLAST
 );
 
+`ifdef ACCELERATOR_SUBSYSTEM
+    // Instantiate Accelerator Subsystem
+    accelerator_subsystem #(
+        .SYS_ADDR_W (SYS_ADDR_W),
+        .SYS_DATA_W (SYS_DATA_W)
+    ) u_accelerator_ss (
+        .HSEL(HSEL),
+        .HADDR(HADDR),
+        .HTRANS(HTRANS),
+        .HSIZE(HSIZE),
+        .HPROT(HPROT),
+        .HWRITE(HWRITE),
+        .HREADY(HREADY),
+        .HWDATA(HWDATA),
+        .HREADYOUT(HREADYOUT),
+        .HRESP(HRESP),
+        .HRDATA(HRDATA),
+        .EXP_IRQ(EXP_IRQ),
+        .EXP_DRQ(EXP_DRQ),
+        .EXP_DLAST(EXP_DLAST)
+    );
+`else 
+    // Default slave - if no expansion region
+    cmsdk_ahb_default_slave u_accelerator_ss_default (
+        .HCLK         (HCLK),
+        .HRESETn      (HRESETn),
+        .HSEL         (HSEL),
+        .HTRANS       (HTRANS),
+        .HREADY       (HREADY),
+        .HREADYOUT    (HREADYOUTS),
+        .HRESP        (HRESPS)
+    );
+    assign   HRDATA = 32'heaedeaed; // Tie off Expansion Address Expansion Data
+    assign   EXP_IRQ = 4'b0;
+    assign   EXP_DRQ = 2'b0;
+`endif
+
 endmodule
\ No newline at end of file

slcore_m0_tech @ 0e036061

-Subproject commit 8d4d1ca205c942d1676180055dd93f5a49f4f7f7
+Subproject commit 0e036061823074e2fe41fc7ea83d58367ea3b524