Copies log from run to target at end

fpga/makefile

@@ -95,6 +95,7 @@ build_fpga: tcl_flist clean_fpga
 	@echo Starting Vivado Run
 	@mkdir -p $(RUN_DIR)
 	@cd $(RUN_DIR); vivado -mode batch -source $(NANOSOC_FPGA_FLOW_DIR)/build_fpga.tcl
+	@cp $(RUN_DIR)/vivado.log $(TARGET_DIR)
 	@echo Vivado Build Complete
 
 # Clean FPGA Run