PnR flow added plus ROM implementation
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- flist/corstone101_ip_ASIC.flist 3 additions, 3 deletionsflist/corstone101_ip_ASIC.flist
- flows/makefile.asic 40 additions, 1 deletionflows/makefile.asic
- nanosoc/nanosoc_regions/expram_h/verilog/nanosoc_region_expram_h.v 0 additions, 6 deletions...anosoc_regions/expram_h/verilog/nanosoc_region_expram_h.v
- nanosoc/nanosoc_regions/expram_l/verilog/nanosoc_region_expram_l.v 8 additions, 0 deletions...anosoc_regions/expram_l/verilog/nanosoc_region_expram_l.v
- synthesis/clock_tree_synthesis.tcl 23 additions, 0 deletionssynthesis/clock_tree_synthesis.tcl
- synthesis/constraints.sdc 12 additions, 3 deletionssynthesis/constraints.sdc
- synthesis/design_import.tcl 32 additions, 0 deletionssynthesis/design_import.tcl
- synthesis/genus.tcl 13 additions, 12 deletionssynthesis/genus.tcl
- synthesis/icc_shell.tcl 18 additions, 0 deletionssynthesis/icc_shell.tcl
- synthesis/io_plan.tcl 16 additions, 0 deletionssynthesis/io_plan.tcl
- synthesis/nanosoc.mmmc 81 additions, 0 deletionssynthesis/nanosoc.mmmc
- synthesis/nanosoc_chip_pads_power.upf 17 additions, 0 deletionssynthesis/nanosoc_chip_pads_power.upf
- synthesis/place.tcl 21 additions, 0 deletionssynthesis/place.tcl
- synthesis/pnr_flow.tcl 40 additions, 0 deletionssynthesis/pnr_flow.tcl
- synthesis/power_plan.tcl 24 additions, 0 deletionssynthesis/power_plan.tcl
- synthesis/power_route.tcl 8 additions, 0 deletionssynthesis/power_route.tcl
- synthesis/rf_sp_hdf.spec 33 additions, 0 deletionssynthesis/rf_sp_hdf.spec
- synthesis/rom_via.spec 30 additions, 0 deletionssynthesis/rom_via.spec
- synthesis/route.tcl 18 additions, 0 deletionssynthesis/route.tcl
- synthesis/synopsys.tcl 15 additions, 6 deletionssynthesis/synopsys.tcl
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