From 6e00f61f43a675a2919c918d16df74494f00906c Mon Sep 17 00:00:00 2001
From: Daniel Newbrook <dwn1c21@soton.ac.uk>
Date: Mon, 21 Aug 2023 16:50:12 +0100
Subject: [PATCH] PnR flow added plus ROM implementation
---
flist/corstone101_ip_ASIC.flist | 6 +-
flows/makefile.asic | 41 +++++++++-
.../verilog/nanosoc_region_expram_h.v | 6 --
.../verilog/nanosoc_region_expram_l.v | 8 ++
synthesis/clock_tree_synthesis.tcl | 23 ++++++
synthesis/constraints.sdc | 15 +++-
synthesis/design_import.tcl | 32 ++++++++
synthesis/genus.tcl | 25 +++---
synthesis/icc_shell.tcl | 18 +++++
synthesis/io_plan.tcl | 16 ++++
synthesis/nanosoc.mmmc | 81 +++++++++++++++++++
synthesis/nanosoc_chip_pads_power.upf | 17 ++++
synthesis/place.tcl | 21 +++++
synthesis/pnr_flow.tcl | 40 +++++++++
synthesis/power_plan.tcl | 24 ++++++
synthesis/power_route.tcl | 8 ++
synthesis/rf_sp_hdf.spec | 33 ++++++++
synthesis/rom_via.spec | 30 +++++++
synthesis/route.tcl | 18 +++++
synthesis/synopsys.tcl | 21 +++--
20 files changed, 452 insertions(+), 31 deletions(-)
create mode 100644 synthesis/clock_tree_synthesis.tcl
create mode 100644 synthesis/design_import.tcl
create mode 100644 synthesis/icc_shell.tcl
create mode 100644 synthesis/io_plan.tcl
create mode 100644 synthesis/nanosoc.mmmc
create mode 100644 synthesis/nanosoc_chip_pads_power.upf
create mode 100644 synthesis/place.tcl
create mode 100644 synthesis/pnr_flow.tcl
create mode 100644 synthesis/power_plan.tcl
create mode 100644 synthesis/power_route.tcl
create mode 100644 synthesis/rf_sp_hdf.spec
create mode 100644 synthesis/rom_via.spec
create mode 100644 synthesis/route.tcl
diff --git a/flist/corstone101_ip_ASIC.flist b/flist/corstone101_ip_ASIC.flist
index 6e7fa9c..2f2a60e 100644
--- a/flist/corstone101_ip_ASIC.flist
+++ b/flist/corstone101_ip_ASIC.flist
@@ -28,7 +28,7 @@ $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_timer/verilog/cmsdk
//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_frc.v
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers.v
-$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v
// CMSDK APB UART IP
@@ -39,7 +39,7 @@ $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_uart/verilog/cmsdk_
//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_frc.v
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog.v
-$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v
// CMSDK APB Slave Mux IP
//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_slave_mux/verilog
@@ -80,7 +80,7 @@ $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/clkgate/cmsdk_clock_ga
//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_ahb_ram_beh.v
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_ahb_ram.v
-$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_ahb_memory_models_defs.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_ahb_memory_models_defs.v
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_ahb_rom.v
$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_fpga_rom.v
diff --git a/flows/makefile.asic b/flows/makefile.asic
index c663c72..f53dced 100644
--- a/flows/makefile.asic
+++ b/flows/makefile.asic
@@ -32,6 +32,18 @@ TCL_OUTPUT_FILELIST := $(TCL_FLIST_DIR)/gen_flist.tcl
GENUS_OUTPUT_FILELIST := $(TCL_FLIST_DIR)/genus_flist.tcl
SYNTHESIS_OUTPUT_FILELIST := $(TCL_FLIST_DIR)/synth_flist_copy.sh
+# Location of outputs from synthesis
+MEMORIES_DIR := $(SOCLABS_PROJECT_DIR)/memories
+RF_SPEC_FILE := $(SOCLABS_NANOSOC_TECH_DIR)/synthesis/rf_sp_hdf.spec
+ROM_SPEC_FILE := $(SOCLABS_NANOSOC_TECH_DIR)/synthesis/rom_via.spec
+BOOTROM_BIN_FILE := $(SOCLABS_PROJECT_DIR)/system/src/bootrom/bintxt/bootrom.bintxt
+RF_DIR := $(MEMORIES_DIR)/rf
+ROM_DIR := $(MEMORIES_DIR)/bootrom
+REPORTS_FOLDER := $(IMP_NANOSOC_ASIC_DIR)/reports
+SYN_LOGS := $(IMP_NANOSOC_ASIC_DIR)/logs
+NETLIST_FOLDER := $(IMP_NANOSOC_ASIC_DIR)/netlist/
+NANOSOC_SYNTH_DIR := $(SOCLABS_NANOSOC_TECH_DIR)/synthesis/
+
# NanoSoC Tech Flow Dependencies
NANOSOC_FPGA_FLOW_DIR := $(SOCLABS_NANOSOC_TECH_DIR)/fpga
@@ -56,12 +68,39 @@ flist_genus_nanosoc: gen_defs
#copy_asic_nanosoc: SHELL:=/bin/bash
-copy_asic_nanosoc: flist_asic_nanosoc
+copy_asic_nanosoc: gen_defs flist_asic_nanosoc
@mkdir -p $(IMP_NANOSOC_ASIC_DIR)/src
@(cd $(IMP_NANOSOC_ASIC_DIR)/src)
@(chmod +x $(SYNTHESIS_OUTPUT_FILELIST))
@(source $(SYNTHESIS_OUTPUT_FILELIST))
+
+gen_memories: bootrom
+ @mkdir -p $(MEMORIES_DIR)
+ @mkdir -p $(RF_DIR)
+ @mkdir -p $(ROM_DIR)
+ echo "Generating register file memory libraries"
+ cd $(RF_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rf_sp_hdf_hvt_rvt/r0p0/bin/rf_sp_hdf_hvt_rvt ascii -spec $(RF_SPEC_FILE);
+ cd $(RF_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rf_sp_hdf_hvt_rvt/r0p0/bin/rf_sp_hdf_hvt_rvt liberty -spec $(RF_SPEC_FILE);
+ cd $(RF_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rf_sp_hdf_hvt_rvt/r0p0/bin/rf_sp_hdf_hvt_rvt postscript -spec $(RF_SPEC_FILE);
+ cd $(RF_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rf_sp_hdf_hvt_rvt/r0p0/bin/rf_sp_hdf_hvt_rvt lef-fp -spec $(RF_SPEC_FILE);
+ cd $(RF_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rf_sp_hdf_hvt_rvt/r0p0/bin/rf_sp_hdf_hvt_rvt verilog -spec $(RF_SPEC_FILE);
+ cd $(ROM_DIR)
+ echo "Generating ROM Libraries"
+ cd $(ROM_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rom_via_hdd_rvt_rvt/r0p0/bin/rom_via_hdd_rvt_rvt ascii -spec $(ROM_SPEC_FILE) -code_file $(BOOTROM_BIN_FILE);
+ cd $(ROM_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rom_via_hdd_rvt_rvt/r0p0/bin/rom_via_hdd_rvt_rvt liberty -spec $(ROM_SPEC_FILE) -code_file $(BOOTROM_BIN_FILE);
+ cd $(ROM_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rom_via_hdd_rvt_rvt/r0p0/bin/rom_via_hdd_rvt_rvt postscript -spec $(ROM_SPEC_FILE) -code_file $(BOOTROM_BIN_FILE);
+ cd $(ROM_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rom_via_hdd_rvt_rvt/r0p0/bin/rom_via_hdd_rvt_rvt lef-fp -spec $(ROM_SPEC_FILE) -code_file $(BOOTROM_BIN_FILE);
+ cd $(ROM_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rom_via_hdd_rvt_rvt/r0p0/bin/rom_via_hdd_rvt_rvt verilog -spec $(ROM_SPEC_FILE) -code_file $(BOOTROM_BIN_FILE);
+ echo "Finished generating memory libraries"
+
+syn_genus:
+ @mkdir -p $(REPORTS_FOLDER)
+ @mkdir -p $(NETLIST_FOLDER)
+ @mkdir -p $(SYN_LOGS)
+ cd $(NANOSOC_SYNTH_DIR)
+ @(genus -f $(NANOSOC_SYNTH_DIR)/genus.tcl -log $(SYN_LOGS)/nanosoc_synth)
+
# Clean FPGA Run
clean_synthesis:
@echo Cleaning Previous Runs of $(BOARD_NAME)
diff --git a/nanosoc/nanosoc_regions/expram_h/verilog/nanosoc_region_expram_h.v b/nanosoc/nanosoc_regions/expram_h/verilog/nanosoc_region_expram_h.v
index f41da67..6bc5f56 100644
--- a/nanosoc/nanosoc_regions/expram_h/verilog/nanosoc_region_expram_h.v
+++ b/nanosoc/nanosoc_regions/expram_h/verilog/nanosoc_region_expram_h.v
@@ -18,9 +18,6 @@ module nanosoc_region_expram_h #(
parameter EXPRAM_H_RAM_DATA_W = 32 // Width of RAM Data Bus - Default 32 bits
)(
`ifdef POWER_PINS
- inout wire VDDCE,
- inout wire VDDPE,
- inout wire VSSE,
inout wire VDD,
inout wire VSS,
`endif
@@ -49,9 +46,6 @@ module nanosoc_region_expram_h #(
.RAM_DATA_W (EXPRAM_H_RAM_DATA_W)
) u_expram_h (
`ifdef POWER_PINS
- .VDDCE (VDDCE),
- .VDDPE (VDDPE),
- .VSSE (VSSE),
.VDD (VDD),
.VSS (VSS),
`endif
diff --git a/nanosoc/nanosoc_regions/expram_l/verilog/nanosoc_region_expram_l.v b/nanosoc/nanosoc_regions/expram_l/verilog/nanosoc_region_expram_l.v
index 76f078f..668744c 100644
--- a/nanosoc/nanosoc_regions/expram_l/verilog/nanosoc_region_expram_l.v
+++ b/nanosoc/nanosoc_regions/expram_l/verilog/nanosoc_region_expram_l.v
@@ -17,6 +17,10 @@ module nanosoc_region_expram_l #(
parameter EXPRAM_L_RAM_ADDR_W = 14, // Width of RAM Address - Default 16KB
parameter EXPRAM_L_RAM_DATA_W = 32 // Width of RAM Data Bus - Default 32 bits
)(
+ `ifdef POWER_PINS
+ inout wire VDD,
+ inout wire VSS,
+ `endif
input wire HCLK,
input wire HRESETn,
@@ -41,6 +45,10 @@ module nanosoc_region_expram_l #(
.RAM_ADDR_W (EXPRAM_L_RAM_ADDR_W),
.RAM_DATA_W (EXPRAM_L_RAM_DATA_W)
) u_expram_l (
+ `ifdef POWER_PINS
+ .VDD (VDD),
+ .VSS (VSS),
+ `endif
// AHB Inputs
.HCLK (HCLK),
.HRESETn (HRESETn),
diff --git a/synthesis/clock_tree_synthesis.tcl b/synthesis/clock_tree_synthesis.tcl
new file mode 100644
index 0000000..5e8a3ed
--- /dev/null
+++ b/synthesis/clock_tree_synthesis.tcl
@@ -0,0 +1,23 @@
+############################################
+# Script : Clock Tree Implementation
+# Date : 24th May 2023
+# Author : Srimanth Tenneti
+# Description : Implements the Clock Tree
+############################################
+
+### Buffer Cells
+set_db cts_buffer_cells {*BUFH*}
+### Inverter Cells
+set_db cts_inverter_cells {*INV*}
+
+### Clock Tree Sepc
+create_clock_tree_spec -out_file design_clk.spec
+
+### Creating a Clock Tree
+ccopt_design
+
+### Optimizing the design
+opt_design -post_cts
+opt_design -post_cts -hold
+
+
diff --git a/synthesis/constraints.sdc b/synthesis/constraints.sdc
index 14f09d2..60124c4 100644
--- a/synthesis/constraints.sdc
+++ b/synthesis/constraints.sdc
@@ -12,15 +12,19 @@
#### CLOCK DEFINITION
set EXTCLK "clk";
+set SWDCLK "swdclk";
set_units -time 1.0ns;
set_units -capacitance 1.0pF;
-set EXTCLK_PERIOD 10.0;
+set EXTCLK_PERIOD 4;
+set SWDCLK_PERIOD 20;
create_clock -name "$EXTCLK" -period "$EXTCLK_PERIOD" -waveform "0 [expr $EXTCLK_PERIOD/2]" [get_ports XTAL1]
+create_clock -name "$SWDCLK" -period "$SWDCLK_PERIOD" -waveform "0 [expr $SWDCLK_PERIOD/2]" [get_ports SWCLKTCK]
set SKEW 0.200
set_clock_uncertainty $SKEW [get_clocks $EXTCLK]
+set_clock_uncertainty $SKEW [get_clocks $SWDCLK]
set MINRISE 0.20
set MAXRISE 0.25
@@ -32,13 +36,18 @@ set_clock_transition -rise -max $MAXRISE [get_clocks $EXTCLK]
set_clock_transition -fall -min $MINFALL [get_clocks $EXTCLK]
set_clock_transition -fall -min $MINFALL [get_clocks $EXTCLK]
+set_clock_transition -rise -min $MINRISE [get_clocks $SWDCLK]
+set_clock_transition -rise -max $MAXRISE [get_clocks $SWDCLK]
+set_clock_transition -fall -min $MINFALL [get_clocks $SWDCLK]
+set_clock_transition -fall -min $MINFALL [get_clocks $SWDCLK]
+
#### DELAY DEFINITION
set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.3 [get_ports NRST]
set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.3 [get_ports P0]
set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.3 [get_ports P1]
-set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.3 [get_ports SWDIOTMS]
-set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.3 [get_ports SWCLKTCK]
+set_input_delay -clock [get_clocks $SWDCLK] -add_delay 0.3 [get_ports SWDIOTMS]
+set_input_delay -clock [get_clocks $SWDCLK] -add_delay 0.3 [get_ports SWCLKTCK]
set_max_capacitance 0.5 [all_outputs]
set_max_fanout 10 [all_inputs]
\ No newline at end of file
diff --git a/synthesis/design_import.tcl b/synthesis/design_import.tcl
new file mode 100644
index 0000000..f642800
--- /dev/null
+++ b/synthesis/design_import.tcl
@@ -0,0 +1,32 @@
+#########################################
+# File : Design Import Logic
+# Date : 22nd May 2022
+# Author : Srimanth Tenneti
+# Description : MMMC + Design Import
+#########################################
+
+### Settting PG Nets
+set_db init_power_nets {VDD VDDIO}
+set_db init_ground_nets {VSS VSSIO}
+
+### Processing MMMC
+read_mmmc nanosoc.mmmc
+set TECH_LEF $::env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/lef/1p9m_6x2z/sc9_tech.lef
+set BASE_LEF $::env(PHYS_IP)/arm/tsmc/cln65lp/sc9_base_rvt/r0p0/lef/sc9_cln65lp_base_rvt.lef
+set RF_LEF $::env(SOCLABS_PROJECT_DIR)/memories/rf/rf_sp_hdf.lef
+set ROM_LEF $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via.lef
+
+### Reading LEFs
+read_physical -lef [list ${TECH_LEF} ${BASE_LEF} ${RF_LEF} ${ROM_LEF}]
+
+### Reading Netlist
+read_netlist ./nanosoc_chip_pads.vm
+
+### Initializing the Design
+init_design
+
+### Adjusting the GUI
+gui_fit
+
+create_floorplan -site sc9_cln65lp -core_size 900 900 50 50 50 50
+
diff --git a/synthesis/genus.tcl b/synthesis/genus.tcl
index ea13d31..bc18590 100644
--- a/synthesis/genus.tcl
+++ b/synthesis/genus.tcl
@@ -1,26 +1,27 @@
set_db init_lib_search_path ./
-set BASE_LIB $::env(PHYS_IP)/arm/tsmc/cln65lp/sc9_base_rvt/r0p0/lib/sc9_cln65lp_base_rvt_tt_typical_max_1p20v_25c.lib
-set RF_LIB ../../../cadence_flow/memory/rf/rf_sp_hdf_tt_1p20v_1p20v_25c.lib
-set_db / .library "$BASE_LIB $RF_LIB"
+set BASE_LIB $::env(PHYS_IP)/arm/tsmc/cln65lp/sc9_base_rvt/r0p0/lib/sc9_cln65lp_base_rvt_ss_typical_max_1p08v_125c.lib
+set RF_LIB $::env(SOCLABS_PROJECT_DIR)/memories/rf/rf_sp_hdf_ss_1p08v_1p08v_125c.lib
+set ROM_LIB $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via_ss_1p08v_1p08v_125c.lib
+set_db / .library "$BASE_LIB $RF_LIB $ROM_LIB"
source $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/genus_flist.tcl
elaborate nanosoc_chip_pads
-source constraints.sdc
+read_sdc $::env(SOCLABS_NANOSOC_TECH_DIR)/synthesis/constraints.sdc
set_db syn_generic_effort high
+set_db syn_map_effort high
syn_generic
-
syn_map
+syn_opt
+
+report_area > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_area.rep
+report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_timing.rep
+report_gates > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_gates.rep
+report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_power.rep
-report_area
-report_timing
-report_gates
+write_hdl > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads.vm
-write_hdl > nanosoc_chip_pads.vm
-write_sdc > constraints.write_sdc
-write_script > constraints.g
-write_design -innovus nanosoc_chip_pads
exit
diff --git a/synthesis/icc_shell.tcl b/synthesis/icc_shell.tcl
new file mode 100644
index 0000000..b6c4541
--- /dev/null
+++ b/synthesis/icc_shell.tcl
@@ -0,0 +1,18 @@
+set design_name nanosoc_chip_pads
+create_lib -technology /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln65lp/arm_tech/r2p0/milkyway/1p9m_6x2z/sc9_tech.tf -ref_libs /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln65lp/sc9_base_rvt/r0p0/lef/sc9_cln65lp_base_rvt.lef tsmc65lp
+
+read_parasitic_tech -name {typical} -tlup {/home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/typical.tluplus} -layermap {/home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/tluplus.map}
+read_parasitic_tech -name {rcbest} -tlup {/home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/rcbest.tluplus} -layermap {/home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/tluplus.map}
+read_parasitic_tech -name {rcworst} -tlup {/home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/rcworst.tluplus} -layermap {/home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/tluplus.map}
+
+
+read_verilog_outline -library tsmc65lp -design nanosoc_chip_pads -top nanosoc_chip_pads nanosoc_chip_pads.vm
+link_block
+initialize_floorplan -control_type die -keep_pg_route -side_ratio {1000 1000} -core_offset {100 100} -keep_placement {all}
+create_io_ring -name main_io
+explore_logic_hierarchy -organize
+
+load_upf nanosoc_chip_pads_power.upf
+commit_upf
+
+
diff --git a/synthesis/io_plan.tcl b/synthesis/io_plan.tcl
new file mode 100644
index 0000000..07c1152
--- /dev/null
+++ b/synthesis/io_plan.tcl
@@ -0,0 +1,16 @@
+################################
+# Script : IO Place
+# Author : Srimanth Tenneti
+# Date : 22nd May 2022
+###############################
+
+### Pin Place
+edit_pin -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Top -layer 9 -spread_type center -spacing 30 -pin {XTAL1 XTAL2 NRST VDD VDDIO}
+
+edit_pin -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Bottom -layer 9 -spread_type center -spacing 30 -pin {SWDIOTMS SWCLKTCK VSS VSSIO}
+
+edit_pin -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Left -layer 9 -spread_type center -spacing 30 -pin {{P0[0]} {P0[1]} {P0[2]} {P0[3]} {P0[4]} {P0[5]} {P0[6]} {P0[7]} {P0[8]} {P0[9]} {P0[10]} {P0[11]} {P0[12]} {P0[13]} {P0[14]} {P0[15]}}
+
+edit_pin -pin_width 1.5 -pin_depth 1.5 -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Right -layer 9 -spread_type center -spacing 30 -pin {{P1[0]} {P1[1]} {P1[2]} {P1[3]} {P1[4]} {P1[5]} {P1[6]} {P1[7]} {P1[8]} {P1[9]} {P1[10]} {P1[11]} {P1[12]} {P1[13]} {P1[14]} {P1[15]}}
+
+gui_fit
diff --git a/synthesis/nanosoc.mmmc b/synthesis/nanosoc.mmmc
new file mode 100644
index 0000000..467a029
--- /dev/null
+++ b/synthesis/nanosoc.mmmc
@@ -0,0 +1,81 @@
+set base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln65lp/sc9_base_rvt/r0p0
+set tech_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln65lp/arm_tech/r2p0
+set ram_path /home/dwn1c21/SoC-Labs/nanosoc_clk/accelerator-project/memories/rf/
+set rom_path /home/dwn1c21/SoC-Labs/nanosoc_clk/accelerator-project/memories/bootrom/
+
+create_library_set -name default_libset_max\
+ -timing\
+ [list ${base_path}/lib/sc9_cln65lp_base_rvt_ss_typical_max_1p08v_125c.lib ${ram_path}/rf_sp_hdf_ss_1p08v_1p08v_125c.lib ${rom_path}/rom_via_ss_1p08v_1p08v_125c.lib] \
+ -si\
+ [list ${base_path}/celtic/sc9_cln65lp_base_rvt_ss_typical_max_1p08v_125c.cdB]
+
+create_library_set -name default_libset_min\
+ -timing\
+ [list ${base_path}/lib/sc9_cln65lp_base_rvt_ff_typical_min_1p32v_m40c.lib ${ram_path}/rf_sp_hdf_ff_1p32v_1p32v_m40c.lib ${rom_path}/rom_via_ff_1p32v_1p32v_m40c.lib] \
+ -si\
+ [list ${base_path}/celtic/sc9_cln65lp_base_rvt_ff_typical_min_1p32v_m40c.cdB]
+
+create_timing_condition -name default_mapping_tc_2\
+ -library_sets [list default_libset_min]
+create_timing_condition -name default_mapping_tc_1\
+ -library_sets [list default_libset_max]
+
+create_rc_corner -name default_rc_corner_worst\
+ -pre_route_res 1\
+ -post_route_res 1\
+ -pre_route_cap 1\
+ -post_route_cap 1\
+ -post_route_cross_cap 1\
+ -pre_route_clock_res 0\
+ -pre_route_clock_cap 0\
+ -cap_table ${tech_path}/cadence_captable/1p9m_6x2z/rcworst.captbl
+
+create_rc_corner -name default_rc_corner_best\
+ -pre_route_res 1\
+ -post_route_res 1\
+ -pre_route_cap 1\
+ -post_route_cap 1\
+ -post_route_cross_cap 1\
+ -pre_route_clock_res 0\
+ -pre_route_clock_cap 0\
+ -cap_table ${tech_path}/cadence_captable/1p9m_6x2z/rcbest.captbl
+
+create_rc_corner -name default_rc_corner_typical\
+ -pre_route_res 1\
+ -post_route_res 1\
+ -pre_route_cap 1\
+ -post_route_cap 1\
+ -post_route_cross_cap 1\
+ -pre_route_clock_res 0\
+ -pre_route_clock_cap 0\
+ -cap_table ${tech_path}/cadence_captable/1p9m_6x2z/typical.captbl
+
+
+
+create_delay_corner -name default_delay_corner_max\
+ -timing_condition {default_mapping_tc_1}\
+ -rc_corner default_rc_corner_worst
+
+create_delay_corner -name default_delay_corner_ocv\
+ -early_timing_condition {default_mapping_tc_2}\
+ -late_timing_condition {default_mapping_tc_1}\
+ -rc_corner default_rc_corner_typical
+
+create_delay_corner -name default_delay_corner_min\
+ -timing_condition default_mapping_tc_2\
+ -rc_corner default_rc_corner_best
+
+create_constraint_mode -name default_constraint_mode\
+ -sdc_files\
+ [list ./constraints.sdc]
+
+create_analysis_view -name default_analysis_view_setup -constraint_mode default_constraint_mode -delay_corner default_delay_corner_max
+
+create_analysis_view -name default_analysis_view_hold -constraint_mode default_constraint_mode -delay_corner default_delay_corner_min
+
+
+create_analysis_view -name typical_analysis_view_setup -constraint_mode default_constraint_mode -delay_corner default_delay_corner_ocv
+create_analysis_view -name typical_analysis_view_hold -constraint_mode default_constraint_mode -delay_corner default_delay_corner_ocv
+
+
+set_analysis_view -setup [list default_analysis_view_setup] -hold [list default_analysis_view_hold]
diff --git a/synthesis/nanosoc_chip_pads_power.upf b/synthesis/nanosoc_chip_pads_power.upf
new file mode 100644
index 0000000..72339c3
--- /dev/null
+++ b/synthesis/nanosoc_chip_pads_power.upf
@@ -0,0 +1,17 @@
+create_power_domain pd_top -include_scope
+create_supply_port VDD -domain pd_top
+create_supply_port VDDIO -domain pd_top
+create_supply_port VSS -domain pd_top
+create_supply_port VSSIO -domain pd_top
+
+create_supply_net VDD -domain pd_top
+create_supply_net VDDIO -domain pd_top
+create_supply_net VSS -domain pd_top
+create_supply_net VSSIO -domain pd_top
+
+connect_supply_net VDD -ports VDD
+connect_supply_net VDDIO -ports VDDIO
+connect_supply_net VSS -ports VSS
+connect_supply_net VSSIO -ports VSSIO
+
+set_domain_supply_net pd_top -primary_power_net VDD -primary_ground_net VSS
\ No newline at end of file
diff --git a/synthesis/place.tcl b/synthesis/place.tcl
new file mode 100644
index 0000000..cc6fcde
--- /dev/null
+++ b/synthesis/place.tcl
@@ -0,0 +1,21 @@
+############################################
+# Script : Placement
+# Date : May 24 2024
+# Author : Srimanth Tenneti
+############################################
+
+### Congestion and Timing Setting
+set_db design_process_node 65
+set_db place_global_cong_effort auto
+set_db place_global_timing_effort high
+
+### Uniform Cell Distribution
+
+set_db place_global_uniform_density true
+
+### Placement Mode Config
+set_db place_design_floorplan_mode false
+place_design
+
+### Delay Calculation
+write_sdf design.sdf -ideal_clock_network
diff --git a/synthesis/pnr_flow.tcl b/synthesis/pnr_flow.tcl
new file mode 100644
index 0000000..ea6c5dc
--- /dev/null
+++ b/synthesis/pnr_flow.tcl
@@ -0,0 +1,40 @@
+######################################
+# Script : Place and Route Flow
+# Date : 25th May 2023
+# Author : Srimanth Tenneti
+# Description : Innovus PnR Flow
+######################################
+
+puts "Starting PnR Flow ..."
+
+
+### Design Import
+source design_import.tcl
+
+### IO Planning
+source io_plan.tcl
+
+### Power Plan
+source power_plan.tcl
+
+### Power Route
+source power_route.tcl
+
+### Placement
+source place.tcl
+
+### CTS
+source clock_tree_synthesis.tcl
+
+### Routing
+source route.tcl
+
+report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_timing.rep
+report_area > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_area.rep
+report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_power.rep
+
+gui_show
+
+
+
+
diff --git a/synthesis/power_plan.tcl b/synthesis/power_plan.tcl
new file mode 100644
index 0000000..279c218
--- /dev/null
+++ b/synthesis/power_plan.tcl
@@ -0,0 +1,24 @@
+#########################################
+# Script : Power Planning
+# Tool : Cadence Innovus
+# Date : May 22, 2023
+# Author : Srimanth Tenneti
+#########################################
+
+### Connecting Global Nets
+connect_global_net VDD -type pg_pin -pin_base_name VDD -inst_base_name *
+connect_global_net VDDIO -type pg_pin -pin_base_name VDDIO -inst_base_name *
+connect_global_net VSS -type pg_pin -pin_base_name VSS -inst_base_name *
+connect_global_net VSSIO -type pg_pin -pin_base_name VSSIO -inst_base_name *
+### Top and Bottom Metal Declartions
+set_db add_rings_stacked_via_top_layer M8
+set_db add_rings_stacked_via_bottom_layer M1
+
+### Adding Rings
+add_rings -nets {VDD VDDIO VSS VSSIO} -type core_rings -follow core -layer {top M7 bottom M7 left M8 right M8} -width {top 8 bottom 8 left 8 right 8} -spacing {top 2 bottom 2 left 2 right 2} -offset {top 1 bottom 1 left 1 right 1} -center 0 -threshold 0 -jog_distance 0 -snap_wire_center_to_grid none
+
+### Adding Stripes
+add_stripes -nets {VDD VDDIO VSS VSSIO} -layer M8 -direction vertical -width 4 -spacing 1 \
+-number_of_sets 8 -start_from left -start_offset 100 -stop_offset 100 -switch_layer_over_obs false \
+-max_same_layer_jog_length 50 -pad_core_ring_top_layer_limit M8 -pad_core_ring_bottom_layer_limit M1 \
+-block_ring_top_layer_limit M8 -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none
diff --git a/synthesis/power_route.tcl b/synthesis/power_route.tcl
new file mode 100644
index 0000000..f593a3f
--- /dev/null
+++ b/synthesis/power_route.tcl
@@ -0,0 +1,8 @@
+##################################
+# Script : Special Route Script
+# Date : May 24, 2023
+# Description : Power Routing
+# Author : Srimanth Tenneti
+##################################
+
+route_special -nets {VDD VSS} -connect core_pin -block_pin_target nearest_target -core_pin_target first_after_row_end -allow_jogging 1 -allow_layer_change 1 -layer_change_range { M1(1) M8(8) } -crossover_via_layer_range { M1(1) M8(8) } -target_via_layer_range { M1(1) M8(8) }
diff --git a/synthesis/rf_sp_hdf.spec b/synthesis/rf_sp_hdf.spec
new file mode 100644
index 0000000..29213c9
--- /dev/null
+++ b/synthesis/rf_sp_hdf.spec
@@ -0,0 +1,33 @@
+# user spec file, compiler rf_sp_hdf_hvt_rvt, version r0p0
+
+activity_factor = 50
+back_biasing = off
+bits = 32
+bmux = off
+bus_notation = on
+check_instname = on
+corners = ff_1p32v_1p32v_125c,ff_1p32v_1p32v_m40c,ss_1p08v_1p08v_125c,ss_1p08v_1p08v_m40c,tt_1p20v_1p20v_25c
+cust_comment =
+diodes = on
+drive = 6
+ema = on
+frequency = 150
+instname = rf_sp_hdf
+left_bus_delim = [
+libertyviewstyle = nldm
+libname = RF_LIB
+mux = 8
+mvt =
+name_case = upper
+power_type = otc
+prefix =
+pwr_gnd_rename = vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
+retention = on
+right_bus_delim = ]
+ser = none
+site_def = off
+top_layer = m5-m10
+words = 256
+wp_size = 1
+write_mask = on
+write_thru = off
diff --git a/synthesis/rom_via.spec b/synthesis/rom_via.spec
new file mode 100644
index 0000000..983fb53
--- /dev/null
+++ b/synthesis/rom_via.spec
@@ -0,0 +1,30 @@
+# user spec file, compiler rom_via_hdd_rvt_rvt, version r0p0
+
+activity_factor = 10
+back_biasing = off
+bits = 32
+bmux = on
+bus_notation = on
+check_instname = on
+corners = ff_1p32v_1p32v_125c,ff_1p32v_1p32v_m40c,ss_1p08v_1p08v_125c,ss_1p08v_1p08v_m40c,tt_1p20v_1p20v_25c
+cust_comment =
+diodes = on
+drive = 6
+ema = on
+frequency = 300
+instname = rom_via
+left_bus_delim = [
+libertyviewstyle = nldm
+libname = USERLIB
+mode = random
+mux = 8
+mvt =
+name_case = upper
+power_gating = on
+power_type = otc
+prefix =
+pwr_gnd_rename = vdde:VDDE,vsse:VSSE
+right_bus_delim = ]
+site_def = off
+top_layer = m5-m10
+words = 256
diff --git a/synthesis/route.tcl b/synthesis/route.tcl
new file mode 100644
index 0000000..b12b097
--- /dev/null
+++ b/synthesis/route.tcl
@@ -0,0 +1,18 @@
+
+### Clock Net Spacing
+set_route_attributes -nets clk -preferred_extra_space_tracks 2
+
+### Multi Cut Via Effort
+set_db route_design_detail_use_multi_cut_via_effort medium
+
+### Timing Driven Route
+set_db route_design_with_timing_driven 1
+
+### SI Driven Route
+set_db route_design_with_si_driven 1
+
+### Route Design
+route_design -global_detail
+
+### Timing Analysis Type
+set_db timing_analysis_type ocv
diff --git a/synthesis/synopsys.tcl b/synthesis/synopsys.tcl
index 77d91ea..3c45896 100644
--- a/synthesis/synopsys.tcl
+++ b/synthesis/synopsys.tcl
@@ -1,3 +1,14 @@
+#-----------------------------------------------------------------------------
+# NanoSoC Synopsys synthesis tcl file to be run with dc_shell
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# Daniel Newbrook (d.newbrook@soton.ac.uk)
+#
+# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
set rtlPath $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/src/
set top_module nanosoc_chip_pads
supress_message = {ELAB-405}
@@ -7,7 +18,7 @@ supress_message = {ELAB-405}
# List locations where your standard cell libraries may be located
#
#####
-set search_path [list . $search_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln65lp/sc9_base_rvt/r0p0/sdb/ /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln65lp/sc9_base_rvt/r0p0/db/ /home/dwn1c21/SoC-Labs/accelerator-project/memories/rf]
+set search_path [list . $search_path $env(PHYS_IP)/arm/tsmc/cln65lp/sc9_base_rvt/r0p0/sdb/ $env(PHYS_IP)/arm/tsmc/cln65lp/sc9_base_rvt/r0p0/db/ $env(SOCLABS_PROJECT_DIR)/memories/rf]
set search_path [concat $rtlPath $search_path]
######
# Set Target Library
@@ -27,9 +38,9 @@ set link_library sc9_cln65lp_base_rvt_tt_typical_max_1p20v_25c.db
#read_file {/home/dwn1c21/SoC-Labs/accelerator-project/imp/ASIC/nanosoc/src/} -autoread -recursive -format verilog -top $top_module
-analyze -format verilog -lib WORK -define POWER_PINS [glob /home/dwn1c21/SoC-Labs/accelerator-project/imp/ASIC/nanosoc/src/*.v]
-analyze -format sverilog -lib WORK -define POWER_PINS [glob /home/dwn1c21/SoC-Labs/accelerator-project/imp/ASIC/nanosoc/src/*.sv]
-elaborate $top_module -lib WORK -update
+analyze -format sverilog -lib WORK -define POWER_PINS [glob $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/src/*.sv]
+analyze -format verilog -lib WORK -define POWER_PINS [glob $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/src/*.v]
+elaborate $top_module -lib WORK
current_design $top_module
# Link Design
@@ -43,8 +54,6 @@ set_load 0.1 [all_outputs]
set_max_fanout 1 [all_inputs]
set_fanout_load 8 [all_outputs]
-redirect [format "%s%s%s" ./ $top_module _ports.rep { report_ports }
-
compile_ultra -exact_map
write -hierarchy -format verilog -output ./nanosoc_chip_pads.vm
--
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