disable UART0,1 and just keep UART2 as APB serial peripheral

Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_sysio.v

@@ -402,13 +402,13 @@ module nanosoc_sysio
     .APB_EXT_PORT13_ENABLE   (1),
     .APB_EXT_PORT14_ENABLE   (1),
     .APB_EXT_PORT15_ENABLE   (1),
-    .INCLUDE_IRQ_SYNCHRONIZER(0),
-    .INCLUDE_APB_TEST_SLAVE  (1),
+    .INCLUDE_IRQ_SYNCHRONIZER(0),  // require IRQs to be HCLK synchronous
+    .INCLUDE_APB_TEST_SLAVE  (1),  // Include example test slave
     .INCLUDE_APB_TIMER0      (1),  // Include simple timer #0
     .INCLUDE_APB_TIMER1      (1),  // Include simple timer #1
     .INCLUDE_APB_DUALTIMER0  (1),  // Include dual timer module
-    .INCLUDE_APB_UART0       (1),  // Include simple UART #0
-    .INCLUDE_APB_UART1       (1),  // Include simple UART #1
+    .INCLUDE_APB_UART0       (0),  // Exclude simple UART #0
+    .INCLUDE_APB_UART1       (0),  // Exclude simple UART #1
     .INCLUDE_APB_UART2       (1),  // Include simple UART #2.
     .INCLUDE_APB_WATCHDOG    (1),  // Include APB watchdog module
     .BE                      (BE)