From 6138eb07a20f6394b39ea5f53f553a4300d8b6e4 Mon Sep 17 00:00:00 2001
From: dwf1m12 <d.w.flynn@soton.ac.uk>
Date: Sun, 19 Mar 2023 06:17:17 +0000
Subject: [PATCH] disable UART0,1 and just keep UART2 as APB serial peripheral
---
Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_sysio.v | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_sysio.v b/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_sysio.v
index 456a2b6..29306dc 100644
--- a/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_sysio.v
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_sysio.v
@@ -402,13 +402,13 @@ module nanosoc_sysio
.APB_EXT_PORT13_ENABLE (1),
.APB_EXT_PORT14_ENABLE (1),
.APB_EXT_PORT15_ENABLE (1),
- .INCLUDE_IRQ_SYNCHRONIZER(0),
- .INCLUDE_APB_TEST_SLAVE (1),
+ .INCLUDE_IRQ_SYNCHRONIZER(0), // require IRQs to be HCLK synchronous
+ .INCLUDE_APB_TEST_SLAVE (1), // Include example test slave
.INCLUDE_APB_TIMER0 (1), // Include simple timer #0
.INCLUDE_APB_TIMER1 (1), // Include simple timer #1
.INCLUDE_APB_DUALTIMER0 (1), // Include dual timer module
- .INCLUDE_APB_UART0 (1), // Include simple UART #0
- .INCLUDE_APB_UART1 (1), // Include simple UART #1
+ .INCLUDE_APB_UART0 (0), // Exclude simple UART #0
+ .INCLUDE_APB_UART1 (0), // Exclude simple UART #1
.INCLUDE_APB_UART2 (1), // Include simple UART #2.
.INCLUDE_APB_WATCHDOG (1), // Include APB watchdog module
.BE (BE)
--
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