FIxed wiring issues with nanosoc expansion region

492dddbb · dam1n19 · 3d9e91a9 · 492dddbb · 492dddbb · 492dddbb
Commit 492dddbb authored 2 years ago by dam1n19
--- a/Cortex-M0/nanosoc/systems/mcu/rtl_sim/adp.cmd
+++ b/Cortex-M0/nanosoc/systems/mcu/rtl_sim/adp.cmd
@@ -5,25 +5,486 @@ R
 A
 A
 A 
-a 10000000
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-a 20000000
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-a 30000000
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-a 40006000
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-A
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-C 201
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  A
 X
 !
\ No newline at end of file
--- a/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip.v
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip.v
@@ -961,7 +961,7 @@ nanosoc_exp #(.ADDRWIDTH(29)
  .HADDRS      (HADDR_exp[28:0]),
  .HTRANSS     (HTRANS_exp),
  .HSIZES      (HSIZE_exp),
-  .HWRITES     (HWDATA_exp),
+  .HWRITES     (HWRITE_exp),
  .HREADYS     (HREADYMUX_exp),
  .HWDATAS     (HWDATA_exp),

--- a/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_exp.v
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_exp.v
@@ -12,7 +12,8 @@
 `include "cmsdk_ahb_slave_mux.v"
 module nanosoc_exp #(
-    parameter    ADDRWIDTH=29 // Region Address Width
+    parameter    ADDRWIDTH=29, // Region Address Width
+    parameter    ACCEL_ADDRWIDTH=12 // Region Address Width
  )(
    input  wire                  HCLK,       // Clock
    input  wire                  HRESETn,    // Reset
@@ -35,31 +36,17 @@ module nanosoc_exp #(
 // Internal Wires
 //********************************************************************************
-// AHB Lite BUS SIGNALS
-wire             hready;
-wire             hresp;
-wire [31:0]      hrdata;
-wire [1:0]       htrans;
-wire [2:0]       hburst;
-wire [3:0]       hprot;
-wire [2:0]       hsize;
-wire             hwrite;
-wire             hmastlock;
-wire [31:0]      haddr;
-wire [31:0]      hwdata;
 // Accelerator AHB Signals
-wire             hsel0;
+wire             HSEL0;
-wire             hreadyout0;
+wire             HREADYOUT0;
-wire             hresp0;
+wire             HRESP0;
-wire [31:0]      hrdata0;
+wire [31:0]      HRDATA0;
 // Default Slave AHB Signals
-wire             hsel1;
+wire             HSEL1;
-wire             hreadyout1;
+wire             HREADYOUT1;
-wire             hresp1;
+wire             HRESP1;
-wire [31:0]      hrdata1;
+wire [31:0]      HRDATA1;
 //********************************************************************************
 // Address decoder, need to be changed for other configuration
@@ -67,8 +54,8 @@ wire [31:0]      hrdata1;
 // 0x00010000 - 0x00010FFF : HSEL #0 - Hash Accelerator
 // Other addresses         : HSEL #1 - Default slave
-  assign hsel0 = (haddr[ADDRWIDTH-1:12] == 'h00010) ? 1'b1:1'b0;
+  assign HSEL0 = (HADDRS[ADDRWIDTH-1:12] == 'h00010) ? 1'b1:1'b0;
-  assign hsel1 = hsel0 ? 1'b0:1'b1;
+  assign HSEL1 = HSEL0 ? 1'b0:1'b1;
 //********************************************************************************
 // Slave multiplexer module:
@@ -89,15 +76,15 @@ cmsdk_ahb_slave_mux  #(
 ) u_ahb_slave_mux (
  .HCLK        (HCLK),
  .HRESETn     (HRESETn),
-  .HREADY      (hready),
+  .HREADY      (HREADYS),
-  .HSEL0       (hsel0),      // Input Port 0
+  .HSEL0       (HSEL0),      // Input Port 0
-  .HREADYOUT0  (hreadyout0),
+  .HREADYOUT0  (HREADYOUT0),
-  .HRESP0      (hresp0),
+  .HRESP0      (HRESP0),
-  .HRDATA0     (hrdata0),
+  .HRDATA0     (HRDATA0),
-  .HSEL1       (hsel1),      // Input Port 1
+  .HSEL1       (HSEL1),      // Input Port 1
-  .HREADYOUT1  (hreadyout1),
+  .HREADYOUT1  (HREADYOUT1),
-  .HRESP1      (hresp1),
+  .HRESP1      (HRESP1),
-  .HRDATA1     (hrdata1),
+  .HRDATA1     (HRDATA1),
  .HSEL2       (1'b0),      // Input Port 2
  .HREADYOUT2  (),
  .HRESP2      (),
@@ -131,32 +118,32 @@ cmsdk_ahb_slave_mux  #(
  .HRESP9      (),
  .HRDATA9     (),
-  .HREADYOUT   (hready),     // Outputs
+  .HREADYOUT   (HREADYOUTS),     // Outputs
-  .HRESP       (hresp),
+  .HRESP       (HRESPS),
-  .HRDATA      (hrdata)
+  .HRDATA      (HRDATAS)
  );
 //********************************************************************************
 // Slave module 1: example AHB slave module
 //********************************************************************************
-  wrapper_sha256_hashing_stream #(ADDRWIDTH
+  wrapper_sha256_hashing_stream #(ACCEL_ADDRWIDTH
  ) accelerator (
  .HCLK        (HCLK),
  .HRESETn     (HRESETn),
  //  Input slave port: 32 bit data bus interface
-  .HSELS       (hsel0),
+  .HSELS       (HSEL0),
-  .HADDRS      (haddr[ADDRWIDTH-1:0]),
+  .HADDRS      (HADDRS[ACCEL_ADDRWIDTH-1:0]),
-  .HTRANSS     (htrans),
+  .HTRANSS     (HTRANSS),
-  .HSIZES      (hsize),
+  .HSIZES      (HSIZES),
-  .HWRITES     (hwrite),
+  .HWRITES     (HWRITES),
-  .HREADYS     (hready),
+  .HREADYS     (HREADYS),
-  .HWDATAS     (hwdata),
+  .HWDATAS     (HWDATAS),
-  .HREADYOUTS  (hreadyout0),
+  .HREADYOUTS  (HREADYOUT0),
-  .HRESPS      (hresp0),
+  .HRESPS      (HRESP0),
-  .HRDATAS     (hrdata0)
+  .HRDATAS     (HRDATA0)
  );
@@ -167,13 +154,13 @@ cmsdk_ahb_slave_mux  #(
 cmsdk_ahb_default_slave  u_ahb_default_slave(
  .HCLK         (HCLK),
  .HRESETn      (HRESETn),
-  .HSEL         (hsel1),
+  .HSEL         (HSEL1),
-  .HTRANS       (htrans),
+  .HTRANS       (HTRANSS),
-  .HREADY       (hready),
+  .HREADY       (HREADYS),
-  .HREADYOUT    (hreadyout1),
+  .HREADYOUT    (HREADYOUT1),
-  .HRESP        (hresp1)
+  .HRESP        (HRESPS)
  );
- assign hrdata1 = {32{1'b0}}; // Default slave don't have data
+ assign HRDATA1 = {32{1'b0}}; // Default slave don't have data
 endmodule