From 492dddbbd3dfe33a834f24e8f0bf9e9f2c54179c Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Mon, 27 Feb 2023 13:09:23 +0000
Subject: [PATCH] FIxed wiring issues with nanosoc expansion region

---
 Cortex-M0/nanosoc/systems/mcu/rtl_sim/adp.cmd | 501 +++++++++++++++++-
 .../systems/mcu/verilog/nanosoc_chip.v        |   2 +-
 .../nanosoc/systems/mcu/verilog/nanosoc_exp.v |  97 ++--
 3 files changed, 524 insertions(+), 76 deletions(-)

diff --git a/Cortex-M0/nanosoc/systems/mcu/rtl_sim/adp.cmd b/Cortex-M0/nanosoc/systems/mcu/rtl_sim/adp.cmd
index d0b75b3..fc9af25 100644
--- a/Cortex-M0/nanosoc/systems/mcu/rtl_sim/adp.cmd
+++ b/Cortex-M0/nanosoc/systems/mcu/rtl_sim/adp.cmd
@@ -5,25 +5,486 @@ R
 A
 A
 A 
-a 10000000
-r
-r
-a 20000000
-r
-r
-a 30000000
-r
-r
-a 40006000
-r
-r
-r
-r
-a 30000200
-z 400
-A
-C 201
-
+a  0x600107c0
+w  0x94748770
+a  0x600107c4
+w  0x0e3109cc
+a  0x600107c8
+w  0xc4411b41
+a  0x600107cc
+w  0x5349fe99
+a  0x600107d0
+w  0xbc3bdfc1
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+w  0xdeb5cb2a
+a  0x600107d8
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+w  0x1761b000
+a  0x600107e0
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+a  0x600107e4
+w  0xeab53b7e
+a  0x600107e8
+w  0x81152f06
+a  0x600107ec
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+a  0x600107fc
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+w  0xebedc242
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+w  0x1498319a
+a  0x600107f0
+w  0xb1f10e58
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+w  0x8d03ecb0
+a  0x600107f8
+w  0x4408ab12
+a  0x600107fc
+w  0xcabcc637
+a  0x60010fe0
+r  0x090f1978
+a  0x60010fe4
+r  0xcc432473
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+r  0x7af5e3f6
+a  0x60010fec
+r  0x093d866f
+a  0x60010ff0
+r  0x80069d04
+a  0x60010ff4
+r  0x9fe9980d
+a  0x60010ff8
+r  0xb8a4b430
+a  0x60010ffc
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   A
 X
-!
+!
\ No newline at end of file
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip.v b/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip.v
index 53fa690..295c7e5 100644
--- a/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip.v
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip.v
@@ -961,7 +961,7 @@ nanosoc_exp #(.ADDRWIDTH(29)
   .HADDRS      (HADDR_exp[28:0]),
   .HTRANSS     (HTRANS_exp),
   .HSIZES      (HSIZE_exp),
-  .HWRITES     (HWDATA_exp),
+  .HWRITES     (HWRITE_exp),
   .HREADYS     (HREADYMUX_exp),
   .HWDATAS     (HWDATA_exp),
 
diff --git a/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_exp.v b/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_exp.v
index 448b150..23fb4d6 100644
--- a/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_exp.v
+++ b/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_exp.v
@@ -12,7 +12,8 @@
 `include "cmsdk_ahb_slave_mux.v"
 
 module nanosoc_exp #(
-    parameter    ADDRWIDTH=29 // Region Address Width
+    parameter    ADDRWIDTH=29, // Region Address Width
+    parameter    ACCEL_ADDRWIDTH=12 // Region Address Width
   )(
     input  wire                  HCLK,       // Clock
     input  wire                  HRESETn,    // Reset
@@ -35,31 +36,17 @@ module nanosoc_exp #(
 // Internal Wires
 //********************************************************************************
 
-// AHB Lite BUS SIGNALS
-wire             hready;
-wire             hresp;
-wire [31:0]      hrdata;
-
-wire [1:0]       htrans;
-wire [2:0]       hburst;
-wire [3:0]       hprot;
-wire [2:0]       hsize;
-wire             hwrite;
-wire             hmastlock;
-wire [31:0]      haddr;
-wire [31:0]      hwdata;
-
 // Accelerator AHB Signals
-wire             hsel0;
-wire             hreadyout0;
-wire             hresp0;
-wire [31:0]      hrdata0;
+wire             HSEL0;
+wire             HREADYOUT0;
+wire             HRESP0;
+wire [31:0]      HRDATA0;
 
 // Default Slave AHB Signals
-wire             hsel1;
-wire             hreadyout1;
-wire             hresp1;
-wire [31:0]      hrdata1;
+wire             HSEL1;
+wire             HREADYOUT1;
+wire             HRESP1;
+wire [31:0]      HRDATA1;
 
 //********************************************************************************
 // Address decoder, need to be changed for other configuration
@@ -67,8 +54,8 @@ wire [31:0]      hrdata1;
 // 0x00010000 - 0x00010FFF : HSEL #0 - Hash Accelerator
 // Other addresses         : HSEL #1 - Default slave
 
-  assign hsel0 = (haddr[ADDRWIDTH-1:12] == 'h00010) ? 1'b1:1'b0;
-  assign hsel1 = hsel0 ? 1'b0:1'b1;
+  assign HSEL0 = (HADDRS[ADDRWIDTH-1:12] == 'h00010) ? 1'b1:1'b0;
+  assign HSEL1 = HSEL0 ? 1'b0:1'b1;
 
 //********************************************************************************
 // Slave multiplexer module:
@@ -89,15 +76,15 @@ cmsdk_ahb_slave_mux  #(
  ) u_ahb_slave_mux (
   .HCLK        (HCLK),
   .HRESETn     (HRESETn),
-  .HREADY      (hready),
-  .HSEL0       (hsel0),      // Input Port 0
-  .HREADYOUT0  (hreadyout0),
-  .HRESP0      (hresp0),
-  .HRDATA0     (hrdata0),
-  .HSEL1       (hsel1),      // Input Port 1
-  .HREADYOUT1  (hreadyout1),
-  .HRESP1      (hresp1),
-  .HRDATA1     (hrdata1),
+  .HREADY      (HREADYS),
+  .HSEL0       (HSEL0),      // Input Port 0
+  .HREADYOUT0  (HREADYOUT0),
+  .HRESP0      (HRESP0),
+  .HRDATA0     (HRDATA0),
+  .HSEL1       (HSEL1),      // Input Port 1
+  .HREADYOUT1  (HREADYOUT1),
+  .HRESP1      (HRESP1),
+  .HRDATA1     (HRDATA1),
   .HSEL2       (1'b0),      // Input Port 2
   .HREADYOUT2  (),
   .HRESP2      (),
@@ -131,32 +118,32 @@ cmsdk_ahb_slave_mux  #(
   .HRESP9      (),
   .HRDATA9     (),
 
-  .HREADYOUT   (hready),     // Outputs
-  .HRESP       (hresp),
-  .HRDATA      (hrdata)
+  .HREADYOUT   (HREADYOUTS),     // Outputs
+  .HRESP       (HRESPS),
+  .HRDATA      (HRDATAS)
   );
 
 
 //********************************************************************************
 // Slave module 1: example AHB slave module
 //********************************************************************************
-  wrapper_sha256_hashing_stream #(ADDRWIDTH
+  wrapper_sha256_hashing_stream #(ACCEL_ADDRWIDTH
   ) accelerator (
   .HCLK        (HCLK),
   .HRESETn     (HRESETn),
 
   //  Input slave port: 32 bit data bus interface
-  .HSELS       (hsel0),
-  .HADDRS      (haddr[ADDRWIDTH-1:0]),
-  .HTRANSS     (htrans),
-  .HSIZES      (hsize),
-  .HWRITES     (hwrite),
-  .HREADYS     (hready),
-  .HWDATAS     (hwdata),
-
-  .HREADYOUTS  (hreadyout0),
-  .HRESPS      (hresp0),
-  .HRDATAS     (hrdata0)
+  .HSELS       (HSEL0),
+  .HADDRS      (HADDRS[ACCEL_ADDRWIDTH-1:0]),
+  .HTRANSS     (HTRANSS),
+  .HSIZES      (HSIZES),
+  .HWRITES     (HWRITES),
+  .HREADYS     (HREADYS),
+  .HWDATAS     (HWDATAS),
+
+  .HREADYOUTS  (HREADYOUT0),
+  .HRESPS      (HRESP0),
+  .HRDATAS     (HRDATA0)
 
   );
 
@@ -167,13 +154,13 @@ cmsdk_ahb_slave_mux  #(
  cmsdk_ahb_default_slave  u_ahb_default_slave(
   .HCLK         (HCLK),
   .HRESETn      (HRESETn),
-  .HSEL         (hsel1),
-  .HTRANS       (htrans),
-  .HREADY       (hready),
-  .HREADYOUT    (hreadyout1),
-  .HRESP        (hresp1)
+  .HSEL         (HSEL1),
+  .HTRANS       (HTRANSS),
+  .HREADY       (HREADYS),
+  .HREADYOUT    (HREADYOUT1),
+  .HRESP        (HRESPS)
   );
 
- assign hrdata1 = {32{1'b0}}; // Default slave don't have data
+ assign HRDATA1 = {32{1'b0}}; // Default slave don't have data
 
 endmodule
-- 
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