Skip to content
GitLab
Explore
Sign in
Register
Primary navigation
Search or go to…
Project
NanoSoC Tech
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Wiki
Jira
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Deploy
Releases
Package registry
Model registry
Operate
Terraform modules
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
Repository analytics
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
Community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
SoCLabs
NanoSoC Tech
Commits
35345e85
Commit
35345e85
authored
1 year ago
by
dam1n19
Browse files
Options
Downloads
Patches
Plain Diff
Updated Quickstart defines and Fixed ADP read in bug
parent
ef9c616b
No related branches found
No related tags found
No related merge requests found
Changes
3
Hide whitespace changes
Inline
Side-by-side
Showing
3 changed files
flist/nanosoc_qs.flist
+1
-4
1 addition, 4 deletions
flist/nanosoc_qs.flist
fpga/makefile
+1
-1
1 addition, 1 deletion
fpga/makefile
makefile
+11
-6
11 additions, 6 deletions
makefile
with
13 additions
and
11 deletions
flist/nanosoc_qs.flist
+
1
−
4
View file @
35345e85
...
...
@@ -27,7 +27,4 @@
-f $(SOCLABS_SLCOREM0_TECH_DIR)/flist/slcorem0_qs.flist
// Debug IP
-f $(SOCLABS_SOCDEBUG_TECH_DIR)/flist/socdebug.flist
// DMA Subystem
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_subsystems/dma/no_dmac/verilog/nanosoc_ss_dma.v
\ No newline at end of file
-f $(SOCLABS_SOCDEBUG_TECH_DIR)/flist/socdebug.flist
\ No newline at end of file
This diff is collapsed.
Click to expand it.
fpga/makefile
+
1
−
1
View file @
35345e85
...
...
@@ -24,6 +24,7 @@ ifeq ($(QUICKSTART),yes)
DESIGN_VC
?=
$(
SOCLABS_PROJECT_DIR
)
/flist/project/top_qs.flist
else
DESIGN_VC
?=
$(
SOCLABS_PROJECT_DIR
)
/flist/project/top.flist
NANOSOC_DEFINES
+=
DMAC_0_PL230
endif
# Top-level of RTL design to Implement
...
...
@@ -76,7 +77,6 @@ endif
# Defines to pass to filelist compile
NANOSOC_DEFINES
+=
$(
ACCELERATOR_SUBSYSTEM
)
NANOSOC_DEFINES
+=
DMAC_0_PL230
# Compile Testcodes and Bootrom
...
...
This diff is collapsed.
Click to expand it.
makefile
+
11
−
6
View file @
35345e85
...
...
@@ -69,11 +69,17 @@ TOOL_CHAIN = ds5
CPU_PRODUCT
?=
CORTEX_M0
DMA_PRODUCT
?=
DMA_230
# Directory to put simulation files
SIM_TOP_DIR
?=
$(
SOCLABS_PROJECT_DIR
)
/simulate/sim
SIM_DIR
=
$(
SIM_TOP_DIR
)
/
$(
TESTNAME
)
# ADP command File
# Defaultly set to demo adp command file
DEFAULT_ADP_FILE
=
$(
SIM_DIR
)
/adp.cmd
ADP_FILE
?=
$(
DEFAULT_ADP_FILE
)
ADP_PATH
:=
$(
shell
realpath
$(
ADP_FILE
))
ADP_FILE
?=
$(
DEFAULT_ADP_FILE
)
ADP_PATH
:=
$(
shell
realpath
$(
ADP_FILE
))
ADP_OPTIONS
:=
-define
ADP_FILE
=
\"
$(
ADP_PATH
)
\"
# Bootrom Parameters:
...
...
@@ -94,7 +100,6 @@ ifeq ($(ACCELERATOR),yes)
NANOSOC_DEFINES
+=
ACCELERATOR_SUBSYSTEM
endif
NANOSOC_DEFINES
+=
DMAC_0_PL230
NANOSOC_DEFINES
+=
IMEM_0_RAM_PRELOAD
# Is the Arm QuickStart being used?
...
...
@@ -113,6 +118,7 @@ else
ARM_CORSTONE_101_DIR
?=
$(
ARM_IP_LIBRARY_PATH
)
/latest/Corstone-101/logical
ARM_CORTEX_M0_DIR
?=
$(
ARM_IP_LIBRARY_PATH
)
/latest/Cortex-M0/logical
TB_TOP
?=
nanosoc_tb
NANOSOC_DEFINES
+=
DMAC_0_PL230
endif
export
ARM_CORTEX_M0_DIR
...
...
@@ -121,10 +127,7 @@ export ARM_CORSTONE_101_DIR
# Simulator type (mti/vcs/xm)
SIMULATOR
=
mti
# Directory to put simulation files
SIM_TOP_DIR
?=
$(
SOCLABS_PROJECT_DIR
)
/simulate/sim
SIM_DIR
=
$(
SIM_TOP_DIR
)
/
$(
TESTNAME
)
LINT_DIR
=
$(
SOCLABS_PROJECT_DIR
)
/lint/nanosoc
LINT_INFO_DIR
=
$(
SOCLABS_NANOSOC_TECH_DIR
)
/hal
...
...
@@ -306,6 +309,8 @@ sim_xm : code compile_xm
compile_mti
:
bootrom defs_gen
@
echo
ADP_FILE
@
echo
$(
ADP_OPTIONS
)
@
echo
$(
ADP_FILE
)
@
echo
$(
ADP_PATH
)
cd
$(
SIM_DIR
)
@
if
[
-d
work
]
;
then
\
true
;
\
...
...
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment