diff --git a/flist/nanosoc_qs.flist b/flist/nanosoc_qs.flist
index f6f7810e919fcb2caf15565e8e259cb81258be88..2d33e273a2c21fc2c9af33879b9f40890a5dc5cb 100644
--- a/flist/nanosoc_qs.flist
+++ b/flist/nanosoc_qs.flist
@@ -27,7 +27,4 @@
 -f $(SOCLABS_SLCOREM0_TECH_DIR)/flist/slcorem0_qs.flist
 
 // Debug IP
--f $(SOCLABS_SOCDEBUG_TECH_DIR)/flist/socdebug.flist
-
-// DMA Subystem
-$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_subsystems/dma/no_dmac/verilog/nanosoc_ss_dma.v
\ No newline at end of file
+-f $(SOCLABS_SOCDEBUG_TECH_DIR)/flist/socdebug.flist
\ No newline at end of file
diff --git a/fpga/makefile b/fpga/makefile
index 71be7bce379cfb2c1382ca3d57857c4267510ce8..fb36daab82f687a4674d35fc7bb6b31b638e8b29 100644
--- a/fpga/makefile
+++ b/fpga/makefile
@@ -24,6 +24,7 @@ ifeq ($(QUICKSTART),yes)
 	DESIGN_VC            ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_qs.flist
 else
 	DESIGN_VC            ?= $(SOCLABS_PROJECT_DIR)/flist/project/top.flist
+	NANOSOC_DEFINES      += DMAC_0_PL230
 endif
 
 # Top-level of RTL design to Implement
@@ -76,7 +77,6 @@ endif
 
 # Defines to pass to filelist compile
 NANOSOC_DEFINES += $(ACCELERATOR_SUBSYSTEM)
-NANOSOC_DEFINES += DMAC_0_PL230
 
 
 # Compile Testcodes and Bootrom
diff --git a/makefile b/makefile
index 2d6dd6307e1137136be19af9eb704ce786157ce7..d39e5647194c99e53802e63ad0c4f1e3625f756c 100644
--- a/makefile
+++ b/makefile
@@ -69,11 +69,17 @@ TOOL_CHAIN = ds5
 CPU_PRODUCT ?= CORTEX_M0
 DMA_PRODUCT ?= DMA_230
 
+
+# Directory to put simulation files
+SIM_TOP_DIR ?= $(SOCLABS_PROJECT_DIR)/simulate/sim
+
+SIM_DIR = $(SIM_TOP_DIR)/$(TESTNAME)
+
 # ADP command File
 # Defaultly set to demo adp command file
 DEFAULT_ADP_FILE = $(SIM_DIR)/adp.cmd
-ADP_FILE ?= $(DEFAULT_ADP_FILE)
-ADP_PATH := $(shell realpath $(ADP_FILE))
+ADP_FILE    ?= $(DEFAULT_ADP_FILE)
+ADP_PATH    :=  $(shell realpath $(ADP_FILE))
 ADP_OPTIONS := -define ADP_FILE=\"$(ADP_PATH)\"
 
 # Bootrom Parameters:
@@ -94,7 +100,6 @@ ifeq ($(ACCELERATOR),yes)
 	NANOSOC_DEFINES += ACCELERATOR_SUBSYSTEM
 endif
 
-NANOSOC_DEFINES += DMAC_0_PL230
 NANOSOC_DEFINES += IMEM_0_RAM_PRELOAD
 
 # Is the Arm QuickStart being used?
@@ -113,6 +118,7 @@ else
 	ARM_CORSTONE_101_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical
 	ARM_CORTEX_M0_DIR    ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical
 	TB_TOP               ?= nanosoc_tb
+	NANOSOC_DEFINES      += DMAC_0_PL230
 endif
 
 export ARM_CORTEX_M0_DIR
@@ -121,10 +127,7 @@ export ARM_CORSTONE_101_DIR
 # Simulator type (mti/vcs/xm)
 SIMULATOR   = mti
 
-# Directory to put simulation files
-SIM_TOP_DIR ?= $(SOCLABS_PROJECT_DIR)/simulate/sim
 
-SIM_DIR = $(SIM_TOP_DIR)/$(TESTNAME)
 
 LINT_DIR = $(SOCLABS_PROJECT_DIR)/lint/nanosoc
 LINT_INFO_DIR = $(SOCLABS_NANOSOC_TECH_DIR)/hal
@@ -306,6 +309,8 @@ sim_xm : code compile_xm
 compile_mti : bootrom defs_gen
 	@echo ADP_FILE
 	@echo $(ADP_OPTIONS)
+	@echo $(ADP_FILE)
+	@echo $(ADP_PATH)
 	cd $(SIM_DIR)
 	@if [ -d work ] ; then \
           true ; \