Split ASIC flow for 28 44 and 60 pin

.gitignore

ASIC/28pin/Cadence/cpf/nanosoc.cpf

ASIC/28pin/Cadence/cpf/nanosoc_imp.cpf

ASIC/28pin/Cadence/scripts/clock_tree_synthesis.tcl

ASIC/28pin/Cadence/scripts/design_import.tcl

ASIC/28pin/Cadence/scripts/genus.tcl

ASIC/28pin/Cadence/scripts/io_plan.tcl

ASIC/28pin/Cadence/scripts/lec.dofile

ASIC/28pin/Cadence/scripts/nanosoc.mmmc

ASIC/28pin/Cadence/scripts/nanosoc_io_plan.io

ASIC/28pin/Cadence/scripts/place.tcl

ASIC/28pin/Cadence/scripts/place_macros.tcl

ASIC/28pin/Cadence/scripts/pnr_flow.tcl

ASIC/28pin/Cadence/scripts/power_plan.tcl

ASIC/28pin/Cadence/scripts/power_route.tcl

ASIC/28pin/Cadence/scripts/route.tcl

ASIC/28pin/Cadence/scripts/voltus_pg.tcl

ASIC/28pin/Synopsys/scripts/fm_shell.tcl

ASIC/28pin/Synopsys/scripts/place_memories.tcl

ASIC/28pin/Synopsys/scripts/place_pins.tcl