diff --git a/.gitignore b/.gitignore
index 513a93cfdd3c5fc9fd416d549fb65639d9a8eb33..65b4d8bc0af7b79ef079b88f58cfb0b68098d4ed 100644
--- a/.gitignore
+++ b/.gitignore
@@ -10,17 +10,18 @@ ASIC/*.mr
ASIC/*.pvk
ASIC/alib-52
ASIC/WORK/*
-ASIC/Cadence/Genus/fv
-ASIC/Cadence/Genus/*.rpt
-ASIC/Cadence/Genus/*.tstamp
-ASIC/Cadence/Innovus/.cadence
-ASIC/Cadence/Innovus/nanosoc_chip_pads
-ASIC/Cadence/Innovus/timingReports
-ASIC/Cadence/Innovus/*.db*
-ASIC/Cadence/Innovus/*.rpt
-ASIC/Cadence/Innovus/*.checkFPlan
-ASIC/Cadence/Innovus/*.ptiavg
-ASIC/Cadence/Innovus/*.ptifiles
+ASIC/*/Cadence/scripts/fv
+ASIC/*/Cadence/scripts/*.rpt
+ASIC/*/Cadence/scripts/*.tstamp
+
+ASIC/*/Cadence/scripts/.cadence
+ASIC/*/Cadence/scripts/nanosoc_chip_pads
+ASIC/*/Cadence/scripts/timingReports
+ASIC/*/Cadence/scripts/*.db*
+ASIC/*/Cadence/scripts/*.rpt
+ASIC/*/Cadence/scripts/*.checkFPlan
+ASIC/*/Cadence/scripts/*.ptiavg
+ASIC/*/Cadence/scripts/*.ptifiles
ASIC/Synopsys/Formality/FM_INFO/*
ASIC/Synopsys/ICC2/CLIBs
ASIC/Synopsys/ICC2/PreFrameCheck
diff --git a/ASIC/Cadence/Genus/nanosoc.cpf b/ASIC/28pin/Cadence/cpf/nanosoc.cpf
similarity index 100%
rename from ASIC/Cadence/Genus/nanosoc.cpf
rename to ASIC/28pin/Cadence/cpf/nanosoc.cpf
diff --git a/ASIC/28pin/Cadence/cpf/nanosoc_imp.cpf b/ASIC/28pin/Cadence/cpf/nanosoc_imp.cpf
new file mode 100644
index 0000000000000000000000000000000000000000..e0869e5a6bcf67fcaf3452a006aac49192bfcc45
--- /dev/null
+++ b/ASIC/28pin/Cadence/cpf/nanosoc_imp.cpf
@@ -0,0 +1,19 @@
+set_cpf_version 1.1
+
+set_design nanosoc_chip_pads
+create_power_domain -name TOP -default
+create_power_domain -name ACCEL -instances u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator
+
+create_nominal_condition -name nom -voltage 1.08
+
+create_power_mode -name PM -domain_conditions {TOP@nom ACCEL@nom} -default
+
+create_ground_nets -nets VSS
+create_power_nets -nets VDD
+create_power_nets -nets VDDACC
+
+update_power_domain -name TOP -primary_power_net VDD -primary_ground_net VSS
+update_power_domain -name ACCEL -primary_power_net VDDACC -primary_ground_net VSS
+
+
+end_design
\ No newline at end of file
diff --git a/ASIC/Cadence/Innovus/clock_tree_synthesis.tcl b/ASIC/28pin/Cadence/scripts/clock_tree_synthesis.tcl
similarity index 100%
rename from ASIC/Cadence/Innovus/clock_tree_synthesis.tcl
rename to ASIC/28pin/Cadence/scripts/clock_tree_synthesis.tcl
diff --git a/ASIC/28pin/Cadence/scripts/design_import.tcl b/ASIC/28pin/Cadence/scripts/design_import.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..7ab8211d6563e0db76825bed56d1362f218ebfff
--- /dev/null
+++ b/ASIC/28pin/Cadence/scripts/design_import.tcl
@@ -0,0 +1,49 @@
+#########################################
+# File : Design Import Logic
+# Date : 22nd May 2022
+# Author : Srimanth Tenneti
+# Description : MMMC + Design Import
+#########################################
+
+### Settting PG Nets
+set_db init_power_nets {VDD VDDIO VDDACC}
+set_db init_ground_nets {VSS VSSIO}
+
+### Processing MMMC
+read_mmmc nanosoc.mmmc
+
+# Set library paths
+# !! EDIT THIS TO YOUR PATHS IN YOUR ENVIRONMENT
+set TECH_LEF $::env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/lef/1p9m_6x2z/sc9_tech.lef
+set BASE_LEF $::env(PHYS_IP)/arm/tsmc/cln65lp/sc9_base_rvt/r0p0/lef/sc9_cln65lp_base_rvt.lef
+set IO_PAD_LEF /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Backend/lef/tpbn65v_9lm.lef
+set IO_PAD_DRIVER_LEF /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Backend/lef/tpdn65lpnv2od3_9lm.lef
+
+
+# !! THESE SHOULD BE CORRECT FOR ANY ENVIRONMENT AS THEY ARE GENERATED BY MAKEFILE
+set RF_16K_LEF $::env(SOCLABS_PROJECT_DIR)/memories/rf_16k/rf_16k.lef
+set RF_08K_LEF $::env(SOCLABS_PROJECT_DIR)/memories/rf_08k/rf_08k.lef
+set ROM_LEF $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via.lef
+
+### Reading LEFs
+read_physical -lef [list ${TECH_LEF} ${BASE_LEF} ${IO_PAD_LEF} ${IO_PAD_DRIVER_LEF} ${RF_16K_LEF} ${RF_08K_LEF} ${ROM_LEF}]
+
+### Reading Netlist
+read_netlist $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_28pin.v
+
+### Read DEF scan chain
+#read_def $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_28pin.def
+
+### Initializing the Design
+init_design
+
+### Adjusting the GUI
+gui_fit
+
+ungroup u_nanosoc_chip_u_system
+
+create_floorplan -core_margins_by die -flip s -site sc9_cln65lp -die_size 1000.0 1000.0 135.0 135.0 135.0 135.0
+
+read_power_intent -cpf ../cpf/nanosoc_imp.cpf
+
+
diff --git a/ASIC/28pin/Cadence/scripts/genus.tcl b/ASIC/28pin/Cadence/scripts/genus.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..ceef0ea4050c370d3ff8bd84952b25002c4bb369
--- /dev/null
+++ b/ASIC/28pin/Cadence/scripts/genus.tcl
@@ -0,0 +1,72 @@
+set_db init_lib_search_path "/home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a/ $::env(PHYS_IP)/arm/tsmc/cln65lp/sc9_base_rvt/r0p0/lib/ $::env(SOCLABS_PROJECT_DIR)/memories/rf_08k/ $::env(SOCLABS_PROJECT_DIR)/memories/rf_16k/ $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/"
+set BASE_LIB sc9_cln65lp_base_rvt_ss_typical_max_1p08v_125c.lib
+set RF_16K_LIB rf_16k_ss_1p08v_1p08v_125c.lib
+set RF_08K_LIB rf_08k_ss_1p08v_1p08v_125c.lib
+set ROM_LIB rom_via_ss_1p08v_1p08v_125c.lib
+set IO_PAD_DRIVER tpdn65lpnv2od3bc.lib
+create_library_domain domain1
+set_db [get_db library_domains domain1] .library "$BASE_LIB $RF_16K_LIB $RF_08K_LIB $ROM_LIB $IO_PAD_DRIVER"
+
+read_power_intent -cpf -module nanosoc_chip_pads ../cpf/nanosoc.cpf
+
+source $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/genus_flist.tcl
+elaborate nanosoc_chip_pads
+
+apply_power_intent
+check_library > lib_check.log
+
+check_cpf
+
+commit_power_intent
+check_power_structure -license lpgxl
+
+read_sdc $::env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/constraints.sdc
+
+#set_db dft_scan_style muxed_scan
+#set_db design:nanosoc_chip_pads .dft_min_number_of_scan_chains 1
+
+#read_dft_abstract_model nanosoc_dft_abstract_model
+#define_test_signal -name TEST -active high -function test_mode -index 0 TEST
+#define_test_signal -name SWDCK -active high -function scan_clock -index 0 SWDCK
+#define_test_signal -name NRST -active low -function async_set_reset -index 0 NRST
+#define_test_signal -name SWDIO -active high -function shift_enable -default -index 0 SWDIO
+#define_test_signal -name CLK -active high -function test_clock -index 0 CLK
+
+#define_scan_chain -name chain_ACCEL -sdi DFT_SDI_1 -sdo DFT_SDO_1 -shared_output
+#define_scan_chain -name chain_TOP -sdi DFT_SDI_2 -sdo DFT_SDO_2 -shared_output
+
+
+#check_dft_rules
+#fix_dft_violations -test_control TEST -async_reset -add_observe_scan -scan_clock_pin SWDCK
+
+
+set_db syn_generic_effort high
+set_db syn_map_effort high
+
+syn_generic
+syn_map
+
+#convert_to_scan
+
+#connect_scan_chains -chains chain_ACCEL -power_domain ACCEL -incremental
+#connect_scan_chains -chains chain_TOP -power_domain TOP -incremental
+
+syn_opt
+
+report_area > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/syn_nanosoc_area_28pin.rep
+report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/syn_nanosoc_timing_28pin.rep
+report_gates > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/syn_nanosoc_gates_28pin.rep
+report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/syn_nanosoc_power_28pin.rep
+
+write_hdl > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_28pin.v
+write_hdl -pg > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_28pins.vp
+
+#report_scan_chains > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_chains.rep
+#report_scan_setup > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_setup.rep
+#report_scan_registers > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_registers.rep
+#write_dft_abstract_model > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_dft_abstract_model
+
+#write_dft_atpg_other_vendor -mentor > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_atpg
+
+#write_scandef > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads.def
+
diff --git a/ASIC/28pin/Cadence/scripts/io_plan.tcl b/ASIC/28pin/Cadence/scripts/io_plan.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..48b4a5dfce8ad92005e7c61ddbd460a1d560c2c0
--- /dev/null
+++ b/ASIC/28pin/Cadence/scripts/io_plan.tcl
@@ -0,0 +1,57 @@
+#-----------------------------------------------------------------------------
+# NanoSoC IO plan for PnR in cadence Innovus
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# Daniel Newbrook (d.newbrook@soton.ac.uk)
+#
+# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+
+delete_io_fillers -cell PCORNER
+delete_io_fillers -cell PFILLER20
+delete_io_fillers -cell PFILLER10
+delete_io_fillers -cell PFILLER5
+delete_io_fillers -cell PFILLER1
+delete_io_fillers -cell PFILLER05
+delete_io_fillers -cell PFILLER0005
+
+
+read_io_file nanosoc_io_plan.io
+
+add_io_fillers -cells PCORNER -prefix CORNER -side n -from -300 -to 300
+add_io_fillers -cells PCORNER -prefix CORNER -side e -from 880 -to 1200
+add_io_fillers -cells PCORNER -prefix CORNER -side s -from 880 -to 1200
+add_io_fillers -cells PCORNER -prefix CORNER -side w -from -300 -to 300
+
+add_io_fillers -cells PFILLER20 -prefix FILLER -side n
+add_io_fillers -cells PFILLER20 -prefix FILLER -side e
+add_io_fillers -cells PFILLER20 -prefix FILLER -side s
+add_io_fillers -cells PFILLER20 -prefix FILLER -side w
+
+add_io_fillers -cells PFILLER10 -prefix FILLER -side n
+add_io_fillers -cells PFILLER10 -prefix FILLER -side e
+add_io_fillers -cells PFILLER10 -prefix FILLER -side s
+add_io_fillers -cells PFILLER10 -prefix FILLER -side w
+
+add_io_fillers -cells PFILLER5 -prefix FILLER -side n
+add_io_fillers -cells PFILLER5 -prefix FILLER -side e
+add_io_fillers -cells PFILLER5 -prefix FILLER -side s
+add_io_fillers -cells PFILLER5 -prefix FILLER -side w
+
+add_io_fillers -cells PFILLER1 -prefix FILLER -side n
+add_io_fillers -cells PFILLER1 -prefix FILLER -side e
+add_io_fillers -cells PFILLER1 -prefix FILLER -side s
+add_io_fillers -cells PFILLER1 -prefix FILLER -side w
+
+add_io_fillers -cells PFILLER05 -prefix FILLER -side n
+add_io_fillers -cells PFILLER05 -prefix FILLER -side e
+add_io_fillers -cells PFILLER05 -prefix FILLER -side s
+add_io_fillers -cells PFILLER05 -prefix FILLER -side w
+
+add_io_fillers -cells PFILLER0005 -prefix FILLER -side n
+add_io_fillers -cells PFILLER0005 -prefix FILLER -side e
+add_io_fillers -cells PFILLER0005 -prefix FILLER -side s
+add_io_fillers -cells PFILLER0005 -prefix FILLER -side w
\ No newline at end of file
diff --git a/ASIC/28pin/Cadence/scripts/lec.dofile b/ASIC/28pin/Cadence/scripts/lec.dofile
new file mode 100644
index 0000000000000000000000000000000000000000..a67fb237af04e071b15799c92b25e8b6c4baf73b
--- /dev/null
+++ b/ASIC/28pin/Cadence/scripts/lec.dofile
@@ -0,0 +1,39 @@
+read library $SOCLABS_PROJECT_DIR/memories/rf/rf_sp_hdf_ss_1p08v_1p08v_125c.lib -liberty -golden
+read library $SOCLABS_PROJECT_DIR/memories/bootrom/rom_via_ss_1p08v_1p08v_125c.lib -liberty -golden -append
+
+
+add search path $SOCLABS_PROJECT_DIR/system/src/defines
+add search path "[get_db hdl_search_path] $ACCELERATOR_DIR/src/rtl"
+read library -verilog -golden -append -define POWER_PINS $SOCLABS_PROJECT_DIR/system/src/defines/gen_defines.v
+read library -golden -append -define POWER_PINS -sv09 $SOCLABS_WRAPPER_TECH_DIR/hdl/src/wrapper_ahb_packet_constructor.sv $SOCLABS_WRAPPER_TECH_DIR/hdl/src/wrapper_ahb_packet_deconstructor.sv $SOCLABS_WRAPPER_TECH_DIR/hdl/src/wrapper_addr_calc.sv $SOCLABS_WRAPPER_TECH_DIR/hdl/src/wrapper_data_req.sv $SOCLABS_WRAPPER_TECH_DIR/hdl/src/wrapper_ahb_reg_interface.sv $SOCLABS_WRAPPER_TECH_DIR/hdl/src/wrapper_packet_construct.sv $SOCLABS_WRAPPER_TECH_DIR/hdl/src/wrapper_packet_deconstruct.sv $SOCLABS_WRAPPER_TECH_DIR/hdl/src/wrapper_req_ctrl_reg.sv $SOCLABS_WRAPPER_TECH_DIR/hdl/src/wrapper_dmac_req.sv $SOCLABS_WRAPPER_TECH_DIR/hdl/src/wrapper_valid_filter.sv
+read library -verilog -golden -append -define POWER_PINS $SOCLABS_PROJECT_DIR/system/src/accelerator_subsystem.v
+read library -golden -append -define POWER_PINS -sv09 $SOCLABS_PRIMITIVES_TECH_DIR/src/sv/fifo_vr.sv
+read library -verilog -golden -append -define POWER_PINS $SOCLABS_ASIC_LIB_TECH_DIR/sram/verilog/sl_ahb_sram.v $SOCLABS_ASIC_LIB_TECH_DIR/sram/verilog/sl_sram.v $SOCLABS_ASIC_LIB_TECH_DIR/rom/verilog/bootrom.v $SOCLABS_ASIC_LIB_TECH_DIR/pads/verilog/PAD_INOUT8MA_NOE.v $SOCLABS_ASIC_LIB_TECH_DIR/pads/verilog/PAD_VDDIO.v $SOCLABS_ASIC_LIB_TECH_DIR/pads/verilog/PAD_VSSIO.v $SOCLABS_ASIC_LIB_TECH_DIR/pads/verilog/PAD_VDDSOC.v $SOCLABS_ASIC_LIB_TECH_DIR/pads/verilog/PAD_VSS.v $SOCLABS_ASIC_LIB_TECH_DIR/sync/verilog/SYNCHRONIZER_EDGES.v
+read library -golden -append -define POWER_PINS -sv09 $SOCLABS_WRAPPER_TECH_DIR/hdl/src/wrapper_ahb_packet_constructor.sv $SOCLABS_WRAPPER_TECH_DIR/hdl/src/wrapper_ahb_packet_deconstructor.sv $SOCLABS_WRAPPER_TECH_DIR/hdl/src/wrapper_addr_calc.sv $SOCLABS_WRAPPER_TECH_DIR/hdl/src/wrapper_data_req.sv $SOCLABS_WRAPPER_TECH_DIR/hdl/src/wrapper_ahb_reg_interface.sv $SOCLABS_WRAPPER_TECH_DIR/hdl/src/wrapper_packet_construct.sv $SOCLABS_WRAPPER_TECH_DIR/hdl/src/wrapper_packet_deconstruct.sv $SOCLABS_WRAPPER_TECH_DIR/hdl/src/wrapper_req_ctrl_reg.sv $SOCLABS_WRAPPER_TECH_DIR/hdl/src/wrapper_dmac_req.sv $SOCLABS_WRAPPER_TECH_DIR/hdl/src/wrapper_valid_filter.sv
+add search path "[get_db hdl_search_path] $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog"
+add search path "[get_db hdl_search_path] $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog"
+add search path "[get_db hdl_search_path] $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/models/memories/"
+read library -verilog -golden -append -define POWER_PINS $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_apb_timer/verilog/cmsdk_apb_timer.v $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_frc.v $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers.v $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_apb_uart/verilog/cmsdk_apb_uart.v $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_frc.v $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog.v $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_apb_slave_mux/verilog/cmsdk_apb_slave_mux.v $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_apb_subsystem/verilog/cmsdk_apb_subsystem.v $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_apb_subsystem/verilog/cmsdk_apb_test_slave.v $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_apb_subsystem/verilog/cmsdk_irq_sync.v $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_ahb_slave_mux/verilog/cmsdk_ahb_slave_mux.v $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_ahb_default_slave/verilog/cmsdk_ahb_default_slave.v $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_ahb_gpio/verilog/cmsdk_ahb_gpio.v $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_ahb_gpio/verilog/cmsdk_ahb_to_iop.v $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_ahb_to_apb/verilog/cmsdk_ahb_to_apb.v $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_iop_gpio/verilog/cmsdk_iop_gpio.v $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/models/clkgate/cmsdk_clock_gate.v $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/models/memories/cmsdk_ahb_ram_beh.v $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/models/memories/cmsdk_ahb_ram.v $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/models/memories/cmsdk_ahb_rom.v $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/models/memories/cmsdk_fpga_rom.v
+read library -verilog2k -golden -append -define POWER_PINS $ARM_IP_LIBRARY_PATH/latest/Corstone-101/logical/cmsdk_ahb_to_sram/verilog/cmsdk_ahb_to_sram.v
+add search path "[get_db hdl_search_path] $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0_dap/verilog"
+add search path "[get_db hdl_search_path] $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/ualdis/verilog"
+read library -verilog -golden -append -define POWER_PINS $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0/verilog/cm0_core_alu.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0/verilog/cm0_core_ctl.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0/verilog/cm0_core_dec.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0/verilog/cm0_core_gpr.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0/verilog/cm0_core_mul.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0/verilog/cm0_core_pfu.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0/verilog/cm0_core_psr.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0/verilog/cm0_core_spu.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0/verilog/cm0_core.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0/verilog/cm0_dbg_bpu.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0/verilog/cm0_dbg_ctl.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0/verilog/cm0_dbg_dwt.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0/verilog/cm0_dbg_if.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0/verilog/cm0_dbg_sel.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0/verilog/cm0_matrix_sel.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0/verilog/cm0_matrix.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0/verilog/cm0_nvic_main.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0/verilog/cm0_nvic_reg.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0/verilog/cm0_nvic.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0/verilog/cm0_tarmac.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0/verilog/cm0_top_clk.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0/verilog/cm0_top_dbg.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0/verilog/cm0_top_sys.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0/verilog/cm0_top.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0/verilog/CORTEXM0.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0_dap/verilog/cm0_dap_ap_cdc.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0_dap/verilog/cm0_dap_ap_mast.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0_dap/verilog/cm0_dap_ap.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0_dap/verilog/cm0_dap_dp_cdc.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0_dap/verilog/cm0_dap_dp_jtag.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0_dap/verilog/cm0_dap_dp_pwr.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0_dap/verilog/cm0_dap_dp_sw.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0_dap/verilog/cm0_dap_dp.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0_dap/verilog/CORTEXM0DAP.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0_integration/verilog/CORTEXM0INTEGRATION.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0_integration/verilog/cortexm0_pmu.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0_integration/verilog/cortexm0_rst_ctl.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/cortexm0_integration/verilog/cortexm0_wic.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/models/cells/cm0_acg.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/models/cells/cm0_dap_cdc_capt_sync.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/models/cells/cm0_dap_cdc_comb_and_addr.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/models/cells/cm0_dap_cdc_comb_and_data.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/models/cells/cm0_dap_cdc_comb_and.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/models/cells/cm0_dap_cdc_send_addr.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/models/cells/cm0_dap_cdc_send_data.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/models/cells/cm0_dap_cdc_send_reset.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/models/cells/cm0_dap_cdc_send.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/models/cells/cm0_dap_jt_cdc_comb_and.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/models/cells/cm0_dap_sw_cdc_capt_reset.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/models/cells/cm0_dbg_reset_sync.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/models/cells/cm0_pmu_acg.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/models/cells/cm0_pmu_cdc_send_reset.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/models/cells/cm0_pmu_cdc_send_set.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/models/cells/cm0_pmu_sync_reset.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/models/cells/cm0_pmu_sync_set.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/models/cells/cm0_rst_send_set.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/models/cells/cm0_rst_sync.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/models/wrappers/CORTEXM0IMP.v $ARM_IP_LIBRARY_PATH/latest/Cortex-M0/logical/models/wrappers/CORTEXM0INTEGRATIONIMP.v
+read library -verilog -golden -append -define POWER_PINS $SOCLABS_SLCOREM0_TECH_DIR/src/verilog/slcorem0.v $SOCLABS_SLCOREM0_TECH_DIR/src/verilog/slcorem0_prmu.v $SOCLABS_SLCOREM0_TECH_DIR/src/verilog/slcorem0_stclkctrl.v $SOCLABS_SLCOREM0_TECH_DIR/src/verilog/slcorem0_rstctrl.v $SOCLABS_SLCOREM0_TECH_DIR/src/verilog/slcorem0_integration.v
+read library -verilog -golden -append -define POWER_PINS $SOCLABS_SOCDEBUG_TECH_DIR/controller/verilog/socdebug_adp_control.v $SOCLABS_SOCDEBUG_TECH_DIR/controller/verilog/socdebug_ahb.v $SOCLABS_SOCDEBUG_TECH_DIR/controller/verilog/socdebug_ft1248_control.v $SOCLABS_SOCDEBUG_TECH_DIR/controller/verilog/socdebug_usrt_control.v
+
+add search path "[get_db hdl_search_path] $SOCLABS_SLDMA350_TECH_DIR/src/logical/"
+add search path "[get_db hdl_search_path] $SOCLABS_SLDMA350_TECH_DIR/src/logical/shared/verilog/"
+read library -golden -append -define POWER_PINS -sv09 $SOCLABS_SLDMA350_TECH_DIR/src/logical/shared/verilog/ada_gen_regmap_sldma350_pkg.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/shared/verilog/ada_apb_regmap_conv_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/shared/verilog/ada_reg_field_ro_ro_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/shared/verilog/ada_reg_field_rw_ro_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/shared/verilog/ada_reg_field_rw_w1c_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/shared/verilog/ada_reg_field_rw_w1s_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/shared/verilog/ada_reg_field_rw_rw_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/shared/verilog/ada_gen_coreif_dmach_sldma350_pkg.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/shared/verilog/ada_gen_addrmap_dmach_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/shared/verilog/ada_interface_sldma350_pkg.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/shared/verilog/ada_address_map_m1_sldma350_inc.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/shared/verilog/ada_flop_en/verilog/ada_flop_en.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/shared/verilog/ada_or_tree/verilog/ada_or_tree.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/shared/verilog/ada_gen_regif_dmainfo_sldma350_pkg.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/models/cells/generic/ada_arm_flop.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/models/cells/generic/ada_arm_sync.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/models/cells/generic/ada_arm_mux2.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/models/cells/generic/ada_arm_or.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/models/cells/generic/ada_arm_idbit_v1.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/shared/verilog/ada_ecorevnum.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_top_sldma350/verilog/ada_top_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_biu_sldma350/verilog/ada_biu_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_biu_sldma350/verilog/ada_biu_read_switch_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_biu_sldma350/verilog/ada_biu_read_switch_wrapper_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_biu_sldma350/verilog/ada_biu_write_switch_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_biu_sldma350/verilog/ada_biu_write_switch_wrapper_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_biu_sldma350/verilog/ada_biu_arbiter_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_biu_sldma350/verilog/ada_biu_qv_cmp_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_biu_sldma350/verilog/ada_biu_lrg_arb_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_biu_sldma350/verilog/ada_biu_grant_queue_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_biu_sldma350/verilog/ada_biu_full_f2s_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_biu_sldma350/verilog/ada_biu_reverse_s2f_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_0_sldma350/verilog/ada_gen_regif_dmach_0_sldma350_pkg.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_0_sldma350/verilog/ada_gen_regif_dmach_0_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_0_sldma350/verilog/ada_gen_regmap_dmach_0_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_0_sldma350/verilog/ada_gen_fields_coreif_dmach_0_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_0_sldma350/verilog/ada_gen_coreif_res_dmach_0_sldma350_pkg.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_sldma350_pkg.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_ctrl_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_1d_wr_ctrl_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_2d_wr_ctrl_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_1d_rd_ctrl_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_2d_rd_ctrl_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_fifo_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_cmdlink_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_axi_rd_if_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_axi_wr_if_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_axi_stop_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_reg_bank_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_inc_gen_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_wrapper_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_slave_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_master_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_bypass_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_trig_in_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_trig_out_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_1_sldma350/verilog/ada_gen_regif_dmach_1_sldma350_pkg.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_1_sldma350/verilog/ada_gen_regif_dmach_1_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_1_sldma350/verilog/ada_gen_regmap_dmach_1_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_1_sldma350/verilog/ada_gen_fields_coreif_dmach_1_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_1_sldma350/verilog/ada_gen_coreif_res_dmach_1_sldma350_pkg.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_sldma350_pkg.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_ctrl_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_1d_wr_ctrl_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_2d_wr_ctrl_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_1d_rd_ctrl_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_2d_rd_ctrl_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_fifo_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_cmdlink_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_axi_rd_if_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_axi_wr_if_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_axi_stop_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_reg_bank_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_inc_gen_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_stream_wrapper_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_stream_slave_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_stream_master_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_stream_bypass_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_trig_in_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_trig_out_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_ctrl_sldma350/verilog/ada_gen_regif_dmainfo_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_ctrl_sldma350/verilog/ada_gen_regmap_dmainfo_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_ctrl_sldma350/verilog/ada_gen_fields_coreif_dmainfo_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_ctrl_sldma350/verilog/ada_gen_addrmap_dmainfo_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_ctrl_sldma350/verilog/ada_gen_coreif_dmansecctrl_sldma350_pkg.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_ctrl_sldma350/verilog/ada_gen_regif_dmansecctrl_sldma350_pkg.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_ctrl_sldma350/verilog/ada_gen_regif_dmansecctrl_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_ctrl_sldma350/verilog/ada_gen_regmap_dmansecctrl_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_ctrl_sldma350/verilog/ada_gen_fields_coreif_dmansecctrl_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_ctrl_sldma350/verilog/ada_gen_addrmap_dmansecctrl_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_ctrl_sldma350/verilog/ada_ctrl_apb_slave_mux_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_ctrl_sldma350/verilog/ada_ctrl_dmainfo_reg_bank_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_ctrl_sldma350/verilog/ada_ctrl_dmansecctrl_reg_bank_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_ctrl_sldma350/verilog/ada_ctrl_trigmask_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_ctrl_sldma350/verilog/ada_ctrl_trigin_used_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_ctrl_sldma350/verilog/ada_ctrl_trigout_used_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_ctrl_sldma350/verilog/ada_ctrl_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_qctrl_sldma350/verilog/ada_qctrl_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/ada_trigmtx_sldma350/verilog/ada_trigmtx_sldma350.sv
+read library -golden -append -define POWER_PINS -sv09 $SOCLABS_SLDMA350_TECH_DIR/src/logical/models/cells/generic/xhb500_or.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/models/cells/generic/xhb500_xor.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/models/cells/generic/xhb500_flop.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/models/cells/generic/xhb500_sync.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/shared/verilog/xhb500_regd_slice/verilog/xhb500_bypass_regd_slice_empty.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/shared/verilog/xhb500_regd_slice/verilog/xhb500_forward_regd_slice.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/shared/verilog/xhb500_regd_slice/verilog/xhb500_forward_regd_slice_empty.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_pkg.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_core.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_core_xin.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_core_h_xout.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_xreg.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_hreg.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_respreg_r.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_respreg_b.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_lpi.sv $SOCLABS_SLDMA350_TECH_DIR/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_strbgen.sv $SOCLABS_SLDMA350_TECH_DIR/wrapper/logical/sldma350_ahb.v $SOCLABS_SLDMA350_TECH_DIR/wrapper/logical/sldma350_trig_converter.v
+read library -verilog -golden -append -define POWER_PINS $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_BOOTROM_0.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_DMEM_0.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_H.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXPRAM_L.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_EXP.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_IMEM_0.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSIO.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_arbiter_SYSTABLE.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_default_slave.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix_lite.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_busmatrix.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_inititator_input.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_CPU_0.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DEBUG.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_0.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_matrix_decode_DMAC_1.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_BOOTROM_0.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_DMEM_0.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_H.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXPRAM_L.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_EXP.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_IMEM_0.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSIO.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_busmatrix/verilog/nanosoc_busmatrix/nanosoc_target_output_SYSTABLE.v
+read library -verilog -golden -append -define POWER_PINS $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_chip/chip/verilog/nanosoc_chip.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_system/verilog/nanosoc_system.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_subsystems/cpu/verilog/nanosoc_ss_cpu.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_subsystems/debug/verilog/nanosoc_ss_debug.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_subsystems/expansion/verilog/nanosoc_ss_expansion.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_subsystems/systemctrl/verilog/nanosoc_ss_systemctrl.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_subsystems/interconnect/verilog/nanosoc_ss_interconnect.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_regions/bootrom_0/verilog/nanosoc_bootrom_cpu_0.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_regions/bootrom_0/verilog/nanosoc_region_bootrom_0.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_regions/dmem_0/verilog/nanosoc_region_dmem_0.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_regions/imem_0/verilog/nanosoc_region_imem_0.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_regions/exp/verilog/nanosoc_region_exp.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_regions/expram_h/verilog/nanosoc_region_expram_h.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_regions/expram_l/verilog/nanosoc_region_expram_l.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysctrl.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_apb_ss.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_regions/systable/verilog/nanosoc_coresight_systable.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_regions/systable/verilog/nanosoc_region_systable.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_control/verilog/nanosoc_clkctrl.v $SOCLABS_NANOSOC_TECH_DIR/nanosoc/nanosoc_control/verilog/nanosoc_pin_mux.v
+read library /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a/tpdn65lpnv2od3wc.lib -liberty -golden -append
+
+read design -verilog -golden -define POWER_PINS $SOCLABS_NANOSOC_TECH_DIR/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads.v
+
+
+read library $PHYS_IP/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lib/sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.lib -liberty -revised
+read library $SOCLABS_PROJECT_DIR/memories/rf/rf_sp_hdf_ss_1p08v_1p08v_125c.lib -liberty -revised -append
+read library $SOCLABS_PROJECT_DIR/memories/bootrom/rom_via_ss_1p08v_1p08v_125c.lib -liberty -revised -append
+read library /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a/tpdn65lpnv2od3wc.lib -liberty -revised -append
+read design $SOCLABS_PROJECT_DIR/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads.vm -revised -verilog
diff --git a/ASIC/28pin/Cadence/scripts/nanosoc.mmmc b/ASIC/28pin/Cadence/scripts/nanosoc.mmmc
new file mode 100644
index 0000000000000000000000000000000000000000..15b9649a0f78ca42e22d7e9b2a2376720890953d
--- /dev/null
+++ b/ASIC/28pin/Cadence/scripts/nanosoc.mmmc
@@ -0,0 +1,86 @@
+set phys_lib /home/dwn1c21/SoC-Labs/phys_ip
+
+set base_path ${phys_lib}/arm/tsmc/cln65lp/sc9_base_rvt/r0p0
+set tech_path ${phys_lib}/arm/tsmc/cln65lp/arm_tech/r2p0
+set ram_16k_path /home/dwn1c21/SoC-Labs/accelerator-project/memories/rf_16k/
+set ram_08k_path /home/dwn1c21/SoC-Labs/accelerator-project/memories/rf_08k/
+
+set rom_path /home/dwn1c21/SoC-Labs/accelerator-project/memories/bootrom/
+set IO_driver_path /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a/
+
+create_library_set -name default_libset_max\
+ -timing\
+ [list ${base_path}/lib/sc9_cln65lp_base_rvt_ss_typical_max_1p08v_125c.lib ${ram_08k_path}/rf_08k_ss_1p08v_1p08v_125c.lib ${ram_16k_path}/rf_16k_ss_1p08v_1p08v_125c.lib ${rom_path}/rom_via_ss_1p08v_1p08v_125c.lib ${IO_driver_path}/tpdn65lpnv2od3wc.lib] \
+ -si\
+ [list ${base_path}/celtic/sc9_cln65lp_base_rvt_ss_typical_max_1p08v_125c.cdB]
+
+create_library_set -name default_libset_min\
+ -timing\
+ [list ${base_path}/lib/sc9_cln65lp_base_rvt_ff_typical_min_1p32v_m40c.lib ${ram_08k_path}/rf_08k_ff_1p32v_1p32v_m40c.lib ${ram_16k_path}/rf_16k_ff_1p32v_1p32v_m40c.lib ${rom_path}/rom_via_ff_1p32v_1p32v_m40c.lib ${IO_driver_path}/tpdn65lpnv2od3bc.lib] \
+ -si\
+ [list ${base_path}/celtic/sc9_cln65lp_base_rvt_ff_typical_min_1p32v_m40c.cdB]
+
+create_timing_condition -name default_mapping_tc_2\
+ -library_sets [list default_libset_min]
+create_timing_condition -name default_mapping_tc_1\
+ -library_sets [list default_libset_max]
+
+create_rc_corner -name default_rc_corner_worst\
+ -pre_route_res 1\
+ -post_route_res 1\
+ -pre_route_cap 1\
+ -post_route_cap 1\
+ -post_route_cross_cap 1\
+ -pre_route_clock_res 0\
+ -pre_route_clock_cap 0\
+ -cap_table ${tech_path}/cadence_captable/1p9m_6x2z/rcworst.captbl
+
+create_rc_corner -name default_rc_corner_best\
+ -pre_route_res 1\
+ -post_route_res 1\
+ -pre_route_cap 1\
+ -post_route_cap 1\
+ -post_route_cross_cap 1\
+ -pre_route_clock_res 0\
+ -pre_route_clock_cap 0\
+ -cap_table ${tech_path}/cadence_captable/1p9m_6x2z/rcbest.captbl
+
+create_rc_corner -name default_rc_corner_typical\
+ -pre_route_res 1\
+ -post_route_res 1\
+ -pre_route_cap 1\
+ -post_route_cap 1\
+ -post_route_cross_cap 1\
+ -pre_route_clock_res 0\
+ -pre_route_clock_cap 0\
+ -cap_table ${tech_path}/cadence_captable/1p9m_6x2z/typical.captbl
+
+
+
+create_delay_corner -name default_delay_corner_max\
+ -timing_condition {default_mapping_tc_1}\
+ -rc_corner default_rc_corner_worst
+
+create_delay_corner -name default_delay_corner_ocv\
+ -early_timing_condition {default_mapping_tc_2}\
+ -late_timing_condition {default_mapping_tc_1}\
+ -rc_corner default_rc_corner_typical
+
+create_delay_corner -name default_delay_corner_min\
+ -timing_condition default_mapping_tc_2\
+ -rc_corner default_rc_corner_best
+
+create_constraint_mode -name default_constraint_mode\
+ -sdc_files\
+ [list ../../../constraints.sdc]
+
+create_analysis_view -name default_analysis_view_setup -constraint_mode default_constraint_mode -delay_corner default_delay_corner_max
+
+create_analysis_view -name default_analysis_view_hold -constraint_mode default_constraint_mode -delay_corner default_delay_corner_min
+
+
+create_analysis_view -name typical_analysis_view_setup -constraint_mode default_constraint_mode -delay_corner default_delay_corner_ocv
+create_analysis_view -name typical_analysis_view_hold -constraint_mode default_constraint_mode -delay_corner default_delay_corner_ocv
+
+
+set_analysis_view -setup [list default_analysis_view_setup] -hold [list default_analysis_view_hold]
diff --git a/ASIC/28pin/Cadence/scripts/nanosoc_io_plan.io b/ASIC/28pin/Cadence/scripts/nanosoc_io_plan.io
new file mode 100644
index 0000000000000000000000000000000000000000..176e13ca2a80a44816fca609686b36c8c3ff4a6a
--- /dev/null
+++ b/ASIC/28pin/Cadence/scripts/nanosoc_io_plan.io
@@ -0,0 +1,50 @@
+###############################################################
+# Generated by: Cadence Innovus 21.11-s130_1
+# OS: Linux x86_64(Host ID srv03335)
+# Generated on: Thu Nov 16 16:18:31 2023
+# Design: nanosoc_chip_pads
+# Command: write_io_file -locations -template nanosoc_chip_pads.save.io
+###############################################################
+
+(globals
+ version = 3
+ io_order = default
+)
+(iopad
+ (top
+ (inst name="uPAD_TEST_I" offset=149.29)
+ (inst name="uPAD_SWDCK_I" offset=257.86 place_status=placed )
+ (inst name="uPAD_VDD_3" offset=366.43 place_status=placed )
+ (inst name="uPAD_VSS_3" offset=475.00 place_status=placed )
+ (inst name="uPAD_VDDIO_3" offset=583.57 place_status=placed )
+ (inst name="uPAD_P1_00" offset=692.14 place_status=placed )
+ (inst name="uPAD_P1_01" offset=800.71 place_status=placed )
+ )
+ (left
+ (inst name="uPAD_P0_03" offset=149.29 place_status=placed )
+ (inst name="uPAD_VDDACC_0" offset=257.86 place_status=placed )
+ (inst name="uPAD_VSS_0" offset=366.43 place_status=placed )
+ (inst name="uPAD_CLK_I" offset=475.00 place_status=placed )
+ (inst name="uPAD_VDD_0" offset=583.57 place_status=placed )
+ (inst name="uPAD_VDDIO_0" offset=692.14 place_status=placed )
+ (inst name="uPAD_SWDIO_IO" offset=800.71 place_status=placed )
+ )
+ (bottom
+ (inst name="uPAD_P0_02" offset=149.29 place_status=placed )
+ (inst name="uPAD_VDDACC_1" offset=257.86 place_status=placed )
+ (inst name="uPAD_VDDIO_1" offset=366.43 place_status=placed )
+ (inst name="uPAD_VDD_1" offset=475.00 place_status=placed )
+ (inst name="uPAD_VSS_1" offset=583.57 place_status=placed )
+ (inst name="uPAD_P0_01" offset=692.14 place_status=placed )
+ (inst name="uPAD_P0_00" offset=800.71 )
+ )
+ (right
+ (inst name="uPAD_P1_03" offset=149.29 place_status=placed )
+ (inst name="uPAD_P1_02" offset=257.86 place_status=placed )
+ (inst name="uPAD_VDDACC_2" offset=366.43 place_status=placed )
+ (inst name="uPAD_VDD_2" offset=475.00 place_status=placed )
+ (inst name="uPAD_VSS_2" offset=583.57 place_status=placed )
+ (inst name="uPAD_VDDIO_2" offset=692.14 place_status=placed )
+ (inst name="uPAD_NRST_I" offset=800.71 place_status=placed )
+ )
+)
diff --git a/ASIC/Cadence/Innovus/place.tcl b/ASIC/28pin/Cadence/scripts/place.tcl
similarity index 96%
rename from ASIC/Cadence/Innovus/place.tcl
rename to ASIC/28pin/Cadence/scripts/place.tcl
index cc6fcde958632176154d97d632e48cef36f79cc7..9f25bb8c140db90cffb66fa2308fecdb43ff2be2 100644
--- a/ASIC/Cadence/Innovus/place.tcl
+++ b/ASIC/28pin/Cadence/scripts/place.tcl
@@ -15,7 +15,7 @@ set_db place_global_uniform_density true
### Placement Mode Config
set_db place_design_floorplan_mode false
-place_design
+place_opt_design
### Delay Calculation
write_sdf design.sdf -ideal_clock_network
diff --git a/ASIC/28pin/Cadence/scripts/place_macros.tcl b/ASIC/28pin/Cadence/scripts/place_macros.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..db37a2022bcd52cbf0f50d4744d9930af48614f4
--- /dev/null
+++ b/ASIC/28pin/Cadence/scripts/place_macros.tcl
@@ -0,0 +1,28 @@
+#------------------------------------------------------------------------------------
+# Cadence Innovus: Place macros
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# Daniel Newbrook (d.newbrook@soton.ac.uk)
+# Copyright (c) 2023, SoC Labs (www.soclabs.org)
+#------------------------------------------------------------------------------------
+
+# relative floorplan
+delete_relative_floorplan -all
+create_relative_floorplan -ref_type core_boundary -horizontal_edge_separate {1 -4.8 1} -vertical_edge_separate {2 0 2} -place u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf
+create_relative_floorplan -ref_type object -horizontal_edge_separate {3 -18.0 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf
+create_relative_floorplan -ref_type core_boundary -horizontal_edge_separate {1 -4.8 1} -vertical_edge_separate {1 0 1} -place u_nanosoc_chip_u_system_u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf
+create_relative_floorplan -ref_type object -orient R0 -horizontal_edge_separate {3 -14.4 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system_u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system_u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf
+create_relative_floorplan -ref_type core_boundary -orient R180 -horizontal_edge_separate {3 200 3} -vertical_edge_separate {2 0 2} -place u_nanosoc_chip_u_system_u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom
+
+move_obj u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -point {500 500}
+update_floorplan_obj -obj u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -rects {600 135.0 865 265.0}
+add_fences -hinst u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -min_gap 5
+create_partition -hinst u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -core_spacing 2.0 2.0 2.0 2.0 -rail_width 0.0 -min_pitch_left 2 -min_pitch_right 2 -min_pitch_top 2 -min_pitch_bottom 2 -reserved_layer { 1 2 3 4 5 6 7 8 9 10} -pin_layer_top { 2 4 6 8 10} -pin_layer_left { 3 5 7 9} -pin_layer_bottom { 2 4 6 8 10} -pin_layer_right { 3 5 7 9} -place_halo 2 2 2 2 -route_halo 2.0 -route_halo_top_layer 5 -route_halo_bottom_layer 1
+
+create_place_halo -halo_deltas {2 2 0 2} -insts u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf
+create_place_halo -halo_deltas {2 2 0 2} -insts u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf
+create_place_halo -halo_deltas {0 2 2 2} -insts u_nanosoc_chip_u_system_u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf
+create_place_halo -halo_deltas {0 2 2 2} -insts u_nanosoc_chip_u_system_u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_genblk1.u_rf_sp_hdf
+create_place_halo -halo_deltas {2 2 0 2} -insts u_nanosoc_chip_u_system_u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom
diff --git a/ASIC/28pin/Cadence/scripts/pnr_flow.tcl b/ASIC/28pin/Cadence/scripts/pnr_flow.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..91a14370cd30dae5731a50f47698e9e0f144c67c
--- /dev/null
+++ b/ASIC/28pin/Cadence/scripts/pnr_flow.tcl
@@ -0,0 +1,76 @@
+######################################
+# Script : Place and Route Flow
+# Date : 25th May 2023
+# Author : Srimanth Tenneti
+# Description : Innovus PnR Flow
+######################################
+
+puts "Starting PnR Flow ..."
+
+
+### Design Import
+source design_import.tcl
+
+### IO Planning
+source io_plan.tcl
+
+### Memory and accelerator placement
+source place_macros.tcl
+commit_power_intent
+check_power_domains
+
+### Power Plan
+source power_plan.tcl
+
+### Power Route
+source power_route.tcl
+
+report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/1pre_place_nanosoc_imp_timing.rep
+
+### Placement
+source place.tcl
+
+report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/2post_place_nanosoc_imp_timing.rep
+
+
+uniquify nanosoc_chip_pads -verbose
+### CTS
+source clock_tree_synthesis.tcl
+
+report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/3post_clock_nanosoc_imp_timing.rep
+
+### Add filler cells
+eval_legacy { addFiller -cell FILL128_A9TR WELLANTENNATIEPW2_A9TR FILLTIE8_A9TR FILLTIE64_A9TR FILLTIE4_A9TR FILLTIE32_A9TR FILLTIE2_A9TR FILLTIE16_A9TR FILLTIE128_A9TR FILLCAPTIE8_A9TR -prefix FILLER -powerDomain ACCEL -doDRC }
+eval_legacy { addFiller -cell WELLANTENNATIEPW2_A9TR FILLTIE8_A9TR FILLTIE64_A9TR FILLTIE4_A9TR FILLTIE32_A9TR FILLTIE2_A9TR FILLTIE16_A9TR FILLTIE128_A9TR FILLCAPTIE8_A9TR -prefix FILLER -powerDomain TOP -doDRC }
+
+
+### Routing
+source route.tcl
+
+report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/4post_route_nanosoc_imp_timing.rep
+
+check_antenna
+
+### Fill metal
+set_metal_fill -layer M1 -opc_active_spacing 0.090 -border_spacing -0.001
+set_metal_fill -layer M2 -opc_active_spacing 0.100 -border_spacing -0.001
+set_metal_fill -layer M3 -opc_active_spacing 0.100 -border_spacing -0.001
+set_metal_fill -layer M4 -opc_active_spacing 0.100 -border_spacing -0.001
+set_metal_fill -layer M5 -opc_active_spacing 0.100 -border_spacing -0.001
+set_metal_fill -layer M6 -opc_active_spacing 0.100 -border_spacing -0.001
+set_metal_fill -layer M7 -opc_active_spacing 0.100 -border_spacing -0.001
+set_metal_fill -layer M8 -opc_active_spacing 0.400 -border_spacing -0.001
+set_metal_fill -layer M9 -opc_active_spacing 0.400 -border_spacing -0.001
+set_metal_fill -layer AP -opc_active_spacing 2.000 -border_spacing -0.001
+add_metal_fill -layers { M1 M2 M3 M4 M5 M6 M7 M8 M9 AP } -nets { VSSIO VSS VDDACC VDDIO VDD }
+
+
+report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_timing.rep
+report_area > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_area.rep
+report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_power.rep
+
+gui_show
+
+
+
+
diff --git a/ASIC/28pin/Cadence/scripts/power_plan.tcl b/ASIC/28pin/Cadence/scripts/power_plan.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..97873398fd2dc6953fb1ae27a70c0257b27149a2
--- /dev/null
+++ b/ASIC/28pin/Cadence/scripts/power_plan.tcl
@@ -0,0 +1,85 @@
+#########################################
+# Script : Power Planning
+# Tool : Cadence Innovus
+# Date : May 22, 2023
+# Author : Srimanth Tenneti
+#########################################
+
+### Connecting Global Nets
+connect_global_net VDD -type pg_pin -pin_base_name VDD -inst_base_name *
+connect_global_net VDDIO -type pg_pin -pin_base_name VDDIO -inst_base_name *
+connect_global_net VSS -type pg_pin -pin_base_name VSS -inst_base_name *
+connect_global_net VSSIO -type pg_pin -pin_base_name VSSIO -inst_base_name *
+connect_global_net VDDACC -type pg_pin -pin_base_name VDD -inst_base_name {} -hinst u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -override
+### Top and Bottom Metal Declartions
+set_db add_rings_stacked_via_top_layer M8
+set_db add_rings_stacked_via_bottom_layer M1
+
+### Adding Rings
+add_rings -nets {VDD VDDACC VSS} -type core_rings -follow core -layer {top M9 bottom M9 left M8 right M8} -width {top 3 bottom 3 left 3 right 3} -spacing {top 1 bottom 1 left 1 right 1} -offset {top 2 bottom 2 left 2 right 2} -center 0 -threshold 0 -jog_distance 0 -snap_wire_center_to_grid none
+
+### Adding Stripes
+set_db add_stripes_ignore_block_check true
+set_db add_stripes_break_at none
+set_db add_stripes_route_over_rows_only false
+set_db add_stripes_rows_without_stripes_only false
+set_db add_stripes_extend_to_closest_target none
+set_db add_stripes_stop_at_last_wire_for_area false
+set_db add_stripes_ignore_non_default_domains true
+set_db add_stripes_trim_antenna_back_to_shape none
+set_db add_stripes_spacing_type edge_to_edge
+set_db add_stripes_spacing_from_block 0
+set_db add_stripes_stripe_min_length stripe_width
+set_db add_stripes_stacked_via_top_layer AP
+set_db add_stripes_stacked_via_bottom_layer M1
+set_db add_stripes_via_using_exact_crossover_size false
+set_db add_stripes_split_vias false
+set_db add_stripes_orthogonal_only true
+set_db add_stripes_allow_jog { padcore_ring block_ring }
+set_db add_stripes_skip_via_on_pin { standardcell }
+set_db add_stripes_skip_via_on_wire_shape { noshape }
+add_stripes -nets {VDD VDDACC VSS} -layer M6 -direction vertical -width 1.8 -spacing 0.8 -set_to_set_distance 60 -extend_to all_domains -start_from left -start_offset 50 -stop_offset 0 -switch_layer_over_obs false -max_same_layer_jog_length 2 -pad_core_ring_top_layer_limit AP -pad_core_ring_bottom_layer_limit M1 -block_ring_top_layer_limit AP -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none
+
+deselect_obj -all
+
+# Connect Accelerator region
+select_obj u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator
+set_db add_stripes_ignore_block_check true
+set_db add_stripes_break_at none
+set_db add_stripes_route_over_rows_only false
+set_db add_stripes_rows_without_stripes_only false
+set_db add_stripes_extend_to_closest_target stripe
+set_db add_stripes_stop_at_last_wire_for_area false
+set_db add_stripes_partial_set_through_domain true
+set_db add_stripes_ignore_non_default_domains false
+set_db add_stripes_trim_antenna_back_to_shape none
+set_db add_stripes_spacing_type edge_to_edge
+set_db add_stripes_spacing_from_block 0
+set_db add_stripes_stripe_min_length stripe_width
+set_db add_stripes_stacked_via_top_layer AP
+set_db add_stripes_stacked_via_bottom_layer M4
+set_db add_stripes_via_using_exact_crossover_size false
+set_db add_stripes_split_vias false
+set_db add_stripes_orthogonal_only true
+set_db add_stripes_allow_jog { padcore_ring block_ring }
+set_db add_stripes_skip_via_on_pin { standardcell }
+set_db add_stripes_skip_via_on_wire_shape { noshape }
+add_stripes -nets {VDDACC VSS} -layer M9 -direction horizontal -width 1 -spacing 0.5 -set_to_set_distance 15 -over_power_domain 1 -start_from bottom -start_offset 0 -stop_offset 0 -switch_layer_over_obs false -max_same_layer_jog_length 2 -pad_core_ring_top_layer_limit AP -pad_core_ring_bottom_layer_limit M1 -block_ring_top_layer_limit AP -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none
+
+deselect_obj -all
+
+# connect Macros
+select_obj [ list u_nanosoc_chip_u_system_u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_genblk1.u_rf_sp_hdf u_nanosoc_chip_u_system_u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf u_nanosoc_chip_u_system_u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom]
+set_db add_stripes_ignore_block_check false
+set_db add_stripes_break_at none
+set_db add_stripes_route_over_rows_only false
+set_db add_stripes_rows_without_stripes_only false
+set_db add_stripes_extend_to_closest_target {ring stripe}
+add_stripes -nets {VDD VSS} -layer M5 -direction horizontal -width 1 -spacing 0.5 -set_to_set_distance 15 -over_power_domain 1 -start_from bottom -start_offset 8 -stop_offset 0 -switch_layer_over_obs false -merge_stripes_value 500 -max_same_layer_jog_length 2 -pad_core_ring_top_layer_limit AP -pad_core_ring_bottom_layer_limit M1 -block_ring_top_layer_limit AP -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none
+
+deselect_obj -all
+
+# Add END CAPS
+add_endcaps -start_row_cap ENDCAPTIE2_A9TR -end_row_cap ENDCAPTIE2_A9TR -prefix ENDCAP
+add_endcaps -power_domain ACCEL -start_row_cap ENDCAPTIE2_A9TR -end_row_cap ENDCAPTIE2_A9TR -prefix ENDCAP
+
diff --git a/ASIC/28pin/Cadence/scripts/power_route.tcl b/ASIC/28pin/Cadence/scripts/power_route.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..bf05e721f3b978bfc85e3b7aa790c38c7ccce5a8
--- /dev/null
+++ b/ASIC/28pin/Cadence/scripts/power_route.tcl
@@ -0,0 +1,12 @@
+##################################
+# Script : Special Route Script
+# Date : May 24, 2023
+# Description : Power Routing
+# Author : Srimanth Tenneti
+##################################
+route_special -connect {pad_pin pad_ring} -layer_change_range { M1(1) AP(10) } -block_pin_target nearest_target -pad_pin_port_connect {all_port all_geom} -pad_pin_target nearest_target -allow_jogging 1 -crossover_via_layer_range { M1(1) AP(10) } -nets { VDD VSS VDDACC } -allow_layer_change 1 -pad_pin_width 6 -target_via_layer_range { M1(1) AP(10) }
+
+route_special -connect {block_pin core_pin floating_stripe} -layer_change_range { M1(1) AP(10) } -block_pin_target nearest_target -pad_pin_port_connect {all_port one_geom} -pad_pin_target nearest_target -core_pin_target first_after_row_end -floating_stripe_target {block_ring pad_ring ring stripe ring_pin block_pin followpin} -allow_jogging 1 -power_domains { ACCEL } -crossover_via_layer_range { M1(1) AP(10) } -nets { VDDACC VSS } -allow_layer_change 1 -block_pin use_lef -target_via_layer_range { M1(1) AP(10) }
+route_special -connect {block_pin core_pin floating_stripe} -layer_change_range { M1(1) AP(10) } -block_pin_target nearest_target -pad_pin_port_connect {all_port one_geom} -pad_pin_target nearest_target -core_pin_target first_after_row_end -floating_stripe_target {block_ring pad_ring ring stripe ring_pin block_pin followpin} -allow_jogging 1 -power_domains { TOP } -crossover_via_layer_range { M1(1) AP(10) } -nets { VDD VSS } -allow_layer_change 1 -block_pin use_lef -target_via_layer_range { M1(1) AP(10) }
+
+#route_special -nets {VDD VSS} -connect core_pin -block_pin_target nearest_target -core_pin_target first_after_row_end -allow_jogging 1 -allow_layer_change 1 -layer_change_range { M1(1) M8(8) } -crossover_via_layer_range { M1(1) M8(8) } -target_via_layer_range { M1(1) M8(8) }
diff --git a/ASIC/Cadence/Innovus/route.tcl b/ASIC/28pin/Cadence/scripts/route.tcl
similarity index 100%
rename from ASIC/Cadence/Innovus/route.tcl
rename to ASIC/28pin/Cadence/scripts/route.tcl
diff --git a/ASIC/28pin/Cadence/scripts/voltus_pg.tcl b/ASIC/28pin/Cadence/scripts/voltus_pg.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..297607d8bf655d70d380387c2358844940347467
--- /dev/null
+++ b/ASIC/28pin/Cadence/scripts/voltus_pg.tcl
@@ -0,0 +1,15 @@
+
+# Set library paths
+# !! EDIT THIS TO YOUR PATHS IN YOUR ENVIRONMENT
+set TECH_LEF $::env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/lef/1p9m_6x2z/sc12_tech.lef
+set BASE_LEF $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lef/sc12_cln65lp_base_rvt.lef
+set IO_PAD_LEF /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Backend/lef/tpbn65v_9lm.lef
+set IO_PAD_DRIVER_LEF /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Backend/lef/tpdn65lpnv2od3_9lm.lef
+
+
+# !! THESE SHOULD BE CORRECT FOR ANY ENVIRONMENT AS THEY ARE GENERATED BY MAKEFILE
+set RF_LEF $::env(SOCLABS_PROJECT_DIR)/memories/rf/rf_sp_hdf.lef
+set ROM_LEF $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via.lef
+
+### Reading LEFs
+read_lib -lef [list ${TECH_LEF} ${BASE_LEF} ${IO_PAD_LEF} ${IO_PAD_DRIVER_LEF} ${RF_LEF} ${ROM_LEF}]
\ No newline at end of file
diff --git a/ASIC/Synopsys/Formality/fm_shell.tcl b/ASIC/28pin/Synopsys/scripts/fm_shell.tcl
similarity index 81%
rename from ASIC/Synopsys/Formality/fm_shell.tcl
rename to ASIC/28pin/Synopsys/scripts/fm_shell.tcl
index 31f2065b92d86b72dc0d42048232b293dc72c1bf..87b374118661e041b6400a887e943cee8c4b3b00 100644
--- a/ASIC/Synopsys/Formality/fm_shell.tcl
+++ b/ASIC/28pin/Synopsys/scripts/fm_shell.tcl
@@ -1,16 +1,19 @@
set_mismatch_message_filter -warn FMR_ELAB-147
set_svf -append $env(SOCLABS_PROJECT_DIR)/nanosoc_tech/synthesis/default.svf
+set IO_FRONTEND_DIR /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a
source $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/formality_flist.tcl
read_db -r $env(SOCLABS_PROJECT_DIR)/memories/rf/rf_sp_hdf_ss_1p08v_1p08v_125c.db
read_db -r $env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via_ss_1p08v_1p08v_125c.db
+read_db -r $IO_FRONTEND_DIR/tpdn65lpnv2od3wc.db
set_top nanosoc_chip_pads
# Read db files
read_db -i $env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/db/sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.db
read_db -i $env(SOCLABS_PROJECT_DIR)/memories/rf/rf_sp_hdf_ss_1p08v_1p08v_125c.db
read_db -i $env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via_ss_1p08v_1p08v_125c.db
+read_db -i $IO_FRONTEND_DIR/tpdn65lpnv2od3wc.db
# Read Gate netlist
read_verilog -i $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads.vm
diff --git a/ASIC/Synopsys/ICC2/place_memories.tcl b/ASIC/28pin/Synopsys/scripts/place_memories.tcl
similarity index 100%
rename from ASIC/Synopsys/ICC2/place_memories.tcl
rename to ASIC/28pin/Synopsys/scripts/place_memories.tcl
diff --git a/ASIC/28pin/Synopsys/scripts/place_pins.tcl b/ASIC/28pin/Synopsys/scripts/place_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..d89cdf9a3adacb6c3f13f1f99555a80ce806d2e9
--- /dev/null
+++ b/ASIC/28pin/Synopsys/scripts/place_pins.tcl
@@ -0,0 +1,6 @@
+set_individual_pin_constraints -ports {P0[3] P0[2] P0[1] P0[0]} -sides 1
+set_individual_pin_constraints -ports {P1[3] P1[2] P1[1] P1[0]} -sides 3
+set_individual_pin_constraints -ports {CLK TEST VDD VDDIO VDDACC} -sides 2
+set_individual_pin_constraints -ports {NRST VSS VSSIO SWDIO SWDCK} -sides 4
+
+place_pins -self
\ No newline at end of file
diff --git a/ASIC/Synopsys/ICC2/pnr.tcl b/ASIC/28pin/Synopsys/scripts/pnr.tcl
similarity index 85%
rename from ASIC/Synopsys/ICC2/pnr.tcl
rename to ASIC/28pin/Synopsys/scripts/pnr.tcl
index 17cbb5880ab06be911f734a90c2a144af3adf22d..9fdf34e618c2ad7f4241833932ac0a105fe334da 100644
--- a/ASIC/Synopsys/ICC2/pnr.tcl
+++ b/ASIC/28pin/Synopsys/scripts/pnr.tcl
@@ -11,23 +11,28 @@
set design_name nanosoc_chip_pads
-set PHYS_IP_DIR /research/AAA/phys_ip_library
+# Edit these for your environment
+set PHYS_IP_DIR /research/AAA/phys_ip_library
+set MEM_DIR /home/dwn1c21/SoC-Labs/accelerator-project/memories
+set IO_BACKEND_DIR /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Backend/lef
+set IO_FRONTEND_DIR /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a
-set_app_var link_library $PHYS_IP_DIR/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/db/sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.db
-create_lib tsmc65lp -technology $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/milkyway/1p9m_6x2z/sc12_tech.tf -ref_libs [list $PHYS_IP_DIR/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lef/sc12_cln65lp_base_rvt.lef /home/dwn1c21/SoC-Labs/accelerator-project/memories/rf/rf_sp_hdf.lef /home/dwn1c21/SoC-Labs/accelerator-project/memories/bootrom/rom_via.lef]
+set_app_var link_library [list $PHYS_IP_DIR/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/db/sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.db $MEM_DIR/bootrom/rom_via_ss_1p08v_1p08v_125c.db $MEM_DIR/rf/rf_sp_hdf_ss_1p08v_1p08v_125c.db $IO_FRONTEND_DIR/tpdn65lpnv2od3wc.db]
+create_lib tsmc65lp -technology $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/milkyway/1p9m_6x2z/sc12_tech.tf -ref_libs [list $PHYS_IP_DIR/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lef/sc12_cln65lp_base_rvt.lef $MEM_DIR/rf/rf_sp_hdf.lef $MEM_DIR/bootrom/rom_via.lef $IO_BACKEND_DIR/tpbn65v_9lm.lef $IO_BACKEND_DIR/tpdn65lpnv2od3_9lm.lef]
read_parasitic_tech -name typical -tlup $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/typical.tluplus -layermap $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/tluplus.map
read_parasitic_tech -name rcbest -tlup $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/rcbest.tluplus -layermap $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/tluplus.map
read_parasitic_tech -name rcworst -tlup $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/rcworst.tluplus -layermap $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/tluplus.map
-read_verilog -library tsmc65lp -design nanosoc_chip_pads -top nanosoc_chip_pads $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/Synopsys/nanosoc_chip_pads.vm
+read_verilog -library tsmc65lp -design nanosoc_chip_pads -top nanosoc_chip_pads $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/Synopsys/nanosoc_chip_pads.vp
read_def $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/Synopsys/nanosoc_chip_pads.def
link_block
+create_cell {PAD_CORNER_NE PAD_CORNER_SE PAD_CORNER_SW PAD_CORNER_NW} PCORNER
-initialize_floorplan -side_length {1600 1600} -core_offset {100}
+initialize_floorplan -side_length {1500 1500} -core_offset {150}
create_io_ring -name main_io
explore_logic_hierarchy -organize
@@ -35,19 +40,16 @@ explore_logic_hierarchy -organize
source place_pins.tcl
# Power domains TOP ACCEL and MEM
-create_power_domain TOP
+create_power_domain TOP
create_power_domain ACCEL -elements {u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator}
-create_power_domain MEM -elements {u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram}
#VDD
create_supply_port VDD
create_supply_net VDD -domain TOP
-create_supply_net VDD -domain MEM -reuse
connect_supply_net VDD -ports VDD
#VSS
create_supply_port VSS
create_supply_net VSS -domain TOP
-create_supply_net VSS -domain MEM -reuse
create_supply_net VSS -domain ACCEL -reuse
connect_supply_net VSS -ports VSS
@@ -63,12 +65,13 @@ connect_supply_net VDDIO -ports VDDIO
set_domain_supply_net TOP -primary_power_net VDD -primary_ground_net VSS
set_domain_supply_net ACCEL -primary_power_net VDDACC -primary_ground_net VSS
-set_domain_supply_net MEM -primary_power_net VDD -primary_ground_net VSS
# Create voltage and power region for accelerator
create_voltage_area -power_domains ACCEL -power VDDACC -ground VSS -nwell VDDACC -pwell VSS -region {{{150 1050} {1100 1650}}} -name VA_ACCEL -cells [get_cells -physical_context -hierarchical \
-regexp u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator/.*]
create_pg_region {pg_ACCEL} -voltage_area VA_ACCEL -expand {0 10}
+create_pg_region {pg_TOP} -voltage_area DEFAULT_VA
+
set_parasitic_parameters -early_spec rcbest -early_temperature -40 -late_spec rcworst -late_temperature 125
current_corner default
@@ -90,8 +93,6 @@ add_port_state VDDIO -state {on 3.0}
create_pst ao_pst -supplies {VSS VDD VDDACC VDDIO}
add_pst_state ao -pst ao_pst -state {on on on on}
-set_voltage_area -add_power_domains MEM DEFAULT_VA
-
commit_upf
set_app_options -list {opt.timing.effort {medium}}
diff --git a/ASIC/Synopsys/ICC2/power_plan.tcl b/ASIC/28pin/Synopsys/scripts/power_plan.tcl
similarity index 88%
rename from ASIC/Synopsys/ICC2/power_plan.tcl
rename to ASIC/28pin/Synopsys/scripts/power_plan.tcl
index d6979b02361303f4d151061c842652a3eaa8e730..f6a77a6e4dc3298d6ef81a9e5f8ab08466b54211 100644
--- a/ASIC/Synopsys/ICC2/power_plan.tcl
+++ b/ASIC/28pin/Synopsys/scripts/power_plan.tcl
@@ -6,11 +6,11 @@ set_pg_strategy core_ring -pattern {{name:ring_pattern} {nets: {VDD VDDIO VDDACC
# Create vertical straps in Nanosoc region
create_pg_mesh_pattern strap_pattern -layers {{{vertical_layer: M6} {width: 1} {pitch: 50} {spacing: interleaving} {trim: false}}}
-set_pg_strategy M6_straps -voltage_areas DEFAULT_VA -pattern {{name: strap_pattern}{nets: VDD VSS}} -extension {{{stop : outermost_ring}}} -blockage {{{pg_regions : {pg_ACCEL}}}}
+set_pg_strategy M6_straps -voltage_areas VA_TOP -pattern {{name: strap_pattern}{nets: VDD VSS}} -extension {{{stop : outermost_ring}}} -blockage {{{pg_regions : {pg_ACCEL}}}}
# Create std cell rails in Nanosoc Region
create_pg_std_cell_conn_pattern rail_pattern -layers M5
-set_pg_strategy M5_rails -voltage_areas DEFAULT_VA -pattern {{name: rail_pattern}{nets: VDD VSS}} -extension {{{stop : outermost_ring}}} -blockage {{{pg_regions : {pg_ACCEL}}}}
+set_pg_strategy M5_rails -voltage_areas VA_TOP -pattern {{name: rail_pattern}{nets: VDD VSS}} -extension {{{stop : outermost_ring}}} -blockage {{{pg_regions : {pg_ACCEL}}}}
# Create rails for macros
create_pg_macro_conn_pattern sram_pg_mesh -pin_conn_type long_pin -nets {VDD VSS} -direction horizontal -layers M5 -width 0.64 -spacing interleaving -pitch 3 -pin_layers {M4} -via_rule {{intersection : all}}
diff --git a/ASIC/Synopsys/DC/synopsys_lib_conversion.tcl b/ASIC/28pin/Synopsys/scripts/synopsys_lib_conversion.tcl
similarity index 100%
rename from ASIC/Synopsys/DC/synopsys_lib_conversion.tcl
rename to ASIC/28pin/Synopsys/scripts/synopsys_lib_conversion.tcl
diff --git a/ASIC/28pin/Synopsys/scripts/synthesis.tcl b/ASIC/28pin/Synopsys/scripts/synthesis.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..0cc586503340e59a0bc690c71a136c776098f60f
--- /dev/null
+++ b/ASIC/28pin/Synopsys/scripts/synthesis.tcl
@@ -0,0 +1,83 @@
+#-----------------------------------------------------------------------------
+# NanoSoC Synopsys synthesis tcl file to be run with dc_shell
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# Daniel Newbrook (d.newbrook@soton.ac.uk)
+#
+# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+set rtlPath $env(SOCLABS_PROJECT_DIR)
+set report_path $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/
+set top_module nanosoc_chip_pads
+set io_path /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a
+#supress_message = {ELAB-405}
+#####
+# Set search_path
+#
+# List locations where your standard cell libraries may be located
+#
+#####
+set search_path [list . $search_path $env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/sdb/ $env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/db/ $env(SOCLABS_PROJECT_DIR)/memories/rf $env(SOCLABS_PROJECT_DIR)/memories/bootrom $io_path]
+set search_path [concat $rtlPath $search_path]
+######
+# Set Target Library
+#
+# Set a default target library for Design Compiler to target when compiling a design
+#
+######
+set target_library "sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.db rf_sp_hdf_ss_1p08v_1p08v_125c.db rom_via_ss_1p08v_1p08v_125c.db tpdn65lpnv2od3wc.db"
+
+######
+# Set Link Library
+#
+# Set a default link library for Design Compiler to target when compiling a design
+#
+######
+set link_library "sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.db rf_sp_hdf_ss_1p08v_1p08v_125c.db rom_via_ss_1p08v_1p08v_125c.db tpdn65lpnv2od3wc.db"
+
+source $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/dc_flist.tcl
+elaborate $top_module -lib WORK
+current_design $top_module
+
+# Link Design
+link
+
+read_sdc ../../constraints.sdc
+
+load_upf ../nanosoc_chip_pads.upf
+
+set_voltage -object_list {VDD VDDACC VDD_VSS.power VDDACC_VSS.power TOP.primary.power ACCEL.primary.power} 1.08
+set_voltage -object_list {VSS VDD_VSS.ground VDDACC_VSS.ground TOP.primary.ground ACCEL.primary.ground} 0.00
+
+set_operating_conditions -library sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c ss_typical_max_1p08v_125c
+
+set_app_var compile_delete_unloaded_sequential_cells false
+compile_ultra -gate_clock -scan
+
+set_scan_configuration -chain_count 2
+set_dft_signal -view spec -type ScanDataIn -port DFT_SDI_1
+set_dft_signal -view spec -type ScanDataIn -port DFT_SDI_2
+set_dft_signal -view spec -type ScanDataOut -port DFT_SDO_1
+set_dft_signal -view spec -type ScanDataOut -port DFT_SDO_2
+set_dft_signal -view spec -type ScanEnable -port TEST -active_state 1
+set_dft_signal -view existing_dft -type Reset -port NRST -active_state 0
+set_scan_configuration -power_domain_mixing false
+create_test_protocol -infer_clock -infer_asynch
+dft_drc
+insert_dft
+
+write -hierarchy -format verilog -output $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/Synopsys/nanosoc_chip_pads.vm
+write -hierarchy -format verilog -pg -output $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/Synopsys/nanosoc_chip_pads.vp
+write_scan_def -output $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/Synopsys/nanosoc_chip_pads.def
+write_test_protocol -output $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/Synopsys/nanosoc_chip_pads_scan.stil
+
+redirect [format "%s%s%s" $report_path $top_module _area.rep] { report_area }
+redirect -append [format "%s%s%s" $report_path $top_module _area.rep] { report_reference }
+redirect [format "%s%s%s" $report_path $top_module _power.rep] { report_power }
+redirect [format "%s%s%s" $report_path $top_module _scan_path.rep] { report_scan_path }
+redirect [format "%s%s%s" $report_path $top_module _timing.rep] \
+ { report_timing -path full -max_paths 100 -nets -transition_time -capacitance -significant_digits 3 -nosplit}
+
diff --git a/ASIC/28pin/Synopsys/upf/nanosoc_chip_pads.upf b/ASIC/28pin/Synopsys/upf/nanosoc_chip_pads.upf
new file mode 100644
index 0000000000000000000000000000000000000000..c6b9d33b87e24a28d6f60b9a88d1f65440e314bd
--- /dev/null
+++ b/ASIC/28pin/Synopsys/upf/nanosoc_chip_pads.upf
@@ -0,0 +1,57 @@
+#Scope: nanosoc_chip_pads
+create_supply_set VDDACC_VSS
+create_supply_set VDD_VSS
+
+#Domain: ACCEL
+create_power_domain ACCEL -supply {primary VDDACC_VSS} -elements {u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator}
+
+#Domain: TOP
+create_power_domain TOP -supply {primary VDD_VSS}
+
+associate_supply_set VDDACC_VSS -handle ACCEL.primary
+associate_supply_set VDD_VSS -handle TOP.primary
+
+create_supply_port VDDACC
+create_supply_port VDD
+create_supply_port VSS
+
+create_supply_net VDDACC
+create_supply_net VDD
+create_supply_net VSS
+
+connect_supply_net VDD -ports VDD
+connect_supply_net VDDACC -ports VDDACC
+connect_supply_net VSS -ports VSS
+
+
+create_supply_set VDDACC_VSS -function {power VDDACC} -function {ground VSS} -update
+create_supply_set VDD_VSS -function {power VDD} -function {ground VSS} -update
+
+
+connect_supply_net VDD -ports u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/u_rf_sp_hdf/VDD
+connect_supply_net VDD -ports u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/u_rf_sp_hdf/VDD
+connect_supply_net VDD -ports u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/u_rf_sp_hdf/VDD
+connect_supply_net VDD -ports u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/u_rf_sp_hdf/VDD
+connect_supply_net VDD -ports u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom/VDDE
+
+connect_supply_net VSS -ports u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/u_rf_sp_hdf/VSS
+connect_supply_net VSS -ports u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/u_rf_sp_hdf/VSS
+connect_supply_net VSS -ports u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/u_rf_sp_hdf/VSS
+connect_supply_net VSS -ports u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/u_rf_sp_hdf/VSS
+connect_supply_net VSS -ports u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom/VSSE
+
+add_port_state VSS -state {state1 0.00}
+add_port_state VDD -state {state1 1.08}
+add_port_state VDDACC -state {state1 1.08}
+
+create_pst all_pst -supplies { \
+ VDDACC \
+ VDD \
+ VSS}
+add_pst_state aon -pst all_pst -state {state1}
+
+
+
+
+
+
diff --git a/ASIC/Cadence/Innovus/nanosoc.cpf b/ASIC/44pin/Cadence/cpf/nanosoc.cpf
similarity index 84%
rename from ASIC/Cadence/Innovus/nanosoc.cpf
rename to ASIC/44pin/Cadence/cpf/nanosoc.cpf
index 90fb37fff35a8d860d293a3d6e01f8024c4b70bf..f57a1ace58fd7473ee19d4cfe46bf7c5f776edf8 100644
--- a/ASIC/Cadence/Innovus/nanosoc.cpf
+++ b/ASIC/44pin/Cadence/cpf/nanosoc.cpf
@@ -2,7 +2,7 @@ set_cpf_version 1.1
set_design nanosoc_chip_pads
create_power_domain -name TOP -default
-create_power_domain -name ACCEL -instances u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator
+create_power_domain -name ACCEL -instances u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator
create_nominal_condition -name nom -voltage 1.08
diff --git a/ASIC/44pin/Cadence/cpf/nanosoc_imp.cpf b/ASIC/44pin/Cadence/cpf/nanosoc_imp.cpf
new file mode 100644
index 0000000000000000000000000000000000000000..e0869e5a6bcf67fcaf3452a006aac49192bfcc45
--- /dev/null
+++ b/ASIC/44pin/Cadence/cpf/nanosoc_imp.cpf
@@ -0,0 +1,19 @@
+set_cpf_version 1.1
+
+set_design nanosoc_chip_pads
+create_power_domain -name TOP -default
+create_power_domain -name ACCEL -instances u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator
+
+create_nominal_condition -name nom -voltage 1.08
+
+create_power_mode -name PM -domain_conditions {TOP@nom ACCEL@nom} -default
+
+create_ground_nets -nets VSS
+create_power_nets -nets VDD
+create_power_nets -nets VDDACC
+
+update_power_domain -name TOP -primary_power_net VDD -primary_ground_net VSS
+update_power_domain -name ACCEL -primary_power_net VDDACC -primary_ground_net VSS
+
+
+end_design
\ No newline at end of file
diff --git a/ASIC/44pin/Cadence/scripts/clock_tree_synthesis.tcl b/ASIC/44pin/Cadence/scripts/clock_tree_synthesis.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..5e8a3ed93fd8086727b0177c8e084b12b46066a8
--- /dev/null
+++ b/ASIC/44pin/Cadence/scripts/clock_tree_synthesis.tcl
@@ -0,0 +1,23 @@
+############################################
+# Script : Clock Tree Implementation
+# Date : 24th May 2023
+# Author : Srimanth Tenneti
+# Description : Implements the Clock Tree
+############################################
+
+### Buffer Cells
+set_db cts_buffer_cells {*BUFH*}
+### Inverter Cells
+set_db cts_inverter_cells {*INV*}
+
+### Clock Tree Sepc
+create_clock_tree_spec -out_file design_clk.spec
+
+### Creating a Clock Tree
+ccopt_design
+
+### Optimizing the design
+opt_design -post_cts
+opt_design -post_cts -hold
+
+
diff --git a/ASIC/44pin/Cadence/scripts/design_import.tcl b/ASIC/44pin/Cadence/scripts/design_import.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..894dd9294213613683a98cfcf2af167b3f074ee8
--- /dev/null
+++ b/ASIC/44pin/Cadence/scripts/design_import.tcl
@@ -0,0 +1,48 @@
+#########################################
+# File : Design Import Logic
+# Date : 22nd May 2022
+# Author : Srimanth Tenneti
+# Description : MMMC + Design Import
+#########################################
+
+### Settting PG Nets
+set_db init_power_nets {VDD VDDIO VDDACC}
+set_db init_ground_nets {VSS VSSIO}
+
+### Processing MMMC
+read_mmmc nanosoc.mmmc
+
+# Set library paths
+# !! EDIT THIS TO YOUR PATHS IN YOUR ENVIRONMENT
+set TECH_LEF $::env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/lef/1p9m_6x2z/sc12_tech.lef
+set BASE_LEF $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lef/sc12_cln65lp_base_rvt.lef
+set IO_PAD_LEF /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Backend/lef/tpbn65v_9lm.lef
+set IO_PAD_DRIVER_LEF /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Backend/lef/tpdn65lpnv2od3_9lm.lef
+
+
+# !! THESE SHOULD BE CORRECT FOR ANY ENVIRONMENT AS THEY ARE GENERATED BY MAKEFILE
+set RF_LEF $::env(SOCLABS_PROJECT_DIR)/memories/rf_16k/rf_16k.lef
+set ROM_LEF $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via.lef
+
+### Reading LEFs
+read_physical -lef [list ${TECH_LEF} ${BASE_LEF} ${IO_PAD_LEF} ${IO_PAD_DRIVER_LEF} ${RF_LEF} ${ROM_LEF}]
+
+### Reading Netlist
+read_netlist $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.v
+
+### Read DEF scan chain
+#read_def $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.def
+
+### Initializing the Design
+init_design
+
+### Adjusting the GUI
+gui_fit
+
+ungroup u_nanosoc_chip_u_system
+
+create_floorplan -core_margins_by die -flip s -site sc12_cln65lp -die_size 1000.0 1500.0 150.0 150.0 150.0 150.0
+
+read_power_intent -cpf ../cpf/nanosoc_imp.cpf
+
+
diff --git a/ASIC/44pin/Cadence/scripts/genus.tcl b/ASIC/44pin/Cadence/scripts/genus.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..a163ff82f46e0a33125d2125559285416ddb16a2
--- /dev/null
+++ b/ASIC/44pin/Cadence/scripts/genus.tcl
@@ -0,0 +1,71 @@
+set_db init_lib_search_path "/home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a/ $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lib/ $::env(SOCLABS_PROJECT_DIR)/memories/rf_16k/ $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/"
+set BASE_LIB sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.lib
+set RF_LIB rf_16k_ss_1p08v_1p08v_125c.lib
+set ROM_LIB rom_via_ss_1p08v_1p08v_125c.lib
+set IO_PAD_DRIVER tpdn65lpnv2od3bc.lib
+create_library_domain domain1
+set_db [get_db library_domains domain1] .library "$BASE_LIB $RF_LIB $ROM_LIB $IO_PAD_DRIVER"
+
+read_power_intent -cpf -module nanosoc_chip_pads ../cpf/nanosoc.cpf
+
+source $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/genus_flist.tcl
+elaborate nanosoc_chip_pads
+
+apply_power_intent
+check_library > lib_check.log
+
+check_cpf
+
+commit_power_intent
+check_power_structure -license lpgxl
+
+read_sdc $::env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/constraints.sdc
+
+#set_db dft_scan_style muxed_scan
+#set_db design:nanosoc_chip_pads .dft_min_number_of_scan_chains 1
+
+#read_dft_abstract_model nanosoc_dft_abstract_model
+#define_test_signal -name TEST -active high -function test_mode -index 0 TEST
+#define_test_signal -name SWDCK -active high -function scan_clock -index 0 SWDCK
+#define_test_signal -name NRST -active low -function async_set_reset -index 0 NRST
+#define_test_signal -name SWDIO -active high -function shift_enable -default -index 0 SWDIO
+#define_test_signal -name CLK -active high -function test_clock -index 0 CLK
+
+#define_scan_chain -name chain_ACCEL -sdi DFT_SDI_1 -sdo DFT_SDO_1 -shared_output
+#define_scan_chain -name chain_TOP -sdi DFT_SDI_2 -sdo DFT_SDO_2 -shared_output
+
+
+#check_dft_rules
+#fix_dft_violations -test_control TEST -async_reset -add_observe_scan -scan_clock_pin SWDCK
+
+
+set_db syn_generic_effort high
+set_db syn_map_effort high
+
+syn_generic
+syn_map
+
+#convert_to_scan
+
+#connect_scan_chains -chains chain_ACCEL -power_domain ACCEL -incremental
+#connect_scan_chains -chains chain_TOP -power_domain TOP -incremental
+
+syn_opt
+
+report_area > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/syn_nanosoc_area_44pin.rep
+report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/syn_nanosoc_timing_44pin.rep
+report_gates > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/syn_nanosoc_gates_44pin.rep
+report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/syn_nanosoc_power_44pin.rep
+
+write_hdl > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.v
+write_hdl -pg > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.vp
+
+#report_scan_chains > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_chains_44pin.rep
+#report_scan_setup > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_setup_44pin.rep
+#report_scan_registers > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_registers_44pin.rep
+#write_dft_abstract_model > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_dft_abstract_model_44pin
+
+#write_dft_atpg_other_vendor -mentor > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_atpg_44pin
+
+#write_scandef > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.def
+
diff --git a/ASIC/44pin/Cadence/scripts/io_plan.tcl b/ASIC/44pin/Cadence/scripts/io_plan.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..44af39fd98971de0f20d3f086bab98b673c73bc6
--- /dev/null
+++ b/ASIC/44pin/Cadence/scripts/io_plan.tcl
@@ -0,0 +1,57 @@
+#-----------------------------------------------------------------------------
+# NanoSoC IO plan for PnR in cadence Innovus
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# Daniel Newbrook (d.newbrook@soton.ac.uk)
+#
+# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+
+delete_io_fillers -cell PCORNER
+delete_io_fillers -cell PFILLER20
+delete_io_fillers -cell PFILLER10
+delete_io_fillers -cell PFILLER5
+delete_io_fillers -cell PFILLER1
+delete_io_fillers -cell PFILLER05
+delete_io_fillers -cell PFILLER0005
+
+
+read_io_file nanosoc_io_plan.io
+
+add_io_fillers -cells PCORNER -prefix CORNER -side n -from -300 -to 300
+add_io_fillers -cells PCORNER -prefix CORNER -side e -from 500 -to 3000
+add_io_fillers -cells PCORNER -prefix CORNER -side s -from 500 -to 3000
+add_io_fillers -cells PCORNER -prefix CORNER -side w -from -300 -to 300
+
+add_io_fillers -cells PFILLER20 -prefix FILLER -side n
+add_io_fillers -cells PFILLER20 -prefix FILLER -side e
+add_io_fillers -cells PFILLER20 -prefix FILLER -side s
+add_io_fillers -cells PFILLER20 -prefix FILLER -side w
+
+add_io_fillers -cells PFILLER10 -prefix FILLER -side n
+add_io_fillers -cells PFILLER10 -prefix FILLER -side e
+add_io_fillers -cells PFILLER10 -prefix FILLER -side s
+add_io_fillers -cells PFILLER10 -prefix FILLER -side w
+
+add_io_fillers -cells PFILLER5 -prefix FILLER -side n
+add_io_fillers -cells PFILLER5 -prefix FILLER -side e
+add_io_fillers -cells PFILLER5 -prefix FILLER -side s
+add_io_fillers -cells PFILLER5 -prefix FILLER -side w
+
+add_io_fillers -cells PFILLER1 -prefix FILLER -side n
+add_io_fillers -cells PFILLER1 -prefix FILLER -side e
+add_io_fillers -cells PFILLER1 -prefix FILLER -side s
+add_io_fillers -cells PFILLER1 -prefix FILLER -side w
+
+add_io_fillers -cells PFILLER05 -prefix FILLER -side n
+add_io_fillers -cells PFILLER05 -prefix FILLER -side e
+add_io_fillers -cells PFILLER05 -prefix FILLER -side s
+add_io_fillers -cells PFILLER05 -prefix FILLER -side w
+
+add_io_fillers -cells PFILLER0005 -prefix FILLER -side n
+add_io_fillers -cells PFILLER0005 -prefix FILLER -side e
+add_io_fillers -cells PFILLER0005 -prefix FILLER -side s
+add_io_fillers -cells PFILLER0005 -prefix FILLER -side w
\ No newline at end of file
diff --git a/ASIC/Cadence/Innovus/nanosoc.mmmc b/ASIC/44pin/Cadence/scripts/nanosoc.mmmc
similarity index 86%
rename from ASIC/Cadence/Innovus/nanosoc.mmmc
rename to ASIC/44pin/Cadence/scripts/nanosoc.mmmc
index 70db329b1dee548ccde34f34ad27202a260d6999..b8c9c0d00a814a59bdc8cd00c94513228643aa60 100644
--- a/ASIC/Cadence/Innovus/nanosoc.mmmc
+++ b/ASIC/44pin/Cadence/scripts/nanosoc.mmmc
@@ -2,18 +2,19 @@ set phys_lib /research/AAA/phys_ip_library
set base_path ${phys_lib}/arm/tsmc/cln65lp/sc12_base_rvt/r0p0
set tech_path ${phys_lib}/arm/tsmc/cln65lp/arm_tech/r2p0
-set ram_path /home/dwn1c21/SoC-Labs/accelerator-project/memories/rf/
+set ram_path /home/dwn1c21/SoC-Labs/accelerator-project/memories/rf_16k/
set rom_path /home/dwn1c21/SoC-Labs/accelerator-project/memories/bootrom/
+set IO_driver_path /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a/
create_library_set -name default_libset_max\
-timing\
- [list ${base_path}/lib/sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.lib ${ram_path}/rf_sp_hdf_ss_1p08v_1p08v_125c.lib ${rom_path}/rom_via_ss_1p08v_1p08v_125c.lib] \
+ [list ${base_path}/lib/sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.lib ${ram_path}/rf_16k_ss_1p08v_1p08v_125c.lib ${rom_path}/rom_via_ss_1p08v_1p08v_125c.lib ${IO_driver_path}/tpdn65lpnv2od3wc.lib] \
-si\
[list ${base_path}/celtic/sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.cdB]
create_library_set -name default_libset_min\
-timing\
- [list ${base_path}/lib/sc12_cln65lp_base_rvt_ff_typical_min_1p32v_m40c.lib ${ram_path}/rf_sp_hdf_ff_1p32v_1p32v_m40c.lib ${rom_path}/rom_via_ff_1p32v_1p32v_m40c.lib] \
+ [list ${base_path}/lib/sc12_cln65lp_base_rvt_ff_typical_min_1p32v_m40c.lib ${ram_path}/rf_16k_ff_1p32v_1p32v_m40c.lib ${rom_path}/rom_via_ff_1p32v_1p32v_m40c.lib ${IO_driver_path}/tpdn65lpnv2od3bc.lib] \
-si\
[list ${base_path}/celtic/sc12_cln65lp_base_rvt_ff_typical_min_1p32v_m40c.cdB]
@@ -69,7 +70,7 @@ create_delay_corner -name default_delay_corner_min\
create_constraint_mode -name default_constraint_mode\
-sdc_files\
- [list ../../constraints.sdc]
+ [list ../../../constraints.sdc]
create_analysis_view -name default_analysis_view_setup -constraint_mode default_constraint_mode -delay_corner default_delay_corner_max
diff --git a/ASIC/44pin/Cadence/scripts/nanosoc_io_plan.io b/ASIC/44pin/Cadence/scripts/nanosoc_io_plan.io
new file mode 100644
index 0000000000000000000000000000000000000000..b0f704a0cedbce4c3e50188506f7efec4f15190f
--- /dev/null
+++ b/ASIC/44pin/Cadence/scripts/nanosoc_io_plan.io
@@ -0,0 +1,66 @@
+###############################################################
+# Generated by: Cadence Innovus 21.11-s130_1
+# OS: Linux x86_64(Host ID srv03335)
+# Generated on: Thu Nov 16 16:18:31 2023
+# Design: nanosoc_chip_pads
+# Command: write_io_file -locations -template nanosoc_chip_pads.save.io
+###############################################################
+
+(globals
+ version = 3
+ io_order = default
+)
+(iopad
+ (top
+ (inst name="uPAD_TEST_I" offset=149.29)
+ (inst name="uPAD_SWDCK_I" offset=257.86 place_status=placed )
+ (inst name="uPAD_VDD_3" offset=366.43 place_status=placed )
+ (inst name="uPAD_VSS_3" offset=475.00 place_status=placed )
+ (inst name="uPAD_VDDIO_3" offset=583.57 place_status=placed )
+ (inst name="uPAD_P1_00" offset=692.14 place_status=placed )
+ (inst name="uPAD_P1_01" offset=800.71 place_status=placed )
+ )
+ (left
+ (inst name="uPAD_P0_04" offset=153.67 place_status=placed )
+ (inst name="uPAD_P0_05" offset=271.00 place_status=placed )
+ (inst name="RESERVED " offset=388.33 place_status=placed )
+ (inst name="RESERVED " offset=505.67 place_status=placed )
+ (inst name="uPAD_P0_03" offset=149.29 place_status=placed )
+ (inst name="uPAD_VDDACC_0" offset=257.86 place_status=placed )
+ (inst name="uPAD_VSS_0" offset=366.43 place_status=placed )
+ (inst name="uPAD_CLK_I" offset=475.00 place_status=placed )
+ (inst name="uPAD_VDD_0" offset=583.57 place_status=placed )
+ (inst name="uPAD_VDDIO_0" offset=692.14 place_status=placed )
+ (inst name="uPAD_SWDIO_IO" offset=800.71 place_status=placed )
+ (inst name="uPAD_VSSIO_0" offset=1444.33 place_status=placed )
+ (inst name="RESERVED " offset=1561.67 place_status=placed )
+ (inst name="uPAD_P0_06" offset=1679.00 place_status=placed )
+ (inst name="uPAD_P0_07" offset=1796.33 place_status=placed )
+ )
+ (bottom
+ (inst name="uPAD_P0_02" offset=149.29 place_status=placed )
+ (inst name="uPAD_VDDACC_1" offset=257.86 place_status=placed )
+ (inst name="uPAD_VDDIO_1" offset=366.43 place_status=placed )
+ (inst name="uPAD_VDD_1" offset=475.00 place_status=placed )
+ (inst name="uPAD_VSS_1" offset=583.57 place_status=placed )
+ (inst name="uPAD_P0_01" offset=692.14 place_status=placed )
+ (inst name="uPAD_P0_00" offset=800.71 )
+ )
+ (right
+ (inst name="uPAD_P1_07" offset=153.67 place_status=placed )
+ (inst name="uPAD_P1_06" offset=271.00 place_status=placed )
+ (inst name="RESERVED " offset=388.33 place_status=placed )
+ (inst name="uPAD_VSSIO_1" offset=505.67 place_status=placed )
+ (inst name="uPAD_P1_03" offset=149.29 place_status=placed )
+ (inst name="uPAD_P1_02" offset=257.86 place_status=placed )
+ (inst name="uPAD_VDDACC_2" offset=366.43 place_status=placed )
+ (inst name="uPAD_VDD_2" offset=475.00 place_status=placed )
+ (inst name="uPAD_VSS_2" offset=583.57 place_status=placed )
+ (inst name="uPAD_VDDIO_2" offset=692.14 place_status=placed )
+ (inst name="uPAD_NRST_I" offset=800.71 place_status=placed )
+ (inst name="RESERVED " offset=1444.33 place_status=placed )
+ (inst name="RESERVED " offset=1561.67 place_status=placed )
+ (inst name="uPAD_P1_04" offset=1679.00 place_status=placed )
+ (inst name="uPAD_P1_05" offset=1796.33 place_status=placed )
+ )
+)
diff --git a/ASIC/44pin/Cadence/scripts/place.tcl b/ASIC/44pin/Cadence/scripts/place.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..9f25bb8c140db90cffb66fa2308fecdb43ff2be2
--- /dev/null
+++ b/ASIC/44pin/Cadence/scripts/place.tcl
@@ -0,0 +1,21 @@
+############################################
+# Script : Placement
+# Date : May 24 2024
+# Author : Srimanth Tenneti
+############################################
+
+### Congestion and Timing Setting
+set_db design_process_node 65
+set_db place_global_cong_effort auto
+set_db place_global_timing_effort high
+
+### Uniform Cell Distribution
+
+set_db place_global_uniform_density true
+
+### Placement Mode Config
+set_db place_design_floorplan_mode false
+place_opt_design
+
+### Delay Calculation
+write_sdf design.sdf -ideal_clock_network
diff --git a/ASIC/44pin/Cadence/scripts/place_macros.tcl b/ASIC/44pin/Cadence/scripts/place_macros.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..e2f219b527c3db49311f745228ee0f06b5cd06c3
--- /dev/null
+++ b/ASIC/44pin/Cadence/scripts/place_macros.tcl
@@ -0,0 +1,29 @@
+#------------------------------------------------------------------------------------
+# Cadence Innovus: Place macros
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# Daniel Newbrook (d.newbrook@soton.ac.uk)
+# Copyright (c) 2023, SoC Labs (www.soclabs.org)
+#------------------------------------------------------------------------------------
+
+# relative floorplan
+delete_relative_floorplan -all
+create_relative_floorplan -ref_type core_boundary -horizontal_edge_separate {1 -4.8 1} -vertical_edge_separate {2 -2.4 2} -place u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf
+create_relative_floorplan -ref_type object -horizontal_edge_separate {3 -12 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf
+create_relative_floorplan -ref_type object -horizontal_edge_separate {3 -12 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system_u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf
+create_relative_floorplan -ref_type object -orient R0 -horizontal_edge_separate {3 -12 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system_u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system_u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf
+create_relative_floorplan -ref_type core_boundary -orient R0 -horizontal_edge_separate {1 -4.8 1} -vertical_edge_separate {0 2.4 0} -place u_nanosoc_chip_u_system_u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom
+
+move_obj u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -point {500 500}
+update_floorplan_obj -obj u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -rects {150 150 500 351.6}
+add_fences -hinst u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -min_gap 5
+create_partition -hinst u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -core_spacing 2.0 2.0 2.0 2.0 -rail_width 0.0 -min_pitch_left 2 -min_pitch_right 2 -min_pitch_top 2 -min_pitch_bottom 2 -reserved_layer { 1 2 3 4 5 6 7 8 9 10} -pin_layer_top { 2 4 6 8 10} -pin_layer_left { 3 5 7 9} -pin_layer_bottom { 2 4 6 8 10} -pin_layer_right { 3 5 7 9} -place_halo 2 2 2 2 -route_halo 2.0 -route_halo_top_layer 5 -route_halo_bottom_layer 1
+
+create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf
+create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf
+create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system_u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf
+create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system_u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_genblk1.u_rf_sp_hdf
+create_place_halo -halo_deltas {4.8 4.8 2.4 4.8} -insts u_nanosoc_chip_u_system_u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom
+0
\ No newline at end of file
diff --git a/ASIC/44pin/Cadence/scripts/pnr_flow.tcl b/ASIC/44pin/Cadence/scripts/pnr_flow.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..35ff13fa2ea91a308bf9500f2be21295967f400d
--- /dev/null
+++ b/ASIC/44pin/Cadence/scripts/pnr_flow.tcl
@@ -0,0 +1,76 @@
+######################################
+# Script : Place and Route Flow
+# Date : 25th May 2023
+# Author : Srimanth Tenneti
+# Description : Innovus PnR Flow
+######################################
+
+puts "Starting PnR Flow ..."
+
+
+### Design Import
+source design_import.tcl
+
+### IO Planning
+source io_plan.tcl
+
+commit_power_intent
+check_power_domains
+### Memory and accelerator placement
+source place_macros.tcl
+
+### Power Plan
+source power_plan.tcl
+
+### Power Route
+source power_route.tcl
+
+report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/1pre_place_nanosoc_imp_timing.rep
+
+### Placement
+source place.tcl
+
+report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/2post_place_nanosoc_imp_timing.rep
+
+
+uniquify nanosoc_chip_pads -verbose
+### CTS
+source clock_tree_synthesis.tcl
+
+report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/3post_clock_nanosoc_imp_timing.rep
+
+### Add filler cells
+eval_legacy { addFiller -cell FILL128_A12TR WELLANTENNATIEPW2_A12TR FILLTIE8_A12TR FILLTIE64_A12TR FILLTIE4_A12TR FILLTIE32_A12TR FILLTIE2_A12TR FILLTIE16_A12TR FILLTIE128_A12TR FILLCAPTIE8_A12TR -prefix FILLER -powerDomain ACCEL -doDRC }
+eval_legacy { addFiller -cell WELLANTENNATIEPW2_A12TR FILLTIE8_A12TR FILLTIE64_A12TR FILLTIE4_A12TR FILLTIE32_A12TR FILLTIE2_A12TR FILLTIE16_A12TR FILLTIE128_A12TR FILLCAPTIE8_A12TR -prefix FILLER -powerDomain TOP -doDRC }
+
+
+### Routing
+source route.tcl
+
+report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/4post_route_nanosoc_imp_timing.rep
+
+check_antenna
+
+### Fill metal
+set_metal_fill -layer M1 -opc_active_spacing 0.090 -border_spacing -0.001
+set_metal_fill -layer M2 -opc_active_spacing 0.100 -border_spacing -0.001
+set_metal_fill -layer M3 -opc_active_spacing 0.100 -border_spacing -0.001
+set_metal_fill -layer M4 -opc_active_spacing 0.100 -border_spacing -0.001
+set_metal_fill -layer M5 -opc_active_spacing 0.100 -border_spacing -0.001
+set_metal_fill -layer M6 -opc_active_spacing 0.100 -border_spacing -0.001
+set_metal_fill -layer M7 -opc_active_spacing 0.100 -border_spacing -0.001
+set_metal_fill -layer M8 -opc_active_spacing 0.400 -border_spacing -0.001
+set_metal_fill -layer M9 -opc_active_spacing 0.400 -border_spacing -0.001
+set_metal_fill -layer AP -opc_active_spacing 2.000 -border_spacing -0.001
+add_metal_fill -layers { M1 M2 M3 M4 M5 M6 M7 M8 M9 AP } -nets { VSSIO VSS VDDACC VDDIO VDD }
+
+
+report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_timing.rep
+report_area > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_area.rep
+report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_power.rep
+
+gui_show
+
+
+
+
diff --git a/ASIC/44pin/Cadence/scripts/power_plan.tcl b/ASIC/44pin/Cadence/scripts/power_plan.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..5895c391175d676798896d0d738044b37a2073e0
--- /dev/null
+++ b/ASIC/44pin/Cadence/scripts/power_plan.tcl
@@ -0,0 +1,86 @@
+#########################################
+# Script : Power Planning
+# Tool : Cadence Innovus
+# Date : May 22, 2023
+# Author : Srimanth Tenneti
+#########################################
+
+### Connecting Global Nets
+connect_global_net VDD -type pg_pin -pin_base_name VDD -inst_base_name *
+connect_global_net VDDIO -type pg_pin -pin_base_name VDDIO -inst_base_name *
+connect_global_net VSS -type pg_pin -pin_base_name VSS -inst_base_name *
+connect_global_net VSSIO -type pg_pin -pin_base_name VSSIO -inst_base_name *
+connect_global_net VDDACC -type pg_pin -pin_base_name VDD -inst_base_name {} -hinst u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -override
+### Top and Bottom Metal Declartions
+set_db add_rings_stacked_via_top_layer M8
+set_db add_rings_stacked_via_bottom_layer M1
+
+### Adding Rings
+add_rings -nets {VDD VDDACC VSS} -type core_rings -follow core -layer {top M9 bottom M9 left M8 right M8} -width {top 8 bottom 8 left 8 right 8} -spacing {top 2 bottom 2 left 2 right 2} -offset {top 3 bottom 3 left 3 right 3} -center 0 -threshold 0 -jog_distance 0 -snap_wire_center_to_grid none
+
+### Adding Stripes
+set_db add_stripes_ignore_block_check true
+set_db add_stripes_break_at none
+set_db add_stripes_route_over_rows_only false
+set_db add_stripes_rows_without_stripes_only false
+set_db add_stripes_extend_to_closest_target none
+set_db add_stripes_stop_at_last_wire_for_area false
+set_db add_stripes_partial_set_through_domain true
+set_db add_stripes_ignore_non_default_domains false
+set_db add_stripes_trim_antenna_back_to_shape none
+set_db add_stripes_spacing_type edge_to_edge
+set_db add_stripes_spacing_from_block 0
+set_db add_stripes_stripe_min_length stripe_width
+set_db add_stripes_stacked_via_top_layer AP
+set_db add_stripes_stacked_via_bottom_layer M1
+set_db add_stripes_via_using_exact_crossover_size false
+set_db add_stripes_split_vias false
+set_db add_stripes_orthogonal_only true
+set_db add_stripes_allow_jog { padcore_ring block_ring }
+set_db add_stripes_skip_via_on_pin { standardcell }
+set_db add_stripes_skip_via_on_wire_shape { noshape }
+add_stripes -nets {VDD VDDACC VSS} -layer M6 -direction vertical -width 1.8 -spacing 0.8 -set_to_set_distance 60 -extend_to all_domains -start_from left -start_offset 50 -stop_offset 0 -switch_layer_over_obs false -max_same_layer_jog_length 2 -pad_core_ring_top_layer_limit AP -pad_core_ring_bottom_layer_limit M1 -block_ring_top_layer_limit AP -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none
+
+deselect_obj -all
+
+# Connect Accelerator region
+select_obj u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator
+set_db add_stripes_ignore_block_check true
+set_db add_stripes_break_at none
+set_db add_stripes_route_over_rows_only false
+set_db add_stripes_rows_without_stripes_only false
+set_db add_stripes_extend_to_closest_target stripe
+set_db add_stripes_stop_at_last_wire_for_area false
+set_db add_stripes_partial_set_through_domain true
+set_db add_stripes_ignore_non_default_domains false
+set_db add_stripes_trim_antenna_back_to_shape none
+set_db add_stripes_spacing_type edge_to_edge
+set_db add_stripes_spacing_from_block 0
+set_db add_stripes_stripe_min_length stripe_width
+set_db add_stripes_stacked_via_top_layer AP
+set_db add_stripes_stacked_via_bottom_layer M4
+set_db add_stripes_via_using_exact_crossover_size false
+set_db add_stripes_split_vias false
+set_db add_stripes_orthogonal_only true
+set_db add_stripes_allow_jog { padcore_ring block_ring }
+set_db add_stripes_skip_via_on_pin { standardcell }
+set_db add_stripes_skip_via_on_wire_shape { noshape }
+add_stripes -nets {VDDACC VSS} -layer M9 -direction horizontal -width 1 -spacing 0.5 -set_to_set_distance 50 -over_power_domain 1 -start_from bottom -start_offset 15 -stop_offset 0 -switch_layer_over_obs false -max_same_layer_jog_length 2 -pad_core_ring_top_layer_limit AP -pad_core_ring_bottom_layer_limit M1 -block_ring_top_layer_limit AP -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none
+
+deselect_obj -all
+
+# connect Macros
+select_obj [ list u_nanosoc_chip_u_system_u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_u_rf_sp_hdf u_nanosoc_chip_u_system_u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_u_rf_sp_hdf u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_u_rf_sp_hdf u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_u_rf_sp_hdf u_nanosoc_chip_u_system_u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom]
+set_db add_stripes_ignore_block_check false
+set_db add_stripes_break_at none
+set_db add_stripes_route_over_rows_only false
+set_db add_stripes_rows_without_stripes_only false
+set_db add_stripes_extend_to_closest_target stripe
+add_stripes -nets {VDD VSS} -layer M5 -direction horizontal -width 1 -spacing 0.5 -set_to_set_distance 15 -over_power_domain 1 -start_from bottom -start_offset 8 -stop_offset 0 -switch_layer_over_obs false -merge_stripes_value 500 -max_same_layer_jog_length 2 -pad_core_ring_top_layer_limit AP -pad_core_ring_bottom_layer_limit M1 -block_ring_top_layer_limit AP -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none
+
+deselect_obj -all
+
+# Add END CAPS
+add_endcaps -start_row_cap ENDCAPTIE2_A12TR -end_row_cap ENDCAPTIE2_A12TR -prefix ENDCAP
+add_endcaps -power_domain ACCEL -start_row_cap ENDCAPTIE2_A12TR -end_row_cap ENDCAPTIE2_A12TR -prefix ENDCAP
+
diff --git a/ASIC/44pin/Cadence/scripts/power_route.tcl b/ASIC/44pin/Cadence/scripts/power_route.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..bf05e721f3b978bfc85e3b7aa790c38c7ccce5a8
--- /dev/null
+++ b/ASIC/44pin/Cadence/scripts/power_route.tcl
@@ -0,0 +1,12 @@
+##################################
+# Script : Special Route Script
+# Date : May 24, 2023
+# Description : Power Routing
+# Author : Srimanth Tenneti
+##################################
+route_special -connect {pad_pin pad_ring} -layer_change_range { M1(1) AP(10) } -block_pin_target nearest_target -pad_pin_port_connect {all_port all_geom} -pad_pin_target nearest_target -allow_jogging 1 -crossover_via_layer_range { M1(1) AP(10) } -nets { VDD VSS VDDACC } -allow_layer_change 1 -pad_pin_width 6 -target_via_layer_range { M1(1) AP(10) }
+
+route_special -connect {block_pin core_pin floating_stripe} -layer_change_range { M1(1) AP(10) } -block_pin_target nearest_target -pad_pin_port_connect {all_port one_geom} -pad_pin_target nearest_target -core_pin_target first_after_row_end -floating_stripe_target {block_ring pad_ring ring stripe ring_pin block_pin followpin} -allow_jogging 1 -power_domains { ACCEL } -crossover_via_layer_range { M1(1) AP(10) } -nets { VDDACC VSS } -allow_layer_change 1 -block_pin use_lef -target_via_layer_range { M1(1) AP(10) }
+route_special -connect {block_pin core_pin floating_stripe} -layer_change_range { M1(1) AP(10) } -block_pin_target nearest_target -pad_pin_port_connect {all_port one_geom} -pad_pin_target nearest_target -core_pin_target first_after_row_end -floating_stripe_target {block_ring pad_ring ring stripe ring_pin block_pin followpin} -allow_jogging 1 -power_domains { TOP } -crossover_via_layer_range { M1(1) AP(10) } -nets { VDD VSS } -allow_layer_change 1 -block_pin use_lef -target_via_layer_range { M1(1) AP(10) }
+
+#route_special -nets {VDD VSS} -connect core_pin -block_pin_target nearest_target -core_pin_target first_after_row_end -allow_jogging 1 -allow_layer_change 1 -layer_change_range { M1(1) M8(8) } -crossover_via_layer_range { M1(1) M8(8) } -target_via_layer_range { M1(1) M8(8) }
diff --git a/ASIC/44pin/Cadence/scripts/route.tcl b/ASIC/44pin/Cadence/scripts/route.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..b12b0975739e80b149b89b66e2ddee6a57df17b5
--- /dev/null
+++ b/ASIC/44pin/Cadence/scripts/route.tcl
@@ -0,0 +1,18 @@
+
+### Clock Net Spacing
+set_route_attributes -nets clk -preferred_extra_space_tracks 2
+
+### Multi Cut Via Effort
+set_db route_design_detail_use_multi_cut_via_effort medium
+
+### Timing Driven Route
+set_db route_design_with_timing_driven 1
+
+### SI Driven Route
+set_db route_design_with_si_driven 1
+
+### Route Design
+route_design -global_detail
+
+### Timing Analysis Type
+set_db timing_analysis_type ocv
diff --git a/ASIC/44pin/Synopsys/scripts/fm_shell.tcl b/ASIC/44pin/Synopsys/scripts/fm_shell.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..87b374118661e041b6400a887e943cee8c4b3b00
--- /dev/null
+++ b/ASIC/44pin/Synopsys/scripts/fm_shell.tcl
@@ -0,0 +1,28 @@
+
+set_mismatch_message_filter -warn FMR_ELAB-147
+set_svf -append $env(SOCLABS_PROJECT_DIR)/nanosoc_tech/synthesis/default.svf
+set IO_FRONTEND_DIR /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a
+
+source $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/formality_flist.tcl
+read_db -r $env(SOCLABS_PROJECT_DIR)/memories/rf/rf_sp_hdf_ss_1p08v_1p08v_125c.db
+read_db -r $env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via_ss_1p08v_1p08v_125c.db
+read_db -r $IO_FRONTEND_DIR/tpdn65lpnv2od3wc.db
+set_top nanosoc_chip_pads
+
+# Read db files
+read_db -i $env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/db/sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.db
+read_db -i $env(SOCLABS_PROJECT_DIR)/memories/rf/rf_sp_hdf_ss_1p08v_1p08v_125c.db
+read_db -i $env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via_ss_1p08v_1p08v_125c.db
+read_db -i $IO_FRONTEND_DIR/tpdn65lpnv2od3wc.db
+# Read Gate netlist
+
+read_verilog -i $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads.vm
+
+set_top nanosoc_chip_pads
+
+match
+verify
+
+analyze_points -failing
+
+save_session nanosoc_chip_pads_formal_equivalence
\ No newline at end of file
diff --git a/ASIC/44pin/Synopsys/scripts/place_memories.tcl b/ASIC/44pin/Synopsys/scripts/place_memories.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..945dea4948d4d6a44e577323a1909c0629a8e6c6
--- /dev/null
+++ b/ASIC/44pin/Synopsys/scripts/place_memories.tcl
@@ -0,0 +1,16 @@
+set_macro_relative_location -target_object [get_cell {u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/u_rf_sp_hdf}] -target_orientation R0 -target_corner tr -anchor_corner tr -offset {-0.1 -0.47} -offset_type scalable
+set_macro_relative_location -target_object [get_cell {u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/u_rf_sp_hdf}] -target_orientation R0 -target_corner tr -anchor_corner tr -offset {-0.1 -0.67} -offset_type scalable
+set_macro_relative_location -target_object [get_cell {u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/u_rf_sp_hdf}] -target_orientation R0 -target_corner tr -anchor_corner tr -offset {-0.1 -0.05} -offset_type scalable
+set_macro_relative_location -target_object [get_cell {u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/u_rf_sp_hdf}] -target_orientation R0 -target_corner tr -anchor_corner tr -offset {-0.1 -0.27} -offset_type scalable
+set_macro_relative_location -target_object [get_cell {u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom}] -target_orientation R180 -target_corner br -anchor_corner br -offset {-0.15 0.1} -offset_type scalable
+create_macro_relative_location_placement
+
+set_attribute -objects [get_cells u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/u_rf_sp_hdf] -name physical_status -value fixed
+set_attribute -objects [get_cells u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/u_rf_sp_hdf] -name physical_status -value fixed
+set_attribute -objects [get_cells u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/u_rf_sp_hdf] -name physical_status -value fixed
+set_attribute -objects [get_cells u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/u_rf_sp_hdf] -name physical_status -value fixed
+set_attribute -objects [get_cells u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom] -name physical_status -value fixed
+
+create_keepout_margin -type hard -outer {5 5 5 5} [get_attribute [get_cells u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/u_rf_sp_hdf] ref_block];create_keepout_margin -type hard_macro -outer {5 5 5 5} [get_attribute [get_cells u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/u_rf_sp_hdf] ref_block];create_keepout_margin -type soft -outer {8 8 8 8} [get_attribute [get_cells u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/u_rf_sp_hdf] ref_block];
+create_keepout_margin -type hard -outer {5 5 5 5} [get_attribute [get_cells u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom] ref_block];create_keepout_margin -type hard_macro -outer {5 5 5 5} [get_attribute [get_cells u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom] ref_block];create_keepout_margin -type soft -outer {8 8 8 8} [get_attribute [get_cells u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom] ref_block];
+
diff --git a/ASIC/Synopsys/ICC2/place_pins.tcl b/ASIC/44pin/Synopsys/scripts/place_pins.tcl
similarity index 100%
rename from ASIC/Synopsys/ICC2/place_pins.tcl
rename to ASIC/44pin/Synopsys/scripts/place_pins.tcl
diff --git a/ASIC/44pin/Synopsys/scripts/pnr.tcl b/ASIC/44pin/Synopsys/scripts/pnr.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..9fdf34e618c2ad7f4241833932ac0a105fe334da
--- /dev/null
+++ b/ASIC/44pin/Synopsys/scripts/pnr.tcl
@@ -0,0 +1,153 @@
+#//-----------------------------------------------------------------------------
+#// PnR Flow script for Synopsys ICC2
+#// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#//
+#// Contributorss
+#//
+#// Daniel Newbrook (d.newbrook@soton.ac.uk)
+#//
+#// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+#//-----------------------------------------------------------------------------
+
+
+set design_name nanosoc_chip_pads
+
+# Edit these for your environment
+set PHYS_IP_DIR /research/AAA/phys_ip_library
+set MEM_DIR /home/dwn1c21/SoC-Labs/accelerator-project/memories
+set IO_BACKEND_DIR /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Backend/lef
+set IO_FRONTEND_DIR /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a
+
+set_app_var link_library [list $PHYS_IP_DIR/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/db/sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.db $MEM_DIR/bootrom/rom_via_ss_1p08v_1p08v_125c.db $MEM_DIR/rf/rf_sp_hdf_ss_1p08v_1p08v_125c.db $IO_FRONTEND_DIR/tpdn65lpnv2od3wc.db]
+create_lib tsmc65lp -technology $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/milkyway/1p9m_6x2z/sc12_tech.tf -ref_libs [list $PHYS_IP_DIR/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lef/sc12_cln65lp_base_rvt.lef $MEM_DIR/rf/rf_sp_hdf.lef $MEM_DIR/bootrom/rom_via.lef $IO_BACKEND_DIR/tpbn65v_9lm.lef $IO_BACKEND_DIR/tpdn65lpnv2od3_9lm.lef]
+
+read_parasitic_tech -name typical -tlup $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/typical.tluplus -layermap $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/tluplus.map
+read_parasitic_tech -name rcbest -tlup $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/rcbest.tluplus -layermap $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/tluplus.map
+read_parasitic_tech -name rcworst -tlup $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/rcworst.tluplus -layermap $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/tluplus.map
+
+
+read_verilog -library tsmc65lp -design nanosoc_chip_pads -top nanosoc_chip_pads $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/Synopsys/nanosoc_chip_pads.vp
+read_def $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/Synopsys/nanosoc_chip_pads.def
+link_block
+
+create_cell {PAD_CORNER_NE PAD_CORNER_SE PAD_CORNER_SW PAD_CORNER_NW} PCORNER
+
+initialize_floorplan -side_length {1500 1500} -core_offset {150}
+create_io_ring -name main_io
+explore_logic_hierarchy -organize
+
+# Place IO pins
+source place_pins.tcl
+
+# Power domains TOP ACCEL and MEM
+create_power_domain TOP
+create_power_domain ACCEL -elements {u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator}
+#VDD
+create_supply_port VDD
+create_supply_net VDD -domain TOP
+connect_supply_net VDD -ports VDD
+
+#VSS
+create_supply_port VSS
+create_supply_net VSS -domain TOP
+create_supply_net VSS -domain ACCEL -reuse
+connect_supply_net VSS -ports VSS
+
+#VDDACC
+create_supply_port VDDACC
+create_supply_net VDDACC -domain ACCEL
+connect_supply_net VDDACC -ports VDDACC
+
+
+#IO Supplies
+create_supply_port VDDIO -domain TOP
+connect_supply_net VDDIO -ports VDDIO
+
+set_domain_supply_net TOP -primary_power_net VDD -primary_ground_net VSS
+set_domain_supply_net ACCEL -primary_power_net VDDACC -primary_ground_net VSS
+# Create voltage and power region for accelerator
+create_voltage_area -power_domains ACCEL -power VDDACC -ground VSS -nwell VDDACC -pwell VSS -region {{{150 1050} {1100 1650}}} -name VA_ACCEL -cells [get_cells -physical_context -hierarchical \
+-regexp u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator/.*]
+create_pg_region {pg_ACCEL} -voltage_area VA_ACCEL -expand {0 10}
+
+create_pg_region {pg_TOP} -voltage_area DEFAULT_VA
+
+
+set_parasitic_parameters -early_spec rcbest -early_temperature -40 -late_spec rcworst -late_temperature 125
+current_corner default
+set_operating_conditions -max_library sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c -max ss_typical_max_1p08v_125c -min_library sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c -min ss_typical_max_1p08v_125c
+current_corner default
+set_parasitic_parameters -early_spec rcbest -early_temperature -40 -late_spec rcworst -late_temperature 125
+current_corner default
+set_operating_conditions -max_library sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c -max ss_typical_max_1p08v_125c -min_library sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c -min ss_typical_max_1p08v_125c
+current_mode default
+set_voltage 1.08 -corner [current_corner] -object_list [get_supply_nets VDD]
+set_voltage 1.08 -corner [current_corner] -object_list [get_supply_nets VDDACC]
+set_voltage 3.00 -corner [current_corner] -object_list [get_supply_nets VDDIO]
+set_voltage 0.00 -corner [current_corner] -object_list [get_supply_nets VSS]
+
+add_port_state VSS -state {on 0.0}
+add_port_state VDD -state {on 1.08}
+add_port_state VDDACC -state {on 1.08}
+add_port_state VDDIO -state {on 3.0}
+create_pst ao_pst -supplies {VSS VDD VDDACC VDDIO}
+add_pst_state ao -pst ao_pst -state {on on on on}
+
+commit_upf
+
+set_app_options -list {opt.timing.effort {medium}}
+set_app_options -list {clock_opt.place.effort {high}}
+set_app_options -list {place_opt.flow.clock_aware_placement {true}}
+set_app_options -list {place_opt.final_place.effort {high}}
+
+read_sdc $env(SOCLABS_PROJECT_DIR)/nanosoc_tech/ASIC/constraints.sdc
+update_timing
+
+
+
+change_selection [explore_logic_hierarchy -create_module_boundary]
+explore_logic_hierarchy -place
+
+#Place and fix memories with boundary
+source place_memories.tcl
+
+change_selection [explore_logic_hierarchy -create_module_boundary]
+explore_logic_hierarchy -place
+
+#Create power ring and straps
+source power_plan.tcl
+
+#Start Placement
+create_placement
+legalize_placement -cells [get_cells *]
+
+save_lib -all
+
+report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/1pre_opt_placement_timing.rep
+check_mv_design > check_mv_design.log
+
+report_utilization -of_objects [get_voltage_areas {DEFAULT_VA}] > check_util_default_va.log
+report_utilization -of_objects [get_voltage_areas {VA_ACCEL}] > check_util_va_accel.log
+
+
+place_opt
+save_lib -all
+
+update_timing -full
+report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/2post_opt_placement_timing.rep
+
+check_clock_trees -clocks clk
+synthesize_clock_trees -clocks clk
+clock_opt
+update_timing -full
+report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/3post_clock_opt_placement_timing.rep
+save_lib -all
+
+#Start Routing
+route_auto
+update_timing -full
+
+report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/final_timing.rep
+report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/final_power.rep
+save_lib -all
+exit
diff --git a/ASIC/44pin/Synopsys/scripts/power_plan.tcl b/ASIC/44pin/Synopsys/scripts/power_plan.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..f6a77a6e4dc3298d6ef81a9e5f8ab08466b54211
--- /dev/null
+++ b/ASIC/44pin/Synopsys/scripts/power_plan.tcl
@@ -0,0 +1,38 @@
+connect_pg_net -automatic
+
+# Create Outer core ring
+create_pg_ring_pattern ring_pattern -horizontal_layer M9 -horizontal_width {5} -horizontal_spacing {2} -vertical_layer M8 -vertical_width {5} -vertical_spacing {2}
+set_pg_strategy core_ring -pattern {{name:ring_pattern} {nets: {VDD VDDIO VDDACC VSS}}{offset: {3 3}}} -core
+
+# Create vertical straps in Nanosoc region
+create_pg_mesh_pattern strap_pattern -layers {{{vertical_layer: M6} {width: 1} {pitch: 50} {spacing: interleaving} {trim: false}}}
+set_pg_strategy M6_straps -voltage_areas VA_TOP -pattern {{name: strap_pattern}{nets: VDD VSS}} -extension {{{stop : outermost_ring}}} -blockage {{{pg_regions : {pg_ACCEL}}}}
+
+# Create std cell rails in Nanosoc Region
+create_pg_std_cell_conn_pattern rail_pattern -layers M5
+set_pg_strategy M5_rails -voltage_areas VA_TOP -pattern {{name: rail_pattern}{nets: VDD VSS}} -extension {{{stop : outermost_ring}}} -blockage {{{pg_regions : {pg_ACCEL}}}}
+
+# Create rails for macros
+create_pg_macro_conn_pattern sram_pg_mesh -pin_conn_type long_pin -nets {VDD VSS} -direction horizontal -layers M5 -width 0.64 -spacing interleaving -pitch 3 -pin_layers {M4} -via_rule {{intersection : all}}
+set_pg_strategy sram_pg_mesh -macros {u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/u_rf_sp_hdf u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom \
+u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/u_rf_sp_hdf u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/u_rf_sp_hdf \
+u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/u_rf_sp_hdf} -pattern {{name : sram_pg_mesh}{nets : {VDD VSS}}}
+
+
+# Create ring for Accelerator Region
+# create_pg_ring_pattern acc_ring_pattern -horizontal_layer M9 -horizontal_width {3} -horizontal_spacing {1} -vertical_layer M8 -vertical_width {3} -vertical_spacing {1}
+# set_pg_strategy acc_ring -voltage_areas VA_ACCEL -pattern {{name:acc_ring_pattern} {nets: {VDDACC VSS}}}
+
+# Create std cell rails in Accelerator region
+create_pg_std_cell_conn_pattern acc_rail_pattern -layers M5
+set_pg_strategy acc_rails -voltage_areas VA_ACCEL -pattern {{name:acc_rail_pattern}{nets:{VDDACC VSS}}} -extension {{{stop: first_target}}}
+
+# Create straps for Accelerator region
+create_pg_mesh_pattern acc_strap_pattern -layers {{vertical_layer : M8} {width : 1} {spacing : interleaving} {pitch : 50} {trim : false}}
+set_pg_strategy M8_straps_acc -voltage_areas VA_ACCEL -pattern {{name: acc_strap_pattern}{nets: VDDACC VSS}} -extension {{{stop : outermost_ring}}}
+
+create_pg_mesh_pattern acc_mesh_pattern -layers {{horizontal_layer : M9} {width : 1} {spacing : interleaving} {pitch : 50} {trim : false}}
+set_pg_strategy M9_mesh_acc -voltage_areas VA_ACCEL -pattern {{name: acc_mesh_pattern}{nets: VDDACC VSS}} -extension {{{stop : outermost_ring}}}
+
+# Compile all power strategies
+compile_pg -strategies {core_ring M6_straps M5_rails acc_rails M8_straps_acc M9_mesh_acc sram_pg_mesh}
\ No newline at end of file
diff --git a/ASIC/44pin/Synopsys/scripts/synopsys_lib_conversion.tcl b/ASIC/44pin/Synopsys/scripts/synopsys_lib_conversion.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..6cc53b16baabb3dfbe14e567433cad2985c23c81
--- /dev/null
+++ b/ASIC/44pin/Synopsys/scripts/synopsys_lib_conversion.tcl
@@ -0,0 +1,35 @@
+set RF_PATH $env(SOCLABS_PROJECT_DIR)/memories/rf
+
+read_lib $RF_PATH/rf_sp_hdf_ss_1p08v_1p08v_125c.lib
+write_lib RF_LIB_ss_1p08v_1p08v_125c -output $RF_PATH/rf_sp_hdf_ss_1p08v_1p08v_125c.db
+
+read_lib $RF_PATH/rf_sp_hdf_ss_1p08v_1p08v_m40c.lib
+write_lib RF_LIB_ss_1p08v_1p08v_m40c -output $RF_PATH/rf_sp_hdf_ss_1p08v_1p08v_m40c.db
+
+read_lib $RF_PATH/rf_sp_hdf_ff_1p32v_1p32v_125c.lib
+write_lib RF_LIB_ff_1p32v_1p32v_125c -output $RF_PATH/rf_sp_hdf_ff_1p32v_1p32v_125c.db
+
+read_lib $RF_PATH/rf_sp_hdf_ff_1p32v_1p32v_m40c.lib
+write_lib RF_LIB_ff_1p32v_1p32v_m40c -output $RF_PATH/rf_sp_hdf_ff_1p32v_1p32v_m40c.db
+
+read_lib $RF_PATH/rf_sp_hdf_tt_1p20v_1p20v_25c.lib
+write_lib RF_LIB_tt_1p20v_1p20v_25c -output $RF_PATH/rf_sp_hdf_tt_1p20v_1p20v_25c.db
+
+set ROM_PATH $env(SOCLABS_PROJECT_DIR)/memories/bootrom
+
+read_lib $ROM_PATH/rom_via_ss_1p08v_1p08v_125c.lib
+write_lib USERLIB_ss_1p08v_1p08v_125c -output $ROM_PATH/rom_via_ss_1p08v_1p08v_125c.db
+
+read_lib $ROM_PATH/rom_via_ss_1p08v_1p08v_m40c.lib
+write_lib USERLIB_ss_1p08v_1p08v_m40c -output $ROM_PATH/rom_via_ss_1p08v_1p08v_m40c.db
+
+read_lib $ROM_PATH/rom_via_ff_1p32v_1p32v_125c.lib
+write_lib USERLIB_ff_1p32v_1p32v_125c -output $ROM_PATH/rom_via_ff_1p32v_1p32v_125c.db
+
+read_lib $ROM_PATH/rom_via_ff_1p32v_1p32v_m40c.lib
+write_lib USERLIB_ff_1p32v_1p32v_m40c -output $ROM_PATH/rom_via_ff_1p32v_1p32v_m40c.db
+
+read_lib $ROM_PATH/rom_via_tt_1p20v_1p20v_25c.lib
+write_lib USERLIB_tt_1p20v_1p20v_25c -output $ROM_PATH/rom_via_tt_1p20v_1p20v_25c.db
+
+exit
\ No newline at end of file
diff --git a/ASIC/44pin/Synopsys/scripts/synthesis.tcl b/ASIC/44pin/Synopsys/scripts/synthesis.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..0cc586503340e59a0bc690c71a136c776098f60f
--- /dev/null
+++ b/ASIC/44pin/Synopsys/scripts/synthesis.tcl
@@ -0,0 +1,83 @@
+#-----------------------------------------------------------------------------
+# NanoSoC Synopsys synthesis tcl file to be run with dc_shell
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# Daniel Newbrook (d.newbrook@soton.ac.uk)
+#
+# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+set rtlPath $env(SOCLABS_PROJECT_DIR)
+set report_path $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/
+set top_module nanosoc_chip_pads
+set io_path /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a
+#supress_message = {ELAB-405}
+#####
+# Set search_path
+#
+# List locations where your standard cell libraries may be located
+#
+#####
+set search_path [list . $search_path $env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/sdb/ $env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/db/ $env(SOCLABS_PROJECT_DIR)/memories/rf $env(SOCLABS_PROJECT_DIR)/memories/bootrom $io_path]
+set search_path [concat $rtlPath $search_path]
+######
+# Set Target Library
+#
+# Set a default target library for Design Compiler to target when compiling a design
+#
+######
+set target_library "sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.db rf_sp_hdf_ss_1p08v_1p08v_125c.db rom_via_ss_1p08v_1p08v_125c.db tpdn65lpnv2od3wc.db"
+
+######
+# Set Link Library
+#
+# Set a default link library for Design Compiler to target when compiling a design
+#
+######
+set link_library "sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.db rf_sp_hdf_ss_1p08v_1p08v_125c.db rom_via_ss_1p08v_1p08v_125c.db tpdn65lpnv2od3wc.db"
+
+source $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/dc_flist.tcl
+elaborate $top_module -lib WORK
+current_design $top_module
+
+# Link Design
+link
+
+read_sdc ../../constraints.sdc
+
+load_upf ../nanosoc_chip_pads.upf
+
+set_voltage -object_list {VDD VDDACC VDD_VSS.power VDDACC_VSS.power TOP.primary.power ACCEL.primary.power} 1.08
+set_voltage -object_list {VSS VDD_VSS.ground VDDACC_VSS.ground TOP.primary.ground ACCEL.primary.ground} 0.00
+
+set_operating_conditions -library sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c ss_typical_max_1p08v_125c
+
+set_app_var compile_delete_unloaded_sequential_cells false
+compile_ultra -gate_clock -scan
+
+set_scan_configuration -chain_count 2
+set_dft_signal -view spec -type ScanDataIn -port DFT_SDI_1
+set_dft_signal -view spec -type ScanDataIn -port DFT_SDI_2
+set_dft_signal -view spec -type ScanDataOut -port DFT_SDO_1
+set_dft_signal -view spec -type ScanDataOut -port DFT_SDO_2
+set_dft_signal -view spec -type ScanEnable -port TEST -active_state 1
+set_dft_signal -view existing_dft -type Reset -port NRST -active_state 0
+set_scan_configuration -power_domain_mixing false
+create_test_protocol -infer_clock -infer_asynch
+dft_drc
+insert_dft
+
+write -hierarchy -format verilog -output $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/Synopsys/nanosoc_chip_pads.vm
+write -hierarchy -format verilog -pg -output $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/Synopsys/nanosoc_chip_pads.vp
+write_scan_def -output $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/Synopsys/nanosoc_chip_pads.def
+write_test_protocol -output $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/Synopsys/nanosoc_chip_pads_scan.stil
+
+redirect [format "%s%s%s" $report_path $top_module _area.rep] { report_area }
+redirect -append [format "%s%s%s" $report_path $top_module _area.rep] { report_reference }
+redirect [format "%s%s%s" $report_path $top_module _power.rep] { report_power }
+redirect [format "%s%s%s" $report_path $top_module _scan_path.rep] { report_scan_path }
+redirect [format "%s%s%s" $report_path $top_module _timing.rep] \
+ { report_timing -path full -max_paths 100 -nets -transition_time -capacitance -significant_digits 3 -nosplit}
+
diff --git a/ASIC/44pin/Synopsys/upf/nanosoc_chip_pads.upf b/ASIC/44pin/Synopsys/upf/nanosoc_chip_pads.upf
new file mode 100644
index 0000000000000000000000000000000000000000..c6b9d33b87e24a28d6f60b9a88d1f65440e314bd
--- /dev/null
+++ b/ASIC/44pin/Synopsys/upf/nanosoc_chip_pads.upf
@@ -0,0 +1,57 @@
+#Scope: nanosoc_chip_pads
+create_supply_set VDDACC_VSS
+create_supply_set VDD_VSS
+
+#Domain: ACCEL
+create_power_domain ACCEL -supply {primary VDDACC_VSS} -elements {u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator}
+
+#Domain: TOP
+create_power_domain TOP -supply {primary VDD_VSS}
+
+associate_supply_set VDDACC_VSS -handle ACCEL.primary
+associate_supply_set VDD_VSS -handle TOP.primary
+
+create_supply_port VDDACC
+create_supply_port VDD
+create_supply_port VSS
+
+create_supply_net VDDACC
+create_supply_net VDD
+create_supply_net VSS
+
+connect_supply_net VDD -ports VDD
+connect_supply_net VDDACC -ports VDDACC
+connect_supply_net VSS -ports VSS
+
+
+create_supply_set VDDACC_VSS -function {power VDDACC} -function {ground VSS} -update
+create_supply_set VDD_VSS -function {power VDD} -function {ground VSS} -update
+
+
+connect_supply_net VDD -ports u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/u_rf_sp_hdf/VDD
+connect_supply_net VDD -ports u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/u_rf_sp_hdf/VDD
+connect_supply_net VDD -ports u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/u_rf_sp_hdf/VDD
+connect_supply_net VDD -ports u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/u_rf_sp_hdf/VDD
+connect_supply_net VDD -ports u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom/VDDE
+
+connect_supply_net VSS -ports u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/u_rf_sp_hdf/VSS
+connect_supply_net VSS -ports u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/u_rf_sp_hdf/VSS
+connect_supply_net VSS -ports u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/u_rf_sp_hdf/VSS
+connect_supply_net VSS -ports u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/u_rf_sp_hdf/VSS
+connect_supply_net VSS -ports u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom/VSSE
+
+add_port_state VSS -state {state1 0.00}
+add_port_state VDD -state {state1 1.08}
+add_port_state VDDACC -state {state1 1.08}
+
+create_pst all_pst -supplies { \
+ VDDACC \
+ VDD \
+ VSS}
+add_pst_state aon -pst all_pst -state {state1}
+
+
+
+
+
+
diff --git a/ASIC/60pin/Cadence/cpf/nanosoc.cpf b/ASIC/60pin/Cadence/cpf/nanosoc.cpf
new file mode 100644
index 0000000000000000000000000000000000000000..f57a1ace58fd7473ee19d4cfe46bf7c5f776edf8
--- /dev/null
+++ b/ASIC/60pin/Cadence/cpf/nanosoc.cpf
@@ -0,0 +1,23 @@
+set_cpf_version 1.1
+
+set_design nanosoc_chip_pads
+create_power_domain -name TOP -default
+create_power_domain -name ACCEL -instances u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator
+
+create_nominal_condition -name nom -voltage 1.08
+
+create_power_mode -name PM -domain_conditions {TOP@nom ACCEL@nom} -default
+
+create_ground_nets -nets VSS
+create_power_nets -nets VDD
+create_power_nets -nets VDDACC
+
+create_global_connection -net VSS -pins VSS
+create_global_connection -net VDD -pins VDD
+create_global_connection -net VDDACC -pins VDDACC
+
+update_power_domain -name TOP -primary_power_net VDD -primary_ground_net VSS
+update_power_domain -name ACCEL -primary_power_net VDDACC -primary_ground_net VSS
+
+
+end_design
\ No newline at end of file
diff --git a/ASIC/60pin/Cadence/cpf/nanosoc_imp.cpf b/ASIC/60pin/Cadence/cpf/nanosoc_imp.cpf
new file mode 100644
index 0000000000000000000000000000000000000000..e0869e5a6bcf67fcaf3452a006aac49192bfcc45
--- /dev/null
+++ b/ASIC/60pin/Cadence/cpf/nanosoc_imp.cpf
@@ -0,0 +1,19 @@
+set_cpf_version 1.1
+
+set_design nanosoc_chip_pads
+create_power_domain -name TOP -default
+create_power_domain -name ACCEL -instances u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator
+
+create_nominal_condition -name nom -voltage 1.08
+
+create_power_mode -name PM -domain_conditions {TOP@nom ACCEL@nom} -default
+
+create_ground_nets -nets VSS
+create_power_nets -nets VDD
+create_power_nets -nets VDDACC
+
+update_power_domain -name TOP -primary_power_net VDD -primary_ground_net VSS
+update_power_domain -name ACCEL -primary_power_net VDDACC -primary_ground_net VSS
+
+
+end_design
\ No newline at end of file
diff --git a/ASIC/60pin/Cadence/scripts/clock_tree_synthesis.tcl b/ASIC/60pin/Cadence/scripts/clock_tree_synthesis.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..5e8a3ed93fd8086727b0177c8e084b12b46066a8
--- /dev/null
+++ b/ASIC/60pin/Cadence/scripts/clock_tree_synthesis.tcl
@@ -0,0 +1,23 @@
+############################################
+# Script : Clock Tree Implementation
+# Date : 24th May 2023
+# Author : Srimanth Tenneti
+# Description : Implements the Clock Tree
+############################################
+
+### Buffer Cells
+set_db cts_buffer_cells {*BUFH*}
+### Inverter Cells
+set_db cts_inverter_cells {*INV*}
+
+### Clock Tree Sepc
+create_clock_tree_spec -out_file design_clk.spec
+
+### Creating a Clock Tree
+ccopt_design
+
+### Optimizing the design
+opt_design -post_cts
+opt_design -post_cts -hold
+
+
diff --git a/ASIC/Cadence/Innovus/design_import.tcl b/ASIC/60pin/Cadence/scripts/design_import.tcl
similarity index 59%
rename from ASIC/Cadence/Innovus/design_import.tcl
rename to ASIC/60pin/Cadence/scripts/design_import.tcl
index 94d98bbc5cf5411cd18971c289c82804a9973f74..b8caba41590c3700779e362dfc6eefe40f6aed7d 100644
--- a/ASIC/Cadence/Innovus/design_import.tcl
+++ b/ASIC/60pin/Cadence/scripts/design_import.tcl
@@ -16,16 +16,22 @@ read_mmmc nanosoc.mmmc
# !! EDIT THIS TO YOUR PATHS IN YOUR ENVIRONMENT
set TECH_LEF $::env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/lef/1p9m_6x2z/sc12_tech.lef
set BASE_LEF $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lef/sc12_cln65lp_base_rvt.lef
+set IO_PAD_LEF /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Backend/lef/tpbn65v_9lm.lef
+set IO_PAD_DRIVER_LEF /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Backend/lef/tpdn65lpnv2od3_9lm.lef
+
# !! THESE SHOULD BE CORRECT FOR ANY ENVIRONMENT AS THEY ARE GENERATED BY MAKEFILE
-set RF_LEF $::env(SOCLABS_PROJECT_DIR)/memories/rf/rf_sp_hdf.lef
+set RF_LEF $::env(SOCLABS_PROJECT_DIR)/memories/rf_16k/rf_16k.lef
set ROM_LEF $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via.lef
### Reading LEFs
-read_physical -lef [list ${TECH_LEF} ${BASE_LEF} ${RF_LEF} ${ROM_LEF}]
+read_physical -lef [list ${TECH_LEF} ${BASE_LEF} ${IO_PAD_LEF} ${IO_PAD_DRIVER_LEF} ${RF_LEF} ${ROM_LEF}]
### Reading Netlist
-read_netlist $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads.vm
+read_netlist $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_60pin.v
+
+### Read DEF scan chain
+read_def $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_60pin.def
### Initializing the Design
init_design
@@ -35,8 +41,8 @@ gui_fit
ungroup u_nanosoc_chip_u_system
-create_floorplan -site sc12_cln65lp -core_size 1500 1500 50 50 50 50
+create_floorplan -core_margins_by die -flip s -site sc12_cln65lp -die_size 1500.0 1500.0 150.0 150.0 150.0 150.0
-read_power_intent -cpf nanosoc.cpf
+read_power_intent -cpf ../cpf/nanosoc_imp.cpf
diff --git a/ASIC/60pin/Cadence/scripts/genus.tcl b/ASIC/60pin/Cadence/scripts/genus.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..9ba96a253844cbe23bee36d765efc8cbddf483c4
--- /dev/null
+++ b/ASIC/60pin/Cadence/scripts/genus.tcl
@@ -0,0 +1,71 @@
+set_db init_lib_search_path "/home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a/ $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lib/ $::env(SOCLABS_PROJECT_DIR)/memories/rf/ $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/"
+set BASE_LIB sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.lib
+set RF_LIB rf_sp_hdf_ss_1p08v_1p08v_125c.lib
+set ROM_LIB rom_via_ss_1p08v_1p08v_125c.lib
+set IO_PAD_DRIVER tpdn65lpnv2od3bc.lib
+create_library_domain domain1
+set_db [get_db library_domains domain1] .library "$BASE_LIB $RF_LIB $ROM_LIB $IO_PAD_DRIVER"
+
+read_power_intent -cpf -module nanosoc_chip_pads nanosoc.cpf
+
+source $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/genus_flist.tcl
+elaborate nanosoc_chip_pads
+
+apply_power_intent
+check_library > lib_check.log
+
+check_cpf
+
+commit_power_intent
+check_power_structure -license lpgxl
+
+read_sdc $::env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/constraints.sdc
+
+set_db dft_scan_style muxed_scan
+set_db design:nanosoc_chip_pads .dft_min_number_of_scan_chains 1
+
+#read_dft_abstract_model nanosoc_dft_abstract_model
+define_test_signal -name TEST -active high -function test_mode -index 0 TEST
+define_test_signal -name SWDCK -active high -function scan_clock -index 0 SWDCK
+define_test_signal -name NRST -active low -function async_set_reset -index 0 NRST
+define_test_signal -name SWDIO -active high -function shift_enable -default -index 0 SWDIO
+define_test_signal -name CLK -active high -function test_clock -index 0 CLK
+
+define_scan_chain -name chain_ACCEL -sdi DFT_SDI_1 -sdo DFT_SDO_1 -shared_output
+define_scan_chain -name chain_TOP -sdi DFT_SDI_2 -sdo DFT_SDO_2 -shared_output
+
+
+check_dft_rules
+fix_dft_violations -test_control TEST -async_reset -add_observe_scan -scan_clock_pin SWDCK
+
+
+set_db syn_generic_effort high
+set_db syn_map_effort high
+
+syn_generic
+syn_map
+
+convert_to_scan
+
+connect_scan_chains -chains chain_ACCEL -power_domain ACCEL -incremental
+connect_scan_chains -chains chain_TOP -power_domain TOP -incremental
+
+syn_opt
+
+report_area > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_area_60pin.rep
+report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_timing_60pin.rep
+report_gates > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_gates_60pin.rep
+report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_power_60pin.rep
+
+write_hdl > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_60pin.vm
+write_hdl -pg > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_60pin.vp
+
+report_scan_chains > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_chains_60pin.rep
+report_scan_setup > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_setup_60pin.rep
+report_scan_registers > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_scan_registers_60pin.rep
+write_dft_abstract_model > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_dft_abstract_model_60pin
+
+write_dft_atpg_other_vendor -mentor > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/dft/nanosoc_atpg_60pin
+
+write_scandef > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_60pin.def
+
diff --git a/ASIC/60pin/Cadence/scripts/io_plan.tcl b/ASIC/60pin/Cadence/scripts/io_plan.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..6a13dc401e144f6c3818bd54d34777aae091957d
--- /dev/null
+++ b/ASIC/60pin/Cadence/scripts/io_plan.tcl
@@ -0,0 +1,57 @@
+#-----------------------------------------------------------------------------
+# NanoSoC IO plan for PnR in cadence Innovus
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# Daniel Newbrook (d.newbrook@soton.ac.uk)
+#
+# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+
+delete_io_fillers -cell PCORNER
+delete_io_fillers -cell PFILLER20
+delete_io_fillers -cell PFILLER10
+delete_io_fillers -cell PFILLER5
+delete_io_fillers -cell PFILLER1
+delete_io_fillers -cell PFILLER05
+delete_io_fillers -cell PFILLER0005
+
+
+read_io_file nanosoc_io_plan.io
+
+add_io_fillers -cells PCORNER -prefix CORNER -side n -from -300 -to 300
+add_io_fillers -cells PCORNER -prefix CORNER -side e -from 1800 -to 3000
+add_io_fillers -cells PCORNER -prefix CORNER -side s -from 1800 -to 3000
+add_io_fillers -cells PCORNER -prefix CORNER -side w -from -300 -to 300
+
+add_io_fillers -cells PFILLER20 -prefix FILLER -side n
+add_io_fillers -cells PFILLER20 -prefix FILLER -side e
+add_io_fillers -cells PFILLER20 -prefix FILLER -side s
+add_io_fillers -cells PFILLER20 -prefix FILLER -side w
+
+add_io_fillers -cells PFILLER10 -prefix FILLER -side n
+add_io_fillers -cells PFILLER10 -prefix FILLER -side e
+add_io_fillers -cells PFILLER10 -prefix FILLER -side s
+add_io_fillers -cells PFILLER10 -prefix FILLER -side w
+
+add_io_fillers -cells PFILLER5 -prefix FILLER -side n
+add_io_fillers -cells PFILLER5 -prefix FILLER -side e
+add_io_fillers -cells PFILLER5 -prefix FILLER -side s
+add_io_fillers -cells PFILLER5 -prefix FILLER -side w
+
+add_io_fillers -cells PFILLER1 -prefix FILLER -side n
+add_io_fillers -cells PFILLER1 -prefix FILLER -side e
+add_io_fillers -cells PFILLER1 -prefix FILLER -side s
+add_io_fillers -cells PFILLER1 -prefix FILLER -side w
+
+add_io_fillers -cells PFILLER05 -prefix FILLER -side n
+add_io_fillers -cells PFILLER05 -prefix FILLER -side e
+add_io_fillers -cells PFILLER05 -prefix FILLER -side s
+add_io_fillers -cells PFILLER05 -prefix FILLER -side w
+
+add_io_fillers -cells PFILLER0005 -prefix FILLER -side n
+add_io_fillers -cells PFILLER0005 -prefix FILLER -side e
+add_io_fillers -cells PFILLER0005 -prefix FILLER -side s
+add_io_fillers -cells PFILLER0005 -prefix FILLER -side w
\ No newline at end of file
diff --git a/ASIC/60pin/Cadence/scripts/nanosoc.mmmc b/ASIC/60pin/Cadence/scripts/nanosoc.mmmc
new file mode 100644
index 0000000000000000000000000000000000000000..b8c9c0d00a814a59bdc8cd00c94513228643aa60
--- /dev/null
+++ b/ASIC/60pin/Cadence/scripts/nanosoc.mmmc
@@ -0,0 +1,84 @@
+set phys_lib /research/AAA/phys_ip_library
+
+set base_path ${phys_lib}/arm/tsmc/cln65lp/sc12_base_rvt/r0p0
+set tech_path ${phys_lib}/arm/tsmc/cln65lp/arm_tech/r2p0
+set ram_path /home/dwn1c21/SoC-Labs/accelerator-project/memories/rf_16k/
+set rom_path /home/dwn1c21/SoC-Labs/accelerator-project/memories/bootrom/
+set IO_driver_path /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a/
+
+create_library_set -name default_libset_max\
+ -timing\
+ [list ${base_path}/lib/sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.lib ${ram_path}/rf_16k_ss_1p08v_1p08v_125c.lib ${rom_path}/rom_via_ss_1p08v_1p08v_125c.lib ${IO_driver_path}/tpdn65lpnv2od3wc.lib] \
+ -si\
+ [list ${base_path}/celtic/sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.cdB]
+
+create_library_set -name default_libset_min\
+ -timing\
+ [list ${base_path}/lib/sc12_cln65lp_base_rvt_ff_typical_min_1p32v_m40c.lib ${ram_path}/rf_16k_ff_1p32v_1p32v_m40c.lib ${rom_path}/rom_via_ff_1p32v_1p32v_m40c.lib ${IO_driver_path}/tpdn65lpnv2od3bc.lib] \
+ -si\
+ [list ${base_path}/celtic/sc12_cln65lp_base_rvt_ff_typical_min_1p32v_m40c.cdB]
+
+create_timing_condition -name default_mapping_tc_2\
+ -library_sets [list default_libset_min]
+create_timing_condition -name default_mapping_tc_1\
+ -library_sets [list default_libset_max]
+
+create_rc_corner -name default_rc_corner_worst\
+ -pre_route_res 1\
+ -post_route_res 1\
+ -pre_route_cap 1\
+ -post_route_cap 1\
+ -post_route_cross_cap 1\
+ -pre_route_clock_res 0\
+ -pre_route_clock_cap 0\
+ -cap_table ${tech_path}/cadence_captable/1p9m_6x2z/rcworst.captbl
+
+create_rc_corner -name default_rc_corner_best\
+ -pre_route_res 1\
+ -post_route_res 1\
+ -pre_route_cap 1\
+ -post_route_cap 1\
+ -post_route_cross_cap 1\
+ -pre_route_clock_res 0\
+ -pre_route_clock_cap 0\
+ -cap_table ${tech_path}/cadence_captable/1p9m_6x2z/rcbest.captbl
+
+create_rc_corner -name default_rc_corner_typical\
+ -pre_route_res 1\
+ -post_route_res 1\
+ -pre_route_cap 1\
+ -post_route_cap 1\
+ -post_route_cross_cap 1\
+ -pre_route_clock_res 0\
+ -pre_route_clock_cap 0\
+ -cap_table ${tech_path}/cadence_captable/1p9m_6x2z/typical.captbl
+
+
+
+create_delay_corner -name default_delay_corner_max\
+ -timing_condition {default_mapping_tc_1}\
+ -rc_corner default_rc_corner_worst
+
+create_delay_corner -name default_delay_corner_ocv\
+ -early_timing_condition {default_mapping_tc_2}\
+ -late_timing_condition {default_mapping_tc_1}\
+ -rc_corner default_rc_corner_typical
+
+create_delay_corner -name default_delay_corner_min\
+ -timing_condition default_mapping_tc_2\
+ -rc_corner default_rc_corner_best
+
+create_constraint_mode -name default_constraint_mode\
+ -sdc_files\
+ [list ../../../constraints.sdc]
+
+create_analysis_view -name default_analysis_view_setup -constraint_mode default_constraint_mode -delay_corner default_delay_corner_max
+
+create_analysis_view -name default_analysis_view_hold -constraint_mode default_constraint_mode -delay_corner default_delay_corner_min
+
+
+create_analysis_view -name typical_analysis_view_setup -constraint_mode default_constraint_mode -delay_corner default_delay_corner_ocv
+create_analysis_view -name typical_analysis_view_hold -constraint_mode default_constraint_mode -delay_corner default_delay_corner_ocv
+
+
+set_analysis_view -setup [list default_analysis_view_setup] -hold [list default_analysis_view_hold]
diff --git a/ASIC/60pin/Cadence/scripts/nanosoc_io_plan.io b/ASIC/60pin/Cadence/scripts/nanosoc_io_plan.io
new file mode 100644
index 0000000000000000000000000000000000000000..e557d0b977d684a90c8787c179eb02906a14438b
--- /dev/null
+++ b/ASIC/60pin/Cadence/scripts/nanosoc_io_plan.io
@@ -0,0 +1,82 @@
+###############################################################
+# Generated by: Cadence Innovus 21.11-s130_1
+# OS: Linux x86_64(Host ID srv03335)
+# Generated on: Thu Nov 16 16:18:31 2023
+# Design: nanosoc_chip_pads
+# Command: write_io_file -locations -template nanosoc_chip_pads.save.io
+###############################################################
+
+(globals
+ version = 3
+ io_order = default
+)
+(iopad
+ (top
+ (inst name="uPAD_P1_08" offset=153.67 )
+ (inst name="uPAD_P1_09" offset=271.00 place_status=placed )
+ (inst name="uPAD_P1_10" offset=388.33 place_status=placed )
+ (inst name="uPAD_P1_11" offset=505.67 place_status=placed )
+ (inst name="uPAD_TEST_I" offset=149.29)
+ (inst name="uPAD_SWDCK_I" offset=257.86 place_status=placed )
+ (inst name="uPAD_VDD_3" offset=366.43 place_status=placed )
+ (inst name="uPAD_VSS_3" offset=475.00 place_status=placed )
+ (inst name="uPAD_VDDIO_3" offset=583.57 place_status=placed )
+ (inst name="uPAD_P1_00" offset=692.14 place_status=placed )
+ (inst name="uPAD_P1_01" offset=800.71 place_status=placed )
+ (inst name="uPAD_P1_12" offset=1444.33 place_status=placed )
+ (inst name="uPAD_P1_13" offset=1561.67 place_status=placed )
+ (inst name="uPAD_P1_14" offset=1679.00 place_status=placed )
+ (inst name="uPAD_P1_15" offset=1796.33 place_status=placed )
+ )
+ (left
+ (inst name="uPAD_P0_04" offset=153.67 place_status=placed )
+ (inst name="uPAD_P0_05" offset=271.00 place_status=placed )
+ (inst name="RESERVED " offset=388.33 place_status=placed )
+ (inst name="RESERVED " offset=505.67 place_status=placed )
+ (inst name="uPAD_P0_03" offset=149.29 place_status=placed )
+ (inst name="uPAD_VDDACC_0" offset=257.86 place_status=placed )
+ (inst name="uPAD_VSS_0" offset=366.43 place_status=placed )
+ (inst name="uPAD_CLK_I" offset=475.00 place_status=placed )
+ (inst name="uPAD_VDD_0" offset=583.57 place_status=placed )
+ (inst name="uPAD_VDDIO_0" offset=692.14 place_status=placed )
+ (inst name="uPAD_SWDIO_IO" offset=800.71 place_status=placed )
+ (inst name="uPAD_VSSIO_0" offset=1444.33 place_status=placed )
+ (inst name="RESERVED " offset=1561.67 place_status=placed )
+ (inst name="uPAD_P0_06" offset=1679.00 place_status=placed )
+ (inst name="uPAD_P0_07" offset=1796.33 place_status=placed )
+ )
+ (bottom
+ (inst name="uPAD_P0_15" offset=153.67 lace_status=placed )
+ (inst name="uPAD_P0_14" offset=271.00 lace_status=placed )
+ (inst name="uPAD_P0_13" offset=388.33 lace_status=placed )
+ (inst name="uPAD_P0_12" offset=505.67 lace_status=placed )
+ (inst name="uPAD_P0_02" offset=149.29 place_status=placed )
+ (inst name="uPAD_VDDACC_1" offset=257.86 place_status=placed )
+ (inst name="uPAD_VDDIO_1" offset=366.43 place_status=placed )
+ (inst name="uPAD_VDD_1" offset=475.00 place_status=placed )
+ (inst name="uPAD_VSS_1" offset=583.57 place_status=placed )
+ (inst name="uPAD_P0_01" offset=692.14 place_status=placed )
+ (inst name="uPAD_P0_00" offset=800.71 )
+ (inst name="uPAD_P0_11" offset=1444.33 place_status=placed )
+ (inst name="uPAD_P0_10" offset=1561.67 place_status=placed )
+ (inst name="uPAD_P0_09" offset=1679.00 place_status=placed )
+ (inst name="uPAD_P0_08" offset=1796.33 place_status=placed )
+ )
+ (right
+ (inst name="uPAD_P1_07" offset=153.67 place_status=placed )
+ (inst name="uPAD_P1_06" offset=271.00 place_status=placed )
+ (inst name="RESERVED " offset=388.33 place_status=placed )
+ (inst name="uPAD_VSSIO_1" offset=505.67 place_status=placed )
+ (inst name="uPAD_P1_03" offset=149.29 place_status=placed )
+ (inst name="uPAD_P1_02" offset=257.86 place_status=placed )
+ (inst name="uPAD_VDDACC_2" offset=366.43 place_status=placed )
+ (inst name="uPAD_VDD_2" offset=475.00 place_status=placed )
+ (inst name="uPAD_VSS_2" offset=583.57 place_status=placed )
+ (inst name="uPAD_VDDIO_2" offset=692.14 place_status=placed )
+ (inst name="uPAD_NRST_I" offset=800.71 place_status=placed )
+ (inst name="RESERVED " offset=1444.33 place_status=placed )
+ (inst name="RESERVED " offset=1561.67 place_status=placed )
+ (inst name="uPAD_P1_04" offset=1679.00 place_status=placed )
+ (inst name="uPAD_P1_05" offset=1796.33 place_status=placed )
+ )
+)
diff --git a/ASIC/60pin/Cadence/scripts/place.tcl b/ASIC/60pin/Cadence/scripts/place.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..9f25bb8c140db90cffb66fa2308fecdb43ff2be2
--- /dev/null
+++ b/ASIC/60pin/Cadence/scripts/place.tcl
@@ -0,0 +1,21 @@
+############################################
+# Script : Placement
+# Date : May 24 2024
+# Author : Srimanth Tenneti
+############################################
+
+### Congestion and Timing Setting
+set_db design_process_node 65
+set_db place_global_cong_effort auto
+set_db place_global_timing_effort high
+
+### Uniform Cell Distribution
+
+set_db place_global_uniform_density true
+
+### Placement Mode Config
+set_db place_design_floorplan_mode false
+place_opt_design
+
+### Delay Calculation
+write_sdf design.sdf -ideal_clock_network
diff --git a/ASIC/Cadence/Innovus/place_macros.tcl b/ASIC/60pin/Cadence/scripts/place_macros.tcl
similarity index 83%
rename from ASIC/Cadence/Innovus/place_macros.tcl
rename to ASIC/60pin/Cadence/scripts/place_macros.tcl
index ee92e421ba9b9c6607f8b59322e71bf453998229..6b1958d3ac8edebab4ea0ebcbb044b58d5abfd18 100644
--- a/ASIC/Cadence/Innovus/place_macros.tcl
+++ b/ASIC/60pin/Cadence/scripts/place_macros.tcl
@@ -15,11 +15,14 @@ create_relative_floorplan -ref_type object -horizontal_edge_separate {3 -30 1}
create_relative_floorplan -ref_type object -horizontal_edge_separate {3 -30 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system_u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_u_rf_sp_hdf -ref u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_u_rf_sp_hdf
create_relative_floorplan -ref_type object -orient R0 -horizontal_edge_separate {3 -30 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system_u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_u_rf_sp_hdf -ref u_nanosoc_chip_u_system_u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_u_rf_sp_hdf
create_relative_floorplan -ref_type core_boundary -orient R180 -horizontal_edge_separate {3 20 3} -vertical_edge_separate {2 -40 2} -place u_nanosoc_chip_u_system_u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom
-create_relative_floorplan -ref_type core_boundary -horizontal_edge_separate {1 -500 1} -vertical_edge_separate {0 50 0} -place u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator
-create_partition -hinst u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -core_spacing 0.0 0.0 0.0 0.0 -rail_width 0.0 -min_pitch_left 2 -min_pitch_right 2 -min_pitch_top 2 -min_pitch_bottom 2 -reserved_layer { 1 2 3 4 5 6 7 8 9 10} -pin_layer_top { 2 4 6 8 10} -pin_layer_left { 3 5 7 9} -pin_layer_bottom { 2 4 6 8 10} -pin_layer_right { 3 5 7 9} -place_halo 0.1 0.1 0.1 0.1 -route_halo 0.0 -route_halo_top_layer 10 -route_halo_bottom_layer 1
+
+move_obj u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -point {500 500}
+add_fences -hinst u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -min_gap 5
+create_relative_floorplan -ref_type core_boundary -horizontal_edge_separate {1 -100 1} -vertical_edge_separate {0 250 0} -place u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator
+create_partition -hinst u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -core_spacing 2.0 2.0 2.0 2.0 -rail_width 0.0 -min_pitch_left 2 -min_pitch_right 2 -min_pitch_top 2 -min_pitch_bottom 2 -reserved_layer { 1 2 3 4 5 6 7 8 9 10} -pin_layer_top { 2 4 6 8 10} -pin_layer_left { 3 5 7 9} -pin_layer_bottom { 2 4 6 8 10} -pin_layer_right { 3 5 7 9} -place_halo 2 2 2 2 -route_halo 2.0 -route_halo_top_layer 5 -route_halo_bottom_layer 1
create_place_halo -halo_deltas {5 5 5 5} -insts u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_u_rf_sp_hdf
create_place_halo -halo_deltas {5 5 5 5} -insts u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_u_rf_sp_hdf
create_place_halo -halo_deltas {5 5 5 5} -insts u_nanosoc_chip_u_system_u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_u_rf_sp_hdf
create_place_halo -halo_deltas {5 5 5 5} -insts u_nanosoc_chip_u_system_u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_u_rf_sp_hdf
-create_place_halo -halo_deltas {5 5 5 5} -insts u_nanosoc_chip_u_system_u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom
\ No newline at end of file
+create_place_halo -halo_deltas {5 5 5 5} -insts u_nanosoc_chip_u_system_u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom
diff --git a/ASIC/60pin/Cadence/scripts/pnr_flow.tcl b/ASIC/60pin/Cadence/scripts/pnr_flow.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..ae76199c635dfb953b5e88a0ef6d9eb86e60f58e
--- /dev/null
+++ b/ASIC/60pin/Cadence/scripts/pnr_flow.tcl
@@ -0,0 +1,76 @@
+######################################
+# Script : Place and Route Flow
+# Date : 25th May 2023
+# Author : Srimanth Tenneti
+# Description : Innovus PnR Flow
+######################################
+
+puts "Starting PnR Flow ..."
+
+
+### Design Import
+source design_import.tcl
+
+### IO Planning
+source io_plan.tcl
+
+### Memory and accelerator placement
+source place_macros.tcl
+commit_power_intent
+check_power_domains
+
+### Power Plan
+source power_plan.tcl
+
+### Power Route
+source power_route.tcl
+
+report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/1pre_place_nanosoc_imp_timing.rep
+
+### Placement
+source place.tcl
+
+report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/2post_place_nanosoc_imp_timing.rep
+
+
+uniquify nanosoc_chip_pads -verbose
+### CTS
+source clock_tree_synthesis.tcl
+
+report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/3post_clock_nanosoc_imp_timing.rep
+
+### Add filler cells
+eval_legacy { addFiller -cell FILL128_A12TR WELLANTENNATIEPW2_A12TR FILLTIE8_A12TR FILLTIE64_A12TR FILLTIE4_A12TR FILLTIE32_A12TR FILLTIE2_A12TR FILLTIE16_A12TR FILLTIE128_A12TR FILLCAPTIE8_A12TR -prefix FILLER -powerDomain ACCEL -doDRC }
+eval_legacy { addFiller -cell WELLANTENNATIEPW2_A12TR FILLTIE8_A12TR FILLTIE64_A12TR FILLTIE4_A12TR FILLTIE32_A12TR FILLTIE2_A12TR FILLTIE16_A12TR FILLTIE128_A12TR FILLCAPTIE8_A12TR -prefix FILLER -powerDomain TOP -doDRC }
+
+
+### Routing
+source route.tcl
+
+report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/4post_route_nanosoc_imp_timing.rep
+
+check_antenna
+
+### Fill metal
+set_metal_fill -layer M1 -opc_active_spacing 0.090 -border_spacing -0.001
+set_metal_fill -layer M2 -opc_active_spacing 0.100 -border_spacing -0.001
+set_metal_fill -layer M3 -opc_active_spacing 0.100 -border_spacing -0.001
+set_metal_fill -layer M4 -opc_active_spacing 0.100 -border_spacing -0.001
+set_metal_fill -layer M5 -opc_active_spacing 0.100 -border_spacing -0.001
+set_metal_fill -layer M6 -opc_active_spacing 0.100 -border_spacing -0.001
+set_metal_fill -layer M7 -opc_active_spacing 0.100 -border_spacing -0.001
+set_metal_fill -layer M8 -opc_active_spacing 0.400 -border_spacing -0.001
+set_metal_fill -layer M9 -opc_active_spacing 0.400 -border_spacing -0.001
+set_metal_fill -layer AP -opc_active_spacing 2.000 -border_spacing -0.001
+add_metal_fill -layers { M1 M2 M3 M4 M5 M6 M7 M8 M9 AP } -nets { VSSIO VSS VDDACC VDDIO VDD }
+
+
+report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_timing.rep
+report_area > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_area.rep
+report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_power.rep
+
+gui_show
+
+
+
+
diff --git a/ASIC/60pin/Cadence/scripts/power_plan.tcl b/ASIC/60pin/Cadence/scripts/power_plan.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..5895c391175d676798896d0d738044b37a2073e0
--- /dev/null
+++ b/ASIC/60pin/Cadence/scripts/power_plan.tcl
@@ -0,0 +1,86 @@
+#########################################
+# Script : Power Planning
+# Tool : Cadence Innovus
+# Date : May 22, 2023
+# Author : Srimanth Tenneti
+#########################################
+
+### Connecting Global Nets
+connect_global_net VDD -type pg_pin -pin_base_name VDD -inst_base_name *
+connect_global_net VDDIO -type pg_pin -pin_base_name VDDIO -inst_base_name *
+connect_global_net VSS -type pg_pin -pin_base_name VSS -inst_base_name *
+connect_global_net VSSIO -type pg_pin -pin_base_name VSSIO -inst_base_name *
+connect_global_net VDDACC -type pg_pin -pin_base_name VDD -inst_base_name {} -hinst u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -override
+### Top and Bottom Metal Declartions
+set_db add_rings_stacked_via_top_layer M8
+set_db add_rings_stacked_via_bottom_layer M1
+
+### Adding Rings
+add_rings -nets {VDD VDDACC VSS} -type core_rings -follow core -layer {top M9 bottom M9 left M8 right M8} -width {top 8 bottom 8 left 8 right 8} -spacing {top 2 bottom 2 left 2 right 2} -offset {top 3 bottom 3 left 3 right 3} -center 0 -threshold 0 -jog_distance 0 -snap_wire_center_to_grid none
+
+### Adding Stripes
+set_db add_stripes_ignore_block_check true
+set_db add_stripes_break_at none
+set_db add_stripes_route_over_rows_only false
+set_db add_stripes_rows_without_stripes_only false
+set_db add_stripes_extend_to_closest_target none
+set_db add_stripes_stop_at_last_wire_for_area false
+set_db add_stripes_partial_set_through_domain true
+set_db add_stripes_ignore_non_default_domains false
+set_db add_stripes_trim_antenna_back_to_shape none
+set_db add_stripes_spacing_type edge_to_edge
+set_db add_stripes_spacing_from_block 0
+set_db add_stripes_stripe_min_length stripe_width
+set_db add_stripes_stacked_via_top_layer AP
+set_db add_stripes_stacked_via_bottom_layer M1
+set_db add_stripes_via_using_exact_crossover_size false
+set_db add_stripes_split_vias false
+set_db add_stripes_orthogonal_only true
+set_db add_stripes_allow_jog { padcore_ring block_ring }
+set_db add_stripes_skip_via_on_pin { standardcell }
+set_db add_stripes_skip_via_on_wire_shape { noshape }
+add_stripes -nets {VDD VDDACC VSS} -layer M6 -direction vertical -width 1.8 -spacing 0.8 -set_to_set_distance 60 -extend_to all_domains -start_from left -start_offset 50 -stop_offset 0 -switch_layer_over_obs false -max_same_layer_jog_length 2 -pad_core_ring_top_layer_limit AP -pad_core_ring_bottom_layer_limit M1 -block_ring_top_layer_limit AP -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none
+
+deselect_obj -all
+
+# Connect Accelerator region
+select_obj u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator
+set_db add_stripes_ignore_block_check true
+set_db add_stripes_break_at none
+set_db add_stripes_route_over_rows_only false
+set_db add_stripes_rows_without_stripes_only false
+set_db add_stripes_extend_to_closest_target stripe
+set_db add_stripes_stop_at_last_wire_for_area false
+set_db add_stripes_partial_set_through_domain true
+set_db add_stripes_ignore_non_default_domains false
+set_db add_stripes_trim_antenna_back_to_shape none
+set_db add_stripes_spacing_type edge_to_edge
+set_db add_stripes_spacing_from_block 0
+set_db add_stripes_stripe_min_length stripe_width
+set_db add_stripes_stacked_via_top_layer AP
+set_db add_stripes_stacked_via_bottom_layer M4
+set_db add_stripes_via_using_exact_crossover_size false
+set_db add_stripes_split_vias false
+set_db add_stripes_orthogonal_only true
+set_db add_stripes_allow_jog { padcore_ring block_ring }
+set_db add_stripes_skip_via_on_pin { standardcell }
+set_db add_stripes_skip_via_on_wire_shape { noshape }
+add_stripes -nets {VDDACC VSS} -layer M9 -direction horizontal -width 1 -spacing 0.5 -set_to_set_distance 50 -over_power_domain 1 -start_from bottom -start_offset 15 -stop_offset 0 -switch_layer_over_obs false -max_same_layer_jog_length 2 -pad_core_ring_top_layer_limit AP -pad_core_ring_bottom_layer_limit M1 -block_ring_top_layer_limit AP -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none
+
+deselect_obj -all
+
+# connect Macros
+select_obj [ list u_nanosoc_chip_u_system_u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_u_rf_sp_hdf u_nanosoc_chip_u_system_u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_u_rf_sp_hdf u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_u_rf_sp_hdf u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_u_rf_sp_hdf u_nanosoc_chip_u_system_u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom]
+set_db add_stripes_ignore_block_check false
+set_db add_stripes_break_at none
+set_db add_stripes_route_over_rows_only false
+set_db add_stripes_rows_without_stripes_only false
+set_db add_stripes_extend_to_closest_target stripe
+add_stripes -nets {VDD VSS} -layer M5 -direction horizontal -width 1 -spacing 0.5 -set_to_set_distance 15 -over_power_domain 1 -start_from bottom -start_offset 8 -stop_offset 0 -switch_layer_over_obs false -merge_stripes_value 500 -max_same_layer_jog_length 2 -pad_core_ring_top_layer_limit AP -pad_core_ring_bottom_layer_limit M1 -block_ring_top_layer_limit AP -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none
+
+deselect_obj -all
+
+# Add END CAPS
+add_endcaps -start_row_cap ENDCAPTIE2_A12TR -end_row_cap ENDCAPTIE2_A12TR -prefix ENDCAP
+add_endcaps -power_domain ACCEL -start_row_cap ENDCAPTIE2_A12TR -end_row_cap ENDCAPTIE2_A12TR -prefix ENDCAP
+
diff --git a/ASIC/60pin/Cadence/scripts/power_route.tcl b/ASIC/60pin/Cadence/scripts/power_route.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..bf05e721f3b978bfc85e3b7aa790c38c7ccce5a8
--- /dev/null
+++ b/ASIC/60pin/Cadence/scripts/power_route.tcl
@@ -0,0 +1,12 @@
+##################################
+# Script : Special Route Script
+# Date : May 24, 2023
+# Description : Power Routing
+# Author : Srimanth Tenneti
+##################################
+route_special -connect {pad_pin pad_ring} -layer_change_range { M1(1) AP(10) } -block_pin_target nearest_target -pad_pin_port_connect {all_port all_geom} -pad_pin_target nearest_target -allow_jogging 1 -crossover_via_layer_range { M1(1) AP(10) } -nets { VDD VSS VDDACC } -allow_layer_change 1 -pad_pin_width 6 -target_via_layer_range { M1(1) AP(10) }
+
+route_special -connect {block_pin core_pin floating_stripe} -layer_change_range { M1(1) AP(10) } -block_pin_target nearest_target -pad_pin_port_connect {all_port one_geom} -pad_pin_target nearest_target -core_pin_target first_after_row_end -floating_stripe_target {block_ring pad_ring ring stripe ring_pin block_pin followpin} -allow_jogging 1 -power_domains { ACCEL } -crossover_via_layer_range { M1(1) AP(10) } -nets { VDDACC VSS } -allow_layer_change 1 -block_pin use_lef -target_via_layer_range { M1(1) AP(10) }
+route_special -connect {block_pin core_pin floating_stripe} -layer_change_range { M1(1) AP(10) } -block_pin_target nearest_target -pad_pin_port_connect {all_port one_geom} -pad_pin_target nearest_target -core_pin_target first_after_row_end -floating_stripe_target {block_ring pad_ring ring stripe ring_pin block_pin followpin} -allow_jogging 1 -power_domains { TOP } -crossover_via_layer_range { M1(1) AP(10) } -nets { VDD VSS } -allow_layer_change 1 -block_pin use_lef -target_via_layer_range { M1(1) AP(10) }
+
+#route_special -nets {VDD VSS} -connect core_pin -block_pin_target nearest_target -core_pin_target first_after_row_end -allow_jogging 1 -allow_layer_change 1 -layer_change_range { M1(1) M8(8) } -crossover_via_layer_range { M1(1) M8(8) } -target_via_layer_range { M1(1) M8(8) }
diff --git a/ASIC/60pin/Cadence/scripts/route.tcl b/ASIC/60pin/Cadence/scripts/route.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..b12b0975739e80b149b89b66e2ddee6a57df17b5
--- /dev/null
+++ b/ASIC/60pin/Cadence/scripts/route.tcl
@@ -0,0 +1,18 @@
+
+### Clock Net Spacing
+set_route_attributes -nets clk -preferred_extra_space_tracks 2
+
+### Multi Cut Via Effort
+set_db route_design_detail_use_multi_cut_via_effort medium
+
+### Timing Driven Route
+set_db route_design_with_timing_driven 1
+
+### SI Driven Route
+set_db route_design_with_si_driven 1
+
+### Route Design
+route_design -global_detail
+
+### Timing Analysis Type
+set_db timing_analysis_type ocv
diff --git a/ASIC/60pin/Synopsys/scripts/fm_shell.tcl b/ASIC/60pin/Synopsys/scripts/fm_shell.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..87b374118661e041b6400a887e943cee8c4b3b00
--- /dev/null
+++ b/ASIC/60pin/Synopsys/scripts/fm_shell.tcl
@@ -0,0 +1,28 @@
+
+set_mismatch_message_filter -warn FMR_ELAB-147
+set_svf -append $env(SOCLABS_PROJECT_DIR)/nanosoc_tech/synthesis/default.svf
+set IO_FRONTEND_DIR /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a
+
+source $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/formality_flist.tcl
+read_db -r $env(SOCLABS_PROJECT_DIR)/memories/rf/rf_sp_hdf_ss_1p08v_1p08v_125c.db
+read_db -r $env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via_ss_1p08v_1p08v_125c.db
+read_db -r $IO_FRONTEND_DIR/tpdn65lpnv2od3wc.db
+set_top nanosoc_chip_pads
+
+# Read db files
+read_db -i $env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/db/sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.db
+read_db -i $env(SOCLABS_PROJECT_DIR)/memories/rf/rf_sp_hdf_ss_1p08v_1p08v_125c.db
+read_db -i $env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via_ss_1p08v_1p08v_125c.db
+read_db -i $IO_FRONTEND_DIR/tpdn65lpnv2od3wc.db
+# Read Gate netlist
+
+read_verilog -i $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads.vm
+
+set_top nanosoc_chip_pads
+
+match
+verify
+
+analyze_points -failing
+
+save_session nanosoc_chip_pads_formal_equivalence
\ No newline at end of file
diff --git a/ASIC/60pin/Synopsys/scripts/place_memories.tcl b/ASIC/60pin/Synopsys/scripts/place_memories.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..945dea4948d4d6a44e577323a1909c0629a8e6c6
--- /dev/null
+++ b/ASIC/60pin/Synopsys/scripts/place_memories.tcl
@@ -0,0 +1,16 @@
+set_macro_relative_location -target_object [get_cell {u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/u_rf_sp_hdf}] -target_orientation R0 -target_corner tr -anchor_corner tr -offset {-0.1 -0.47} -offset_type scalable
+set_macro_relative_location -target_object [get_cell {u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/u_rf_sp_hdf}] -target_orientation R0 -target_corner tr -anchor_corner tr -offset {-0.1 -0.67} -offset_type scalable
+set_macro_relative_location -target_object [get_cell {u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/u_rf_sp_hdf}] -target_orientation R0 -target_corner tr -anchor_corner tr -offset {-0.1 -0.05} -offset_type scalable
+set_macro_relative_location -target_object [get_cell {u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/u_rf_sp_hdf}] -target_orientation R0 -target_corner tr -anchor_corner tr -offset {-0.1 -0.27} -offset_type scalable
+set_macro_relative_location -target_object [get_cell {u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom}] -target_orientation R180 -target_corner br -anchor_corner br -offset {-0.15 0.1} -offset_type scalable
+create_macro_relative_location_placement
+
+set_attribute -objects [get_cells u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/u_rf_sp_hdf] -name physical_status -value fixed
+set_attribute -objects [get_cells u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/u_rf_sp_hdf] -name physical_status -value fixed
+set_attribute -objects [get_cells u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/u_rf_sp_hdf] -name physical_status -value fixed
+set_attribute -objects [get_cells u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/u_rf_sp_hdf] -name physical_status -value fixed
+set_attribute -objects [get_cells u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom] -name physical_status -value fixed
+
+create_keepout_margin -type hard -outer {5 5 5 5} [get_attribute [get_cells u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/u_rf_sp_hdf] ref_block];create_keepout_margin -type hard_macro -outer {5 5 5 5} [get_attribute [get_cells u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/u_rf_sp_hdf] ref_block];create_keepout_margin -type soft -outer {8 8 8 8} [get_attribute [get_cells u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/u_rf_sp_hdf] ref_block];
+create_keepout_margin -type hard -outer {5 5 5 5} [get_attribute [get_cells u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom] ref_block];create_keepout_margin -type hard_macro -outer {5 5 5 5} [get_attribute [get_cells u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom] ref_block];create_keepout_margin -type soft -outer {8 8 8 8} [get_attribute [get_cells u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom] ref_block];
+
diff --git a/ASIC/60pin/Synopsys/scripts/place_pins.tcl b/ASIC/60pin/Synopsys/scripts/place_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..c0f262384a37661c2e11fc243eb90c23f8da9e81
--- /dev/null
+++ b/ASIC/60pin/Synopsys/scripts/place_pins.tcl
@@ -0,0 +1,6 @@
+set_individual_pin_constraints -ports {P0[15] P0[14] P0[13] P0[12] P0[11] P0[10] P0[9] P0[8] P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0]} -sides 1
+set_individual_pin_constraints -ports {P1[15] P1[14] P1[13] P1[12] P1[11] P1[10] P1[9] P1[8] P1[7] P1[6] P1[5] P1[4] P1[3] P1[2] P1[1] P1[0]} -sides 3
+set_individual_pin_constraints -ports {CLK TEST VDD VDDIO VDDACC} -sides 2
+set_individual_pin_constraints -ports {NRST VSS VSSIO SWDIO SWDCK} -sides 4
+
+place_pins -self
\ No newline at end of file
diff --git a/ASIC/60pin/Synopsys/scripts/pnr.tcl b/ASIC/60pin/Synopsys/scripts/pnr.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..9fdf34e618c2ad7f4241833932ac0a105fe334da
--- /dev/null
+++ b/ASIC/60pin/Synopsys/scripts/pnr.tcl
@@ -0,0 +1,153 @@
+#//-----------------------------------------------------------------------------
+#// PnR Flow script for Synopsys ICC2
+#// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#//
+#// Contributorss
+#//
+#// Daniel Newbrook (d.newbrook@soton.ac.uk)
+#//
+#// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+#//-----------------------------------------------------------------------------
+
+
+set design_name nanosoc_chip_pads
+
+# Edit these for your environment
+set PHYS_IP_DIR /research/AAA/phys_ip_library
+set MEM_DIR /home/dwn1c21/SoC-Labs/accelerator-project/memories
+set IO_BACKEND_DIR /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Backend/lef
+set IO_FRONTEND_DIR /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a
+
+set_app_var link_library [list $PHYS_IP_DIR/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/db/sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.db $MEM_DIR/bootrom/rom_via_ss_1p08v_1p08v_125c.db $MEM_DIR/rf/rf_sp_hdf_ss_1p08v_1p08v_125c.db $IO_FRONTEND_DIR/tpdn65lpnv2od3wc.db]
+create_lib tsmc65lp -technology $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/milkyway/1p9m_6x2z/sc12_tech.tf -ref_libs [list $PHYS_IP_DIR/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lef/sc12_cln65lp_base_rvt.lef $MEM_DIR/rf/rf_sp_hdf.lef $MEM_DIR/bootrom/rom_via.lef $IO_BACKEND_DIR/tpbn65v_9lm.lef $IO_BACKEND_DIR/tpdn65lpnv2od3_9lm.lef]
+
+read_parasitic_tech -name typical -tlup $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/typical.tluplus -layermap $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/tluplus.map
+read_parasitic_tech -name rcbest -tlup $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/rcbest.tluplus -layermap $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/tluplus.map
+read_parasitic_tech -name rcworst -tlup $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/rcworst.tluplus -layermap $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/tluplus.map
+
+
+read_verilog -library tsmc65lp -design nanosoc_chip_pads -top nanosoc_chip_pads $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/Synopsys/nanosoc_chip_pads.vp
+read_def $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/Synopsys/nanosoc_chip_pads.def
+link_block
+
+create_cell {PAD_CORNER_NE PAD_CORNER_SE PAD_CORNER_SW PAD_CORNER_NW} PCORNER
+
+initialize_floorplan -side_length {1500 1500} -core_offset {150}
+create_io_ring -name main_io
+explore_logic_hierarchy -organize
+
+# Place IO pins
+source place_pins.tcl
+
+# Power domains TOP ACCEL and MEM
+create_power_domain TOP
+create_power_domain ACCEL -elements {u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator}
+#VDD
+create_supply_port VDD
+create_supply_net VDD -domain TOP
+connect_supply_net VDD -ports VDD
+
+#VSS
+create_supply_port VSS
+create_supply_net VSS -domain TOP
+create_supply_net VSS -domain ACCEL -reuse
+connect_supply_net VSS -ports VSS
+
+#VDDACC
+create_supply_port VDDACC
+create_supply_net VDDACC -domain ACCEL
+connect_supply_net VDDACC -ports VDDACC
+
+
+#IO Supplies
+create_supply_port VDDIO -domain TOP
+connect_supply_net VDDIO -ports VDDIO
+
+set_domain_supply_net TOP -primary_power_net VDD -primary_ground_net VSS
+set_domain_supply_net ACCEL -primary_power_net VDDACC -primary_ground_net VSS
+# Create voltage and power region for accelerator
+create_voltage_area -power_domains ACCEL -power VDDACC -ground VSS -nwell VDDACC -pwell VSS -region {{{150 1050} {1100 1650}}} -name VA_ACCEL -cells [get_cells -physical_context -hierarchical \
+-regexp u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator/.*]
+create_pg_region {pg_ACCEL} -voltage_area VA_ACCEL -expand {0 10}
+
+create_pg_region {pg_TOP} -voltage_area DEFAULT_VA
+
+
+set_parasitic_parameters -early_spec rcbest -early_temperature -40 -late_spec rcworst -late_temperature 125
+current_corner default
+set_operating_conditions -max_library sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c -max ss_typical_max_1p08v_125c -min_library sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c -min ss_typical_max_1p08v_125c
+current_corner default
+set_parasitic_parameters -early_spec rcbest -early_temperature -40 -late_spec rcworst -late_temperature 125
+current_corner default
+set_operating_conditions -max_library sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c -max ss_typical_max_1p08v_125c -min_library sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c -min ss_typical_max_1p08v_125c
+current_mode default
+set_voltage 1.08 -corner [current_corner] -object_list [get_supply_nets VDD]
+set_voltage 1.08 -corner [current_corner] -object_list [get_supply_nets VDDACC]
+set_voltage 3.00 -corner [current_corner] -object_list [get_supply_nets VDDIO]
+set_voltage 0.00 -corner [current_corner] -object_list [get_supply_nets VSS]
+
+add_port_state VSS -state {on 0.0}
+add_port_state VDD -state {on 1.08}
+add_port_state VDDACC -state {on 1.08}
+add_port_state VDDIO -state {on 3.0}
+create_pst ao_pst -supplies {VSS VDD VDDACC VDDIO}
+add_pst_state ao -pst ao_pst -state {on on on on}
+
+commit_upf
+
+set_app_options -list {opt.timing.effort {medium}}
+set_app_options -list {clock_opt.place.effort {high}}
+set_app_options -list {place_opt.flow.clock_aware_placement {true}}
+set_app_options -list {place_opt.final_place.effort {high}}
+
+read_sdc $env(SOCLABS_PROJECT_DIR)/nanosoc_tech/ASIC/constraints.sdc
+update_timing
+
+
+
+change_selection [explore_logic_hierarchy -create_module_boundary]
+explore_logic_hierarchy -place
+
+#Place and fix memories with boundary
+source place_memories.tcl
+
+change_selection [explore_logic_hierarchy -create_module_boundary]
+explore_logic_hierarchy -place
+
+#Create power ring and straps
+source power_plan.tcl
+
+#Start Placement
+create_placement
+legalize_placement -cells [get_cells *]
+
+save_lib -all
+
+report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/1pre_opt_placement_timing.rep
+check_mv_design > check_mv_design.log
+
+report_utilization -of_objects [get_voltage_areas {DEFAULT_VA}] > check_util_default_va.log
+report_utilization -of_objects [get_voltage_areas {VA_ACCEL}] > check_util_va_accel.log
+
+
+place_opt
+save_lib -all
+
+update_timing -full
+report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/2post_opt_placement_timing.rep
+
+check_clock_trees -clocks clk
+synthesize_clock_trees -clocks clk
+clock_opt
+update_timing -full
+report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/3post_clock_opt_placement_timing.rep
+save_lib -all
+
+#Start Routing
+route_auto
+update_timing -full
+
+report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/final_timing.rep
+report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/final_power.rep
+save_lib -all
+exit
diff --git a/ASIC/60pin/Synopsys/scripts/power_plan.tcl b/ASIC/60pin/Synopsys/scripts/power_plan.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..f6a77a6e4dc3298d6ef81a9e5f8ab08466b54211
--- /dev/null
+++ b/ASIC/60pin/Synopsys/scripts/power_plan.tcl
@@ -0,0 +1,38 @@
+connect_pg_net -automatic
+
+# Create Outer core ring
+create_pg_ring_pattern ring_pattern -horizontal_layer M9 -horizontal_width {5} -horizontal_spacing {2} -vertical_layer M8 -vertical_width {5} -vertical_spacing {2}
+set_pg_strategy core_ring -pattern {{name:ring_pattern} {nets: {VDD VDDIO VDDACC VSS}}{offset: {3 3}}} -core
+
+# Create vertical straps in Nanosoc region
+create_pg_mesh_pattern strap_pattern -layers {{{vertical_layer: M6} {width: 1} {pitch: 50} {spacing: interleaving} {trim: false}}}
+set_pg_strategy M6_straps -voltage_areas VA_TOP -pattern {{name: strap_pattern}{nets: VDD VSS}} -extension {{{stop : outermost_ring}}} -blockage {{{pg_regions : {pg_ACCEL}}}}
+
+# Create std cell rails in Nanosoc Region
+create_pg_std_cell_conn_pattern rail_pattern -layers M5
+set_pg_strategy M5_rails -voltage_areas VA_TOP -pattern {{name: rail_pattern}{nets: VDD VSS}} -extension {{{stop : outermost_ring}}} -blockage {{{pg_regions : {pg_ACCEL}}}}
+
+# Create rails for macros
+create_pg_macro_conn_pattern sram_pg_mesh -pin_conn_type long_pin -nets {VDD VSS} -direction horizontal -layers M5 -width 0.64 -spacing interleaving -pitch 3 -pin_layers {M4} -via_rule {{intersection : all}}
+set_pg_strategy sram_pg_mesh -macros {u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/u_rf_sp_hdf u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom \
+u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/u_rf_sp_hdf u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/u_rf_sp_hdf \
+u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/u_rf_sp_hdf} -pattern {{name : sram_pg_mesh}{nets : {VDD VSS}}}
+
+
+# Create ring for Accelerator Region
+# create_pg_ring_pattern acc_ring_pattern -horizontal_layer M9 -horizontal_width {3} -horizontal_spacing {1} -vertical_layer M8 -vertical_width {3} -vertical_spacing {1}
+# set_pg_strategy acc_ring -voltage_areas VA_ACCEL -pattern {{name:acc_ring_pattern} {nets: {VDDACC VSS}}}
+
+# Create std cell rails in Accelerator region
+create_pg_std_cell_conn_pattern acc_rail_pattern -layers M5
+set_pg_strategy acc_rails -voltage_areas VA_ACCEL -pattern {{name:acc_rail_pattern}{nets:{VDDACC VSS}}} -extension {{{stop: first_target}}}
+
+# Create straps for Accelerator region
+create_pg_mesh_pattern acc_strap_pattern -layers {{vertical_layer : M8} {width : 1} {spacing : interleaving} {pitch : 50} {trim : false}}
+set_pg_strategy M8_straps_acc -voltage_areas VA_ACCEL -pattern {{name: acc_strap_pattern}{nets: VDDACC VSS}} -extension {{{stop : outermost_ring}}}
+
+create_pg_mesh_pattern acc_mesh_pattern -layers {{horizontal_layer : M9} {width : 1} {spacing : interleaving} {pitch : 50} {trim : false}}
+set_pg_strategy M9_mesh_acc -voltage_areas VA_ACCEL -pattern {{name: acc_mesh_pattern}{nets: VDDACC VSS}} -extension {{{stop : outermost_ring}}}
+
+# Compile all power strategies
+compile_pg -strategies {core_ring M6_straps M5_rails acc_rails M8_straps_acc M9_mesh_acc sram_pg_mesh}
\ No newline at end of file
diff --git a/ASIC/60pin/Synopsys/scripts/synopsys_lib_conversion.tcl b/ASIC/60pin/Synopsys/scripts/synopsys_lib_conversion.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..6cc53b16baabb3dfbe14e567433cad2985c23c81
--- /dev/null
+++ b/ASIC/60pin/Synopsys/scripts/synopsys_lib_conversion.tcl
@@ -0,0 +1,35 @@
+set RF_PATH $env(SOCLABS_PROJECT_DIR)/memories/rf
+
+read_lib $RF_PATH/rf_sp_hdf_ss_1p08v_1p08v_125c.lib
+write_lib RF_LIB_ss_1p08v_1p08v_125c -output $RF_PATH/rf_sp_hdf_ss_1p08v_1p08v_125c.db
+
+read_lib $RF_PATH/rf_sp_hdf_ss_1p08v_1p08v_m40c.lib
+write_lib RF_LIB_ss_1p08v_1p08v_m40c -output $RF_PATH/rf_sp_hdf_ss_1p08v_1p08v_m40c.db
+
+read_lib $RF_PATH/rf_sp_hdf_ff_1p32v_1p32v_125c.lib
+write_lib RF_LIB_ff_1p32v_1p32v_125c -output $RF_PATH/rf_sp_hdf_ff_1p32v_1p32v_125c.db
+
+read_lib $RF_PATH/rf_sp_hdf_ff_1p32v_1p32v_m40c.lib
+write_lib RF_LIB_ff_1p32v_1p32v_m40c -output $RF_PATH/rf_sp_hdf_ff_1p32v_1p32v_m40c.db
+
+read_lib $RF_PATH/rf_sp_hdf_tt_1p20v_1p20v_25c.lib
+write_lib RF_LIB_tt_1p20v_1p20v_25c -output $RF_PATH/rf_sp_hdf_tt_1p20v_1p20v_25c.db
+
+set ROM_PATH $env(SOCLABS_PROJECT_DIR)/memories/bootrom
+
+read_lib $ROM_PATH/rom_via_ss_1p08v_1p08v_125c.lib
+write_lib USERLIB_ss_1p08v_1p08v_125c -output $ROM_PATH/rom_via_ss_1p08v_1p08v_125c.db
+
+read_lib $ROM_PATH/rom_via_ss_1p08v_1p08v_m40c.lib
+write_lib USERLIB_ss_1p08v_1p08v_m40c -output $ROM_PATH/rom_via_ss_1p08v_1p08v_m40c.db
+
+read_lib $ROM_PATH/rom_via_ff_1p32v_1p32v_125c.lib
+write_lib USERLIB_ff_1p32v_1p32v_125c -output $ROM_PATH/rom_via_ff_1p32v_1p32v_125c.db
+
+read_lib $ROM_PATH/rom_via_ff_1p32v_1p32v_m40c.lib
+write_lib USERLIB_ff_1p32v_1p32v_m40c -output $ROM_PATH/rom_via_ff_1p32v_1p32v_m40c.db
+
+read_lib $ROM_PATH/rom_via_tt_1p20v_1p20v_25c.lib
+write_lib USERLIB_tt_1p20v_1p20v_25c -output $ROM_PATH/rom_via_tt_1p20v_1p20v_25c.db
+
+exit
\ No newline at end of file
diff --git a/ASIC/60pin/Synopsys/scripts/synthesis.tcl b/ASIC/60pin/Synopsys/scripts/synthesis.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..0cc586503340e59a0bc690c71a136c776098f60f
--- /dev/null
+++ b/ASIC/60pin/Synopsys/scripts/synthesis.tcl
@@ -0,0 +1,83 @@
+#-----------------------------------------------------------------------------
+# NanoSoC Synopsys synthesis tcl file to be run with dc_shell
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# Daniel Newbrook (d.newbrook@soton.ac.uk)
+#
+# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+set rtlPath $env(SOCLABS_PROJECT_DIR)
+set report_path $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/
+set top_module nanosoc_chip_pads
+set io_path /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a
+#supress_message = {ELAB-405}
+#####
+# Set search_path
+#
+# List locations where your standard cell libraries may be located
+#
+#####
+set search_path [list . $search_path $env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/sdb/ $env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/db/ $env(SOCLABS_PROJECT_DIR)/memories/rf $env(SOCLABS_PROJECT_DIR)/memories/bootrom $io_path]
+set search_path [concat $rtlPath $search_path]
+######
+# Set Target Library
+#
+# Set a default target library for Design Compiler to target when compiling a design
+#
+######
+set target_library "sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.db rf_sp_hdf_ss_1p08v_1p08v_125c.db rom_via_ss_1p08v_1p08v_125c.db tpdn65lpnv2od3wc.db"
+
+######
+# Set Link Library
+#
+# Set a default link library for Design Compiler to target when compiling a design
+#
+######
+set link_library "sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.db rf_sp_hdf_ss_1p08v_1p08v_125c.db rom_via_ss_1p08v_1p08v_125c.db tpdn65lpnv2od3wc.db"
+
+source $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/dc_flist.tcl
+elaborate $top_module -lib WORK
+current_design $top_module
+
+# Link Design
+link
+
+read_sdc ../../constraints.sdc
+
+load_upf ../nanosoc_chip_pads.upf
+
+set_voltage -object_list {VDD VDDACC VDD_VSS.power VDDACC_VSS.power TOP.primary.power ACCEL.primary.power} 1.08
+set_voltage -object_list {VSS VDD_VSS.ground VDDACC_VSS.ground TOP.primary.ground ACCEL.primary.ground} 0.00
+
+set_operating_conditions -library sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c ss_typical_max_1p08v_125c
+
+set_app_var compile_delete_unloaded_sequential_cells false
+compile_ultra -gate_clock -scan
+
+set_scan_configuration -chain_count 2
+set_dft_signal -view spec -type ScanDataIn -port DFT_SDI_1
+set_dft_signal -view spec -type ScanDataIn -port DFT_SDI_2
+set_dft_signal -view spec -type ScanDataOut -port DFT_SDO_1
+set_dft_signal -view spec -type ScanDataOut -port DFT_SDO_2
+set_dft_signal -view spec -type ScanEnable -port TEST -active_state 1
+set_dft_signal -view existing_dft -type Reset -port NRST -active_state 0
+set_scan_configuration -power_domain_mixing false
+create_test_protocol -infer_clock -infer_asynch
+dft_drc
+insert_dft
+
+write -hierarchy -format verilog -output $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/Synopsys/nanosoc_chip_pads.vm
+write -hierarchy -format verilog -pg -output $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/Synopsys/nanosoc_chip_pads.vp
+write_scan_def -output $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/Synopsys/nanosoc_chip_pads.def
+write_test_protocol -output $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/Synopsys/nanosoc_chip_pads_scan.stil
+
+redirect [format "%s%s%s" $report_path $top_module _area.rep] { report_area }
+redirect -append [format "%s%s%s" $report_path $top_module _area.rep] { report_reference }
+redirect [format "%s%s%s" $report_path $top_module _power.rep] { report_power }
+redirect [format "%s%s%s" $report_path $top_module _scan_path.rep] { report_scan_path }
+redirect [format "%s%s%s" $report_path $top_module _timing.rep] \
+ { report_timing -path full -max_paths 100 -nets -transition_time -capacitance -significant_digits 3 -nosplit}
+
diff --git a/ASIC/60pin/Synopsys/upf/nanosoc_chip_pads.upf b/ASIC/60pin/Synopsys/upf/nanosoc_chip_pads.upf
new file mode 100644
index 0000000000000000000000000000000000000000..c6b9d33b87e24a28d6f60b9a88d1f65440e314bd
--- /dev/null
+++ b/ASIC/60pin/Synopsys/upf/nanosoc_chip_pads.upf
@@ -0,0 +1,57 @@
+#Scope: nanosoc_chip_pads
+create_supply_set VDDACC_VSS
+create_supply_set VDD_VSS
+
+#Domain: ACCEL
+create_power_domain ACCEL -supply {primary VDDACC_VSS} -elements {u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator}
+
+#Domain: TOP
+create_power_domain TOP -supply {primary VDD_VSS}
+
+associate_supply_set VDDACC_VSS -handle ACCEL.primary
+associate_supply_set VDD_VSS -handle TOP.primary
+
+create_supply_port VDDACC
+create_supply_port VDD
+create_supply_port VSS
+
+create_supply_net VDDACC
+create_supply_net VDD
+create_supply_net VSS
+
+connect_supply_net VDD -ports VDD
+connect_supply_net VDDACC -ports VDDACC
+connect_supply_net VSS -ports VSS
+
+
+create_supply_set VDDACC_VSS -function {power VDDACC} -function {ground VSS} -update
+create_supply_set VDD_VSS -function {power VDD} -function {ground VSS} -update
+
+
+connect_supply_net VDD -ports u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/u_rf_sp_hdf/VDD
+connect_supply_net VDD -ports u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/u_rf_sp_hdf/VDD
+connect_supply_net VDD -ports u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/u_rf_sp_hdf/VDD
+connect_supply_net VDD -ports u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/u_rf_sp_hdf/VDD
+connect_supply_net VDD -ports u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom/VDDE
+
+connect_supply_net VSS -ports u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/u_rf_sp_hdf/VSS
+connect_supply_net VSS -ports u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/u_rf_sp_hdf/VSS
+connect_supply_net VSS -ports u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/u_rf_sp_hdf/VSS
+connect_supply_net VSS -ports u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/u_rf_sp_hdf/VSS
+connect_supply_net VSS -ports u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom/VSSE
+
+add_port_state VSS -state {state1 0.00}
+add_port_state VDD -state {state1 1.08}
+add_port_state VDDACC -state {state1 1.08}
+
+create_pst all_pst -supplies { \
+ VDDACC \
+ VDD \
+ VSS}
+add_pst_state aon -pst all_pst -state {state1}
+
+
+
+
+
+
diff --git a/ASIC/Cadence/Genus/genus.tcl b/ASIC/Cadence/Genus/genus.tcl
deleted file mode 100644
index 64611b02647829fdf8be18da8d843b6209d96e11..0000000000000000000000000000000000000000
--- a/ASIC/Cadence/Genus/genus.tcl
+++ /dev/null
@@ -1,53 +0,0 @@
-set_db init_lib_search_path "$::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lib/ $::env(SOCLABS_PROJECT_DIR)/memories/rf/ $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/"
-set BASE_LIB sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.lib
-set RF_LIB rf_sp_hdf_ss_1p08v_1p08v_125c.lib
-set ROM_LIB rom_via_ss_1p08v_1p08v_125c.lib
-create_library_domain domain1
-set_db [get_db library_domains domain1] .library "$BASE_LIB $RF_LIB $ROM_LIB"
-
-read_power_intent -cpf -module nanosoc_chip_pads nanosoc.cpf
-
-source $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/genus_flist.tcl
-elaborate nanosoc_chip_pads
-
-apply_power_intent
-check_library > lib_check.log
-
-check_cpf
-
-commit_power_intent
-check_power_structure -license lpgxl
-
-read_sdc $::env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/constraints.sdc
-
-set_db dft_scan_style muxed_scan
-define_test_signal -function test_mode TEST
-define_test_signal -function shift_enable SWDIO -shared_input
-define_test_signal -function scan_clock SWDCK -shared_input
-define_test_signal -function async_set_reset -active low NRST
-check_dft_rules
-
-
-set_db syn_generic_effort high
-set_db syn_map_effort high
-
-syn_generic
-syn_map
-syn_opt
-
-report_area > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_area.rep
-report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_timing.rep
-report_gates > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_gates.rep
-report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_power.rep
-
-write_hdl > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads.vm
-
-connect_scan_chains -auto_create_chains
-report_scan_chains > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_scan_chains.rep
-report_scan_setup > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_scan_setup.rep
-report_scan_registers > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_scan_registers.rep
-
-write_dft_abstract_model > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_dft_abstract_model
-write_scandef > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads.def
-
-exit
diff --git a/ASIC/Cadence/Innovus/io_plan.tcl b/ASIC/Cadence/Innovus/io_plan.tcl
deleted file mode 100644
index 2afa6e7d9f57b19566862e072813a71e5b81f3a1..0000000000000000000000000000000000000000
--- a/ASIC/Cadence/Innovus/io_plan.tcl
+++ /dev/null
@@ -1,16 +0,0 @@
-################################
-# Script : IO Place
-# Author : Srimanth Tenneti
-# Date : 22nd May 2022
-###############################
-
-### Pin Place
-edit_pin -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Top -layer 9 -spread_type center -spacing 90 -pin { TEST VDD VDDIO VDDACC {P1[15]} {P1[14]} {P1[13]} {P1[12]} {P1[11]}}
-
-edit_pin -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Bottom -layer 9 -spread_type center -spacing 90 -pin {{P0[5]} {P0[6]} {P0[7]} {P0[8]} {P0[9]} {P0[10]} {P0[11]} {P0[12]} {P0[13]} {P0[14]} {P0[15]}}
-
-edit_pin -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Left -layer 9 -spread_type center -spacing 90 -pin {NRST CLK SWDIO SWDCK VSS VSSIO {P0[0]} {P0[1]} {P0[2]} {P0[3]} {P0[4]}}
-
-edit_pin -pin_width 1.5 -pin_depth 1.5 -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Right -layer 9 -spread_type center -spacing 90 -pin {{P1[0]} {P1[1]} {P1[2]} {P1[3]} {P1[4]} {P1[5]} {P1[6]} {P1[7]} {P1[8]} {P1[9]} {P1[10]} }
-
-gui_fit
diff --git a/ASIC/Cadence/Innovus/pnr_flow.tcl b/ASIC/Cadence/Innovus/pnr_flow.tcl
deleted file mode 100644
index 1b7de8a4a513d8ffb89ddaf9e7ca60c276d9a410..0000000000000000000000000000000000000000
--- a/ASIC/Cadence/Innovus/pnr_flow.tcl
+++ /dev/null
@@ -1,45 +0,0 @@
-######################################
-# Script : Place and Route Flow
-# Date : 25th May 2023
-# Author : Srimanth Tenneti
-# Description : Innovus PnR Flow
-######################################
-
-puts "Starting PnR Flow ..."
-
-
-### Design Import
-source design_import.tcl
-
-### IO Planning
-source io_plan.tcl
-
-### Memory and accelerator placement
-source place_macros.tcl
-commit_power_intent
-check_power_domains
-
-### Power Plan
-source power_plan.tcl
-
-### Power Route
-source power_route.tcl
-
-### Placement
-source place.tcl
-
-### CTS
-source clock_tree_synthesis.tcl
-
-### Routing
-source route.tcl
-
-report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_timing.rep
-report_area > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_area.rep
-report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_power.rep
-
-gui_show
-
-
-
-
diff --git a/ASIC/Cadence/Innovus/power_plan.tcl b/ASIC/Cadence/Innovus/power_plan.tcl
deleted file mode 100644
index 6d516c86bed7db8979296769202ab4308d92b4a8..0000000000000000000000000000000000000000
--- a/ASIC/Cadence/Innovus/power_plan.tcl
+++ /dev/null
@@ -1,42 +0,0 @@
-#########################################
-# Script : Power Planning
-# Tool : Cadence Innovus
-# Date : May 22, 2023
-# Author : Srimanth Tenneti
-#########################################
-
-### Connecting Global Nets
-connect_global_net VDD -type pg_pin -pin_base_name VDD -inst_base_name *
-connect_global_net VDDACC -type pg_pin -pin_base_name VDDACC -inst_base_name *
-connect_global_net VDDIO -type pg_pin -pin_base_name VDDIO -inst_base_name *
-connect_global_net VSS -type pg_pin -pin_base_name VSS -inst_base_name *
-connect_global_net VSSIO -type pg_pin -pin_base_name VSSIO -inst_base_name *
-### Top and Bottom Metal Declartions
-set_db add_rings_stacked_via_top_layer M8
-set_db add_rings_stacked_via_bottom_layer M1
-
-### Adding Rings
-add_rings -nets {VDD VDDACC VDDIO VSS VSSIO} -type core_rings -follow core -layer {top M7 bottom M7 left M8 right M8} -width {top 8 bottom 8 left 8 right 8} -spacing {top 2 bottom 2 left 2 right 2} -offset {top 1 bottom 1 left 1 right 1} -center 0 -threshold 0 -jog_distance 0 -snap_wire_center_to_grid none
-
-### Adding Stripes
-set_db add_stripes_ignore_block_check true
-set_db add_stripes_break_at none
-set_db add_stripes_route_over_rows_only false
-set_db add_stripes_rows_without_stripes_only false
-set_db add_stripes_extend_to_closest_target none
-set_db add_stripes_stop_at_last_wire_for_area false
-set_db add_stripes_partial_set_through_domain true
-set_db add_stripes_ignore_non_default_domains false
-set_db add_stripes_trim_antenna_back_to_shape none
-set_db add_stripes_spacing_type edge_to_edge
-set_db add_stripes_spacing_from_block 0
-set_db add_stripes_stripe_min_length stripe_width
-set_db add_stripes_stacked_via_top_layer AP
-set_db add_stripes_stacked_via_bottom_layer M1
-set_db add_stripes_via_using_exact_crossover_size false
-set_db add_stripes_split_vias false
-set_db add_stripes_orthogonal_only true
-set_db add_stripes_allow_jog { padcore_ring block_ring }
-set_db add_stripes_skip_via_on_pin { standardcell }
-set_db add_stripes_skip_via_on_wire_shape { noshape }
-add_stripes -nets {VDD VDDACC VSS} -layer M8 -direction vertical -width 4 -spacing 1.8 -number_of_sets 8 -extend_to last_padring -start_from left -start_offset 100 -stop_offset 100 -switch_layer_over_obs false -max_same_layer_jog_length 2 -pad_core_ring_top_layer_limit AP -pad_core_ring_bottom_layer_limit M1 -block_ring_top_layer_limit AP -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none
diff --git a/ASIC/Cadence/Innovus/power_route.tcl b/ASIC/Cadence/Innovus/power_route.tcl
deleted file mode 100644
index 90f207d636ea6017c040b7bf4d3a81a4d3f22f28..0000000000000000000000000000000000000000
--- a/ASIC/Cadence/Innovus/power_route.tcl
+++ /dev/null
@@ -1,10 +0,0 @@
-##################################
-# Script : Special Route Script
-# Date : May 24, 2023
-# Description : Power Routing
-# Author : Srimanth Tenneti
-##################################
-route_special -connect {block_pin pad_pin pad_ring core_pin floating_stripe} -layer_change_range { M1(1) AP(10) } -block_pin_target nearest_target -pad_pin_port_connect {all_port one_geom} -pad_pin_target nearest_target -core_pin_target first_after_row_end -floating_stripe_target {block_ring pad_ring ring stripe ring_pin block_pin followpin} -allow_jogging 1 -power_domains { ACCEL } -crossover_via_layer_range { M1(1) AP(10) } -nets { VDDACC VSS } -allow_layer_change 1 -block_pin use_lef -target_via_layer_range { M1(1) AP(10) }
-route_special -connect {block_pin pad_pin pad_ring core_pin floating_stripe} -layer_change_range { M1(1) AP(10) } -block_pin_target nearest_target -pad_pin_port_connect {all_port one_geom} -pad_pin_target nearest_target -core_pin_target first_after_row_end -floating_stripe_target {block_ring pad_ring ring stripe ring_pin block_pin followpin} -allow_jogging 1 -power_domains { TOP } -crossover_via_layer_range { M1(1) AP(10) } -nets { VDD VSS } -allow_layer_change 1 -block_pin use_lef -target_via_layer_range { M1(1) AP(10) }
-
-#route_special -nets {VDD VSS} -connect core_pin -block_pin_target nearest_target -core_pin_target first_after_row_end -allow_jogging 1 -allow_layer_change 1 -layer_change_range { M1(1) M8(8) } -crossover_via_layer_range { M1(1) M8(8) } -target_via_layer_range { M1(1) M8(8) }
diff --git a/ASIC/Synopsys/DC/synopsys.tcl b/ASIC/Synopsys/DC/synopsys.tcl
deleted file mode 100644
index 42aef1b72937c50fe81fc3381e07e94c5f3f7f7c..0000000000000000000000000000000000000000
--- a/ASIC/Synopsys/DC/synopsys.tcl
+++ /dev/null
@@ -1,119 +0,0 @@
-#-----------------------------------------------------------------------------
-# NanoSoC Synopsys synthesis tcl file to be run with dc_shell
-# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-#
-# Contributors
-#
-# Daniel Newbrook (d.newbrook@soton.ac.uk)
-#
-# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
-#-----------------------------------------------------------------------------
-
-set rtlPath $env(SOCLABS_PROJECT_DIR)
-set report_path $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/
-set top_module nanosoc_chip_pads
-#supress_message = {ELAB-405}
-#####
-# Set search_path
-#
-# List locations where your standard cell libraries may be located
-#
-#####
-set search_path [list . $search_path $env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/sdb/ $env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/db/ $env(SOCLABS_PROJECT_DIR)/memories/rf $env(SOCLABS_PROJECT_DIR)/memories/bootrom]
-set search_path [concat $rtlPath $search_path]
-######
-# Set Target Library
-#
-# Set a default target library for Design Compiler to target when compiling a design
-#
-######
-set target_library "sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.db rf_sp_hdf_ss_1p08v_1p08v_125c.db rom_via_ss_1p08v_1p08v_125c.db"
-
-######
-# Set Link Library
-#
-# Set a default link library for Design Compiler to target when compiling a design
-#
-######
-set link_library "sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.db rf_sp_hdf_ss_1p08v_1p08v_125c.db rom_via_ss_1p08v_1p08v_125c.db"
-
-source $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/dc_flist.tcl
-elaborate $top_module -lib WORK
-current_design $top_module
-
-# Link Design
-link
-
-read_sdc ../../constraints.sdc
-
-add_port_state VSS -state {state1 0.00}
-add_port_state VDD -state {state1 1.08}
-add_port_state VSSACC -state {state1 0.00}
-add_port_state VDDACC -state {state1 1.08}
-add_port_state VSSIO -state {state1 0.00}
-add_port_state VDDIO -state {state1 3.3}
-
-# Visual UPF added these lines...
-#Scope: nanosoc_chip_pads
-create_supply_set SSET1
-create_supply_set SSET2
-#Domain: ACCEL
-create_power_domain ACCEL -elements {u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator}
-set_domain_supply_net ACCEL -primary_power_net SSET2.power -primary_ground_net SSET2.ground
-
-#Domain: MEM
-create_power_domain MEM -elements {u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram}
-set_domain_supply_net MEM -primary_power_net SSET1.power -primary_ground_net SSET1.ground
-
-#Domain: TOP
-create_power_domain TOP
-set_domain_supply_net TOP -primary_power_net SSET1.power -primary_ground_net SSET1.ground
-
-add_power_state SSET1 -state state1 { -supply_expr {power == `{FULL_ON, 1.080000}}}
-add_power_state SSET1 -state state2 { -supply_expr {ground == `{FULL_ON, 0.000000}}}
-add_power_state SSET2 -state state3 { -supply_expr {power == `{FULL_ON, 1.080000}}}
-add_power_state SSET2 -state state4 { -supply_expr {ground == `{FULL_ON, 0.000000}}}
-
-
-connect_supply_net SSET1.power -port VDD
-connect_supply_net SSET1.ground -port VSS
-connect_supply_net SSET2.power -port VDDACC
-connect_supply_net SSET2.ground -port VSSACC
-
-set_voltage -object_list {SSET1.power SSET2.power MEM.primary.power TOP.primary.power ACCEL.primary.power} 1.08
-set_voltage -object_list {SSET1.ground SSET2.ground MEM.primary.ground TOP.primary.ground ACCEL.primary.ground} 0.00
-
-
-connect_supply_net MEM.primary.power -ports u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/u_rf_sp_hdf/VDD
-connect_supply_net MEM.primary.power -ports u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/u_rf_sp_hdf/VDD
-connect_supply_net MEM.primary.power -ports u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/u_rf_sp_hdf/VDD
-connect_supply_net MEM.primary.power -ports u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/u_rf_sp_hdf/VDD
-connect_supply_net MEM.primary.power -ports u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom/VDDE
-
-
-connect_supply_net MEM.primary.ground -ports u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/u_rf_sp_hdf/VSS
-connect_supply_net MEM.primary.ground -ports u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/u_rf_sp_hdf/VSS
-connect_supply_net MEM.primary.ground -ports u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/u_rf_sp_hdf/VSS
-connect_supply_net MEM.primary.ground -ports u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/u_rf_sp_hdf/VSS
-connect_supply_net MEM.primary.ground -ports u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom/VSSE
-
-
-set_app_var compile_delete_unloaded_sequential_cells false
-compile_ultra -gate_clock -scan
-
-set_scan_configuration -chain_count 1
-create_test_protocol -infer_clock -infer_asynch
-dft_drc
-insert_dft
-
-write -hierarchy -format verilog -output $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/Synopsys/nanosoc_chip_pads.vm
-write_scan_def -output $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/Synopsys/nanosoc_chip_pads.def
-write_test_protocol -output $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/Synopsys/nanosoc_chip_pads_scan.stil
-
-redirect [format "%s%s%s" $report_path $top_module _area.rep] { report_area }
-redirect -append [format "%s%s%s" $report_path $top_module _area.rep] { report_reference }
-redirect [format "%s%s%s" $report_path $top_module _power.rep] { report_power }
-redirect [format "%s%s%s" $report_path $top_module _scan_path.rep] { report_scan_path }
-redirect [format "%s%s%s" $report_path $top_module _timing.rep] \
- { report_timing -path full -max_paths 100 -nets -transition_time -capacitance -significant_digits 3 -nosplit}
-
diff --git a/ASIC/constraints.sdc b/ASIC/constraints.sdc
index 997304c40cb91a0852168fcc4b9e86926e268caa..b8b469bde43bfc03974a2c206dc0cbbb3061f67b 100644
--- a/ASIC/constraints.sdc
+++ b/ASIC/constraints.sdc
@@ -41,6 +41,13 @@ set_clock_transition -rise -max $MAXRISE [get_clocks $SWDCLK]
set_clock_transition -fall -min $MINFALL [get_clocks $SWDCLK]
set_clock_transition -fall -min $MINFALL [get_clocks $SWDCLK]
+### Multicycle path through pads
+
+set_false_path -from uPAD_SWDIO_IO/* -to uPAD_SWDIO_IO/*
+set_false_path -from uPAD_P0_*/* -to uPAD_P0_*/*
+set_false_path -from uPAD_P1_*/* -to uPAD_P1_*/*
+
+
#### DELAY DEFINITION
set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.3 [get_ports NRST]
@@ -49,5 +56,5 @@ set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.3 [get_ports P0]
set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.3 [get_ports P1]
set_input_delay -clock [get_clocks $SWDCLK] -add_delay 0.3 [get_ports SWDIO]
-set_max_capacitance 0.5 [all_outputs]
+set_max_capacitance 3 [all_outputs]
set_max_fanout 10 [all_inputs]
\ No newline at end of file
diff --git a/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_28pin.v b/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_28pin.v
new file mode 100644
index 0000000000000000000000000000000000000000..3ce7c03286ff099c5d7ffe269595898941917468
--- /dev/null
+++ b/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_28pin.v
@@ -0,0 +1,341 @@
+//-----------------------------------------------------------------------------
+// Top-Level Pad implementation for TSMC65nm
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Top level for example Cortex-M0/Cortex-M0+ microcontroller
+//-----------------------------------------------------------------------------
+//
+`define POWER_PINS
+module nanosoc_chip_pads (
+ inout wire VDDIO,
+ inout wire VDD,
+ inout wire VSS,
+ inout wire VDDACC,
+
+ input wire CLK, // input
+ input wire TEST, // input
+ input wire NRST, // active low reset
+ inout wire [3:0] P0,
+ inout wire [3:0] P1,
+ inout wire SWDIO,
+ input wire SWDCK,
+);
+
+
+//------------------------------------
+// internal wires
+
+ wire clk_i;
+ wire test_i;
+ wire nrst_i;
+ wire [15:0] p0_i; // level-shifted input from pad
+ wire [15:0] p0_o; // output port drive
+ wire [15:0] p0_e; // active high output drive enable (pad tech dependent)
+ wire [15:0] p0_z; // active low output drive enable (pad tech dependent)
+ wire [15:0] p1_i; // level-shifted input from pad
+ wire [15:0] p1_o; // output port drive
+ wire [15:0] p1_e; // active high output drive enable (pad tech dependent)
+ wire [15:0] p1_z; // active low output drive enable (pad tech dependent)
+
+ wire swdio_i;
+ wire swdio_o;
+ wire swdio_e;
+ wire swdio_z;
+ wire swdclk_i;
+ wire VSSIO;
+
+ assign VSSIO = VSS;
+ // --------------------------------------------------------------------------------
+ // Cortex-M0 nanosoc Microcontroller
+ // --------------------------------------------------------------------------------
+
+ nanosoc_chip u_nanosoc_chip (
+`ifdef POWER_PINS
+ .VDDIO (VDDIO),
+ .VSSIO (VSSIO),
+ .VDD (VDD),
+ .VSS (VSS),
+ .VDDACC (VDDACC),
+`endif
+ .clk_i(clk_i),
+ .test_i(test_i),
+ .nrst_i(nrst_i),
+ .p0_i(p0_i), // level-shifted input from pad
+ .p0_o(p0_o), // output port drive
+ .p0_e(p0_e), // active high output drive enable (pad tech dependent)
+ .p0_z(p0_z), // active low output drive enable (pad tech dependent)
+ .p1_i(p1_i), // level-shifted input from pad
+ .p1_o(p1_o), // output port drive
+ .p1_e(p1_e), // active high output drive enable (pad tech dependent)
+ .p1_z(p1_z), // active low output drive enable (pad tech dependent)
+ .swdio_i(swdio_i),
+ .swdio_o(swdio_o),
+ .swdio_e(swdio_e),
+ .swdio_z(swdio_z),
+ .swdclk_i(swdclk_i)
+ );
+
+
+//TIE_HI uTIEHI (.tiehi(tiehi));
+ wire tiehi = 1'b1;
+//TIE_LO uTIELO (.tielo(tielo));
+ wire tielo = 1'b0;
+
+ // --------------------------------------------------------------------------------
+ // IO pad (TSMC 65nm mapping)
+ // --------------------------------------------------------------------------------
+
+// Pad IO power supplies
+
+PVDD2CDG uPAD_VDDIO_0(
+ .VDDPST(VDDIO)
+ );
+PVDD2CDG uPAD_VDDIO_1(
+ .VDDPST(VDDIO)
+ );
+PVDD2CDG uPAD_VDDIO_2(
+ .VDDPST(VDDIO)
+ );
+PVDD2POC uPAD_VDDIO_3(
+ .VDDPST(VDDIO)
+ );
+
+
+
+// Core power supplies
+
+PVDD1CDG uPAD_VDD_0(
+ .VDD(VDD)
+ );
+PVDD1CDG uPAD_VDD_1(
+ .VDD(VDD)
+ );
+PVDD1CDG uPAD_VDD_2(
+ .VDD(VDD)
+ );
+PVDD1CDG uPAD_VDD_3(
+ .VDD(VDD)
+ );
+
+PVSS3CDG uPAD_VSS_0(
+ .VSS(VSS)
+ );
+PVSS3CDG uPAD_VSS_1(
+ .VSS(VSS)
+ );
+PVSS3CDG uPAD_VSS_2(
+ .VSS(VSS)
+ );
+PVSS3CDG uPAD_VSS_3(
+ .VSS(VSS)
+ );
+// Accelerator Power supplies
+PVDD1CDG uPAD_VDDACC_0(
+ .VDD(VDDACC)
+ );
+PVDD1CDG uPAD_VDDACC_1(
+ .VDD(VDDACC)
+ );
+PVDD1CDG uPAD_VDDACC_2(
+ .VDD(VDDACC)
+ );
+
+// Clock, Reset and Serial Wire Debug ports
+
+PRDW0408SCDG uPAD_CLK_I (
+ .IE(tiehi),
+ .C(clk_i),
+ .PE(tielo),
+ .DS(tielo),
+ .I(tielo),
+ .OEN(tiehi),
+ .PAD(CLK)
+ );
+
+PRDW0408SCDG uPAD_TEST_I (
+ .IE(tiehi),
+ .C(test_i),
+ .PE(tielo),
+ .DS(tielo),
+ .I(tielo),
+ .OEN(tiehi),
+ .PAD(TEST)
+ );
+
+PRDW0408SCDG uPAD_NRST_I (
+ .IE(tiehi),
+ .C(nrst_i),
+ .PE(tielo),
+ .DS(tielo),
+ .I(tielo),
+ .OEN(tiehi),
+ .PAD(NRST)
+ );
+
+PRDW0408SCDG uPAD_SWDIO_IO (
+ .IE(swdio_z),
+ .C(swdio_i),
+ .PE(tielo),
+ .DS(tielo),
+ .I(swdio_o),
+ .OEN(swdio_z),
+ .PAD(SWDIO)
+ );
+
+PRDW0408SCDG uPAD_SWDCK_I (
+ .IE(tiehi),
+ .C(swdclk_i),
+ .PE(tielo),
+ .DS(tielo),
+ .I(tielo),
+ .OEN(tiehi),
+ .PAD(SWDCK)
+ );
+
+// GPI.I Port 0 x 16
+
+PRDW0408SCDG uPAD_P0_00 (
+ .IE(p0_z[00]),
+ .C(p0_i[00]),
+ .PE(p0_z[00]&p0_o[00]),
+ .DS(tielo),
+ .I(p0_o[00]),
+ .OEN(p0_z[00]),
+ .PAD(P0[00])
+ );
+
+PRDW0408SCDG uPAD_P0_01 (
+ .IE(p0_z[01]),
+ .C(p0_i[01]),
+ .PE(p0_z[01]&p0_o[01]),
+ .DS(tielo),
+ .I(p0_o[01]),
+ .OEN(p0_z[01]),
+ .PAD(P0[01])
+ );
+
+PRDW0408SCDG uPAD_P0_02 (
+ .IE(p0_z[02]),
+ .C(p0_i[02]),
+ .PE(p0_z[02]&p0_o[02]),
+ .DS(tielo),
+ .I(p0_o[02]),
+ .OEN(p0_z[02]),
+ .PAD(P0[02])
+ );
+
+PRDW0408SCDG uPAD_P0_03 (
+ .IE(p0_z[03]),
+ .C(p0_i[03]),
+ .PE(p0_z[03]&p0_o[03]),
+ .DS(tielo),
+ .I(p0_o[03]),
+ .OEN(p0_z[03]),
+ .PAD(P0[03])
+ );
+// GPI.I Port 1 x 16
+
+PRDW0408SCDG uPAD_P1_00 (
+ .IE(p1_z[00]),
+ .C(p1_i[00]),
+ .PE(p1_z[00]&p1_o[00]),
+ .DS(tielo),
+ .I(p1_o[00]),
+ .OEN(p1_z[00]),
+ .PAD(P1[00])
+ );
+
+PRDW0408SCDG uPAD_P1_01 (
+ .IE(p1_z[01]),
+ .C(p1_i[01]),
+ .PE(p1_z[01]&p1_o[01]),
+ .DS(tielo),
+ .I(p1_o[01]),
+ .OEN(p1_z[01]),
+ .PAD(P1[01])
+ );
+
+PRDW0408SCDG uPAD_P1_02 (
+ .IE(p1_z[02]),
+ .C(p1_i[02]),
+ .PE(p1_z[02]&p1_o[02]),
+ .DS(tielo),
+ .I(p1_o[02]),
+ .OEN(p1_z[02]),
+ .PAD(P1[02])
+ );
+
+PRDW0408SCDG uPAD_P1_03 (
+ .IE(p1_z[03]),
+ .C(p1_i[03]),
+ .PE(p1_z[03]&p1_o[03]),
+ .DS(tielo),
+ .I(p1_o[03]),
+ .OEN(p1_z[03]),
+ .PAD(P1[03])
+ );
+
+
+// GPIO unused pin tie offs
+
+assign p0_i[4] = p0_o[4] & p0_e[4];
+assign p0_i[5] = p0_o[5] & p0_e[5];
+assign p0_i[6] = p0_o[6] & p0_e[6];
+assign p0_i[7] = p0_o[7] & p0_e[7];
+assign p0_i[8] = p0_o[8] & p0_e[8];
+assign p0_i[9] = p0_o[9] & p0_e[9];
+assign p0_i[10] = p0_o[10] & p0_e[10];
+assign p0_i[11] = p0_o[11] & p0_e[11];
+assign p0_i[12] = p0_o[12] & p0_e[12];
+assign p0_i[13] = p0_o[13] & p0_e[13];
+assign p0_i[14] = p0_o[14] & p0_e[14];
+assign p0_i[15] = p0_o[15] & p0_e[15];
+
+assign p1_i[4] = p1_o[4] & p1_e[4];
+assign p1_i[5] = p1_o[5] & p1_e[5];
+assign p1_i[6] = p1_o[6] & p1_e[6];
+assign p1_i[7] = p1_o[7] & p1_e[7];
+assign p1_i[8] = p1_o[8] & p1_e[8];
+assign p1_i[9] = p1_o[9] & p1_e[9];
+assign p1_i[10] = p1_o[10] & p1_e[10];
+assign p1_i[11] = p1_o[11] & p1_e[11];
+assign p1_i[12] = p1_o[12] & p1_e[12];
+assign p1_i[13] = p1_o[13] & p1_e[13];
+assign p1_i[14] = p1_o[14] & p1_e[14];
+assign p1_i[15] = p1_o[15] & p1_e[15];
+
+
+endmodule
+
+
+
diff --git a/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_44pin.v b/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_44pin.v
new file mode 100644
index 0000000000000000000000000000000000000000..a73a32c5856f14f081e42c3be23fa9bcd44fd8d1
--- /dev/null
+++ b/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_44pin.v
@@ -0,0 +1,415 @@
+//-----------------------------------------------------------------------------
+// Top-Level Pad implementation for TSMC65nm
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Top level for example Cortex-M0/Cortex-M0+ microcontroller
+//-----------------------------------------------------------------------------
+//
+`define POWER_PINS
+module nanosoc_chip_pads (
+ inout wire VDDIO,
+ inout wire VSSIO,
+ inout wire VDD,
+ inout wire VSS,
+ inout wire VDDACC,
+
+ input wire CLK, // input
+ input wire TEST, // input
+ input wire NRST, // active low reset
+ inout wire [7:0] P0,
+ inout wire [7:0] P1,
+ inout wire SWDIO,
+ input wire SWDCK);
+
+
+//------------------------------------
+// internal wires
+
+ wire clk_i;
+ wire test_i;
+ wire nrst_i;
+ wire [15:0] p0_i; // level-shifted input from pad
+ wire [15:0] p0_o; // output port drive
+ wire [15:0] p0_e; // active high output drive enable (pad tech dependent)
+ wire [15:0] p0_z; // active low output drive enable (pad tech dependent)
+ wire [15:0] p1_i; // level-shifted input from pad
+ wire [15:0] p1_o; // output port drive
+ wire [15:0] p1_e; // active high output drive enable (pad tech dependent)
+ wire [15:0] p1_z; // active low output drive enable (pad tech dependent)
+
+ wire swdio_i;
+ wire swdio_o;
+ wire swdio_e;
+ wire swdio_z;
+ wire swdclk_i;
+
+ // --------------------------------------------------------------------------------
+ // Cortex-M0 nanosoc Microcontroller
+ // --------------------------------------------------------------------------------
+
+ nanosoc_chip u_nanosoc_chip (
+`ifdef POWER_PINS
+ .VDDIO (VDDIO),
+ .VSSIO (VSSIO),
+ .VDD (VDD),
+ .VSS (VSS),
+ .VDDACC (VDDACC),
+`endif
+ .clk_i(clk_i),
+ .test_i(test_i),
+ .nrst_i(nrst_i),
+ .p0_i(p0_i), // level-shifted input from pad
+ .p0_o(p0_o), // output port drive
+ .p0_e(p0_e), // active high output drive enable (pad tech dependent)
+ .p0_z(p0_z), // active low output drive enable (pad tech dependent)
+ .p1_i(p1_i), // level-shifted input from pad
+ .p1_o(p1_o), // output port drive
+ .p1_e(p1_e), // active high output drive enable (pad tech dependent)
+ .p1_z(p1_z), // active low output drive enable (pad tech dependent)
+ .swdio_i(swdio_i),
+ .swdio_o(swdio_o),
+ .swdio_e(swdio_e),
+ .swdio_z(swdio_z),
+ .swdclk_i(swdclk_i)
+ );
+
+
+//TIE_HI uTIEHI (.tiehi(tiehi));
+ wire tiehi = 1'b1;
+//TIE_LO uTIELO (.tielo(tielo));
+ wire tielo = 1'b0;
+
+
+ wire dft_sdi_1, dft_sdi_2, dft_sdo_1, dft_sdo_2;
+ // --------------------------------------------------------------------------------
+ // IO pad (GLIB Generic Library napping)
+ // --------------------------------------------------------------------------------
+
+// Pad IO power supplies
+
+PVDD2CDG uPAD_VDDIO_0(
+ .VDDPST(VDDIO)
+ );
+PVDD2CDG uPAD_VDDIO_1(
+ .VDDPST(VDDIO)
+ );
+PVDD2CDG uPAD_VDDIO_2(
+ .VDDPST(VDDIO)
+ );
+PVDD2POC uPAD_VDDIO_3(
+ .VDDPST(VDDIO)
+ );
+
+PVSS3CDG uPAD_VSSIO_0(
+ .VSS(VSS)
+ );
+PVSS3CDG uPAD_VSSIO_1(
+ .VSS(VSS)
+ );
+
+// Core power supplies
+
+PVDD1CDG uPAD_VDD_0(
+ .VDD(VDD)
+ );
+PVDD1CDG uPAD_VDD_1(
+ .VDD(VDD)
+ );
+PVDD1CDG uPAD_VDD_2(
+ .VDD(VDD)
+ );
+PVDD1CDG uPAD_VDD_3(
+ .VDD(VDD)
+ );
+
+PVSS3CDG uPAD_VSS_0(
+ .VSS(VSS)
+ );
+PVSS3CDG uPAD_VSS_1(
+ .VSS(VSS)
+ );
+PVSS3CDG uPAD_VSS_2(
+ .VSS(VSS)
+ );
+PVSS3CDG uPAD_VSS_3(
+ .VSS(VSS)
+ );
+// Accelerator Power supplies
+PVDD1CDG uPAD_VDDACC_0(
+ .VDD(VDDACC)
+ );
+PVDD1CDG uPAD_VDDACC_1(
+ .VDD(VDDACC)
+ );
+PVDD1CDG uPAD_VDDACC_2(
+ .VDD(VDDACC)
+ );
+
+// Clock, Reset and Serial Wire Debug ports
+
+PRDW0408SCDG uPAD_CLK_I (
+ .IE(tiehi),
+ .C(clk_i),
+ .PE(tielo),
+ .DS(tielo),
+ .I(tielo),
+ .OEN(tiehi),
+ .PAD(CLK)
+ );
+
+PRDW0408SCDG uPAD_TEST_I (
+ .IE(tiehi),
+ .C(test_i),
+ .PE(tielo),
+ .DS(tielo),
+ .I(tielo),
+ .OEN(tiehi),
+ .PAD(TEST)
+ );
+
+PRDW0408SCDG uPAD_NRST_I (
+ .IE(tiehi),
+ .C(nrst_i),
+ .PE(tielo),
+ .DS(tielo),
+ .I(tielo),
+ .OEN(tiehi),
+ .PAD(NRST)
+ );
+
+PRDW0408SCDG uPAD_SWDIO_IO (
+ .IE(swdio_z),
+ .C(swdio_i),
+ .PE(tielo),
+ .DS(tielo),
+ .I(swdio_o),
+ .OEN(swdio_z),
+ .PAD(SWDIO)
+ );
+
+PRDW0408SCDG uPAD_SWDCK_I (
+ .IE(tiehi),
+ .C(swdclk_i),
+ .PE(tielo),
+ .DS(tielo),
+ .I(tielo),
+ .OEN(tiehi),
+ .PAD(SWDCK)
+ );
+
+// GPI.I Port 0 x 16
+
+PRDW0408SCDG uPAD_P0_00 (
+ .IE(p0_z[00]),
+ .C(p0_i[00]),
+ .PE(p0_z[00]&p0_o[00]),
+ .DS(tielo),
+ .I(p0_o[00]),
+ .OEN(p0_z[00]),
+ .PAD(P0[00])
+ );
+
+PRDW0408SCDG uPAD_P0_01 (
+ .IE(p0_z[01]),
+ .C(p0_i[01]),
+ .PE(p0_z[01]&p0_o[01]),
+ .DS(tielo),
+ .I(p0_o[01]),
+ .OEN(p0_z[01]),
+ .PAD(P0[01])
+ );
+
+PRDW0408SCDG uPAD_P0_02 (
+ .IE(p0_z[02]),
+ .C(p0_i[02]),
+ .PE(p0_z[02]&p0_o[02]),
+ .DS(tielo),
+ .I(p0_o[02]),
+ .OEN(p0_z[02]),
+ .PAD(P0[02])
+ );
+
+PRDW0408SCDG uPAD_P0_03 (
+ .IE(p0_z[03]),
+ .C(p0_i[03]),
+ .PE(p0_z[03]&p0_o[03]),
+ .DS(tielo),
+ .I(p0_o[03]),
+ .OEN(p0_z[03]),
+ .PAD(P0[03])
+ );
+
+PRDW0408SCDG uPAD_P0_04 (
+ .IE(p0_z[04]),
+ .C(p0_i[04]),
+ .PE(p0_z[04]&p0_o[04]),
+ .DS(tielo),
+ .I(p0_o[04]),
+ .OEN(p0_z[04]),
+ .PAD(P0[04])
+ );
+
+PRDW0408SCDG uPAD_P0_05 (
+ .IE(p0_z[05]),
+ .C(p0_i[05]),
+ .PE(p0_z[05]&p0_o[05]),
+ .DS(tielo),
+ .I(p0_o[05]),
+ .OEN(p0_z[05]),
+ .PAD(P0[05])
+ );
+
+PRDW0408SCDG uPAD_P0_06 (
+ .IE(p0_z[06]),
+ .C(p0_i[06]),
+ .PE(p0_z[06]&p0_o[06]),
+ .DS(tielo),
+ .I(p0_o[06]),
+ .OEN(p0_z[06]),
+ .PAD(P0[06])
+ );
+
+PRDW0408SCDG uPAD_P0_07 (
+ .IE(p0_z[07]),
+ .C(p0_i[07]),
+ .PE(p0_z[07]&p0_o[07]),
+ .DS(tielo),
+ .I(p0_o[07]),
+ .OEN(p0_z[07]),
+ .PAD(P0[07])
+ );
+// GPI.I Port 1 x 16
+
+PRDW0408SCDG uPAD_P1_00 (
+ .IE(p1_z[00]),
+ .C(p1_i[00]),
+ .PE(p1_z[00]&p1_o[00]),
+ .DS(tielo),
+ .I(p1_o[00]),
+ .OEN(p1_z[00]),
+ .PAD(P1[00])
+ );
+
+PRDW0408SCDG uPAD_P1_01 (
+ .IE(p1_z[01]),
+ .C(p1_i[01]),
+ .PE(p1_z[01]&p1_o[01]),
+ .DS(tielo),
+ .I(p1_o[01]),
+ .OEN(p1_z[01]),
+ .PAD(P1[01])
+ );
+
+PRDW0408SCDG uPAD_P1_02 (
+ .IE(p1_z[02]),
+ .C(p1_i[02]),
+ .PE(p1_z[02]&p1_o[02]),
+ .DS(tielo),
+ .I(p1_o[02]),
+ .OEN(p1_z[02]),
+ .PAD(P1[02])
+ );
+
+PRDW0408SCDG uPAD_P1_03 (
+ .IE(p1_z[03]),
+ .C(p1_i[03]),
+ .PE(p1_z[03]&p1_o[03]),
+ .DS(tielo),
+ .I(p1_o[03]),
+ .OEN(p1_z[03]),
+ .PAD(P1[03])
+ );
+
+PRDW0408SCDG uPAD_P1_04 (
+ .IE(p1_z[04]),
+ .C(p1_i[04]),
+ .PE(p1_z[04]&p1_o[04]),
+ .DS(tielo),
+ .I(p1_o[04]),
+ .OEN(p1_z[04]),
+ .PAD(P1[04])
+ );
+
+PRDW0408SCDG uPAD_P1_05 (
+ .IE(p1_z[05]),
+ .C(p1_i[05]),
+ .PE(p1_z[05]&p1_o[05]),
+ .DS(tielo),
+ .I(p1_o[05]),
+ .OEN(p1_z[05]),
+ .PAD(P1[05])
+ );
+
+PRDW0408SCDG uPAD_P1_06 (
+ .IE(p1_z[06]),
+ .C(p1_i[06]),
+ .PE(p1_z[06]&p1_o[06]),
+ .DS(tielo),
+ .I(p1_o[06]),
+ .OEN(p1_z[06]),
+ .PAD(P1[06])
+ );
+
+PRDW0408SCDG uPAD_P1_07 (
+ .IE(p1_z[07]),
+ .C(p1_i[07]),
+ .PE(p1_z[07]&p1_o[07]),
+ .DS(tielo),
+ .I(p1_o[07]),
+ .OEN(p1_z[07]),
+ .PAD(P1[07])
+ );
+
+
+assign p0_i[8] = p0_o[8] & p0_e[8];
+assign p0_i[9] = p0_o[9] & p0_e[9];
+assign p0_i[10] = p0_o[10] & p0_e[10];
+assign p0_i[11] = p0_o[11] & p0_e[11];
+assign p0_i[12] = p0_o[12] & p0_e[12];
+assign p0_i[13] = p0_o[13] & p0_e[13];
+assign p0_i[14] = p0_o[14] & p0_e[14];
+assign p0_i[15] = p0_o[15] & p0_e[15];
+
+assign p1_i[8] = p1_o[8] & p1_e[8];
+assign p1_i[9] = p1_o[9] & p1_e[9];
+assign p1_i[10] = p1_o[10] & p1_e[10];
+assign p1_i[11] = p1_o[11] & p1_e[11];
+assign p1_i[12] = p1_o[12] & p1_e[12];
+assign p1_i[13] = p1_o[13] & p1_e[13];
+assign p1_i[14] = p1_o[14] & p1_e[14];
+assign p1_i[15] = p1_o[15] & p1_e[15];
+
+endmodule
+
+
+
diff --git a/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_60pin.v b/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_60pin.v
new file mode 100644
index 0000000000000000000000000000000000000000..c4b16345b107c9cbb9f25569a72b3342e28d9367
--- /dev/null
+++ b/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_60pin.v
@@ -0,0 +1,559 @@
+//-----------------------------------------------------------------------------
+// Top-Level Pad implementation for TSMC65nm
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from Arm Limited or its affiliates.
+//
+// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+// ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from Arm Limited or its affiliates.
+//
+// SVN Information
+//
+// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+//
+// Revision : $Revision: 371321 $
+//
+// Release Information : Cortex-M System Design Kit-r1p1-00rel0
+//
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Top level for example Cortex-M0/Cortex-M0+ microcontroller
+//-----------------------------------------------------------------------------
+//
+`define POWER_PINS
+module nanosoc_chip_pads (
+ inout wire VDDIO,
+ inout wire VSSIO,
+ inout wire VDD,
+ inout wire VSS,
+ inout wire VDDACC,
+
+ input wire CLK, // input
+ input wire TEST, // input
+ input wire NRST, // active low reset
+ inout wire [15:0] P0,
+ inout wire [15:0] P1,
+ inout wire SWDIO,
+ input wire SWDCK
+ );
+
+
+//------------------------------------
+// internal wires
+
+ wire clk_i;
+ wire test_i;
+ wire nrst_i;
+ wire [15:0] p0_i; // level-shifted input from pad
+ wire [15:0] p0_o; // output port drive
+ wire [15:0] p0_e; // active high output drive enable (pad tech dependent)
+ wire [15:0] p0_z; // active low output drive enable (pad tech dependent)
+ wire [15:0] p1_i; // level-shifted input from pad
+ wire [15:0] p1_o; // output port drive
+ wire [15:0] p1_e; // active high output drive enable (pad tech dependent)
+ wire [15:0] p1_z; // active low output drive enable (pad tech dependent)
+
+ wire swdio_i;
+ wire swdio_o;
+ wire swdio_e;
+ wire swdio_z;
+ wire swdclk_i;
+
+ // --------------------------------------------------------------------------------
+ // Cortex-M0 nanosoc Microcontroller
+ // --------------------------------------------------------------------------------
+
+ nanosoc_chip u_nanosoc_chip (
+`ifdef POWER_PINS
+ .VDDIO (VDDIO),
+ .VSSIO (VSSIO),
+ .VDD (VDD),
+ .VSS (VSS),
+ .VDDACC (VDDACC),
+`endif
+ .clk_i(clk_i),
+ .test_i(test_i),
+ .nrst_i(nrst_i),
+ .p0_i(p0_i), // level-shifted input from pad
+ .p0_o(p0_o), // output port drive
+ .p0_e(p0_e), // active high output drive enable (pad tech dependent)
+ .p0_z(p0_z), // active low output drive enable (pad tech dependent)
+ .p1_i(p1_i), // level-shifted input from pad
+ .p1_o(p1_o), // output port drive
+ .p1_e(p1_e), // active high output drive enable (pad tech dependent)
+ .p1_z(p1_z), // active low output drive enable (pad tech dependent)
+ .swdio_i(swdio_i),
+ .swdio_o(swdio_o),
+ .swdio_e(swdio_e),
+ .swdio_z(swdio_z),
+ .swdclk_i(swdclk_i)
+ );
+
+
+//TIE_HI uTIEHI (.tiehi(tiehi));
+ wire tiehi = 1'b1;
+//TIE_LO uTIELO (.tielo(tielo));
+ wire tielo = 1'b0;
+
+
+ wire dft_sdi_1, dft_sdi_2, dft_sdo_1, dft_sdo_2;
+ // --------------------------------------------------------------------------------
+ // IO pad (GLIB Generic Library napping)
+ // --------------------------------------------------------------------------------
+
+// Pad IO power supplies
+
+PVDD2CDG uPAD_VDDIO_0(
+ .VDDPST(VDDIO)
+ );
+PVDD2CDG uPAD_VDDIO_1(
+ .VDDPST(VDDIO)
+ );
+PVDD2CDG uPAD_VDDIO_2(
+ .VDDPST(VDDIO)
+ );
+PVDD2POC uPAD_VDDIO_3(
+ .VDDPST(VDDIO)
+ );
+
+PVSS3CDG uPAD_VSSIO_0(
+ .VSS(VSS)
+ );
+PVSS3CDG uPAD_VSSIO_1(
+ .VSS(VSS)
+ );
+
+
+// Core power supplies
+
+PVDD1CDG uPAD_VDD_0(
+ .VDD(VDD)
+ );
+PVDD1CDG uPAD_VDD_1(
+ .VDD(VDD)
+ );
+PVDD1CDG uPAD_VDD_2(
+ .VDD(VDD)
+ );
+PVDD1CDG uPAD_VDD_3(
+ .VDD(VDD)
+ );
+
+PVSS3CDG uPAD_VSS_0(
+ .VSS(VSS)
+ );
+PVSS3CDG uPAD_VSS_1(
+ .VSS(VSS)
+ );
+PVSS3CDG uPAD_VSS_2(
+ .VSS(VSS)
+ );
+PVSS3CDG uPAD_VSS_3(
+ .VSS(VSS)
+ );
+// Accelerator Power supplies
+PVDD1CDG uPAD_VDDACC_0(
+ .VDD(VDDACC)
+ );
+PVDD1CDG uPAD_VDDACC_1(
+ .VDD(VDDACC)
+ );
+PVDD1CDG uPAD_VDDACC_2(
+ .VDD(VDDACC)
+ );
+
+// Clock, Reset and Serial Wire Debug ports
+
+PRDW0408SCDG uPAD_CLK_I (
+ .IE(tiehi),
+ .C(clk_i),
+ .PE(tielo),
+ .DS(tielo),
+ .I(tielo),
+ .OEN(tiehi),
+ .PAD(CLK)
+ );
+
+PRDW0408SCDG uPAD_TEST_I (
+ .IE(tiehi),
+ .C(test_i),
+ .PE(tielo),
+ .DS(tielo),
+ .I(tielo),
+ .OEN(tiehi),
+ .PAD(TEST)
+ );
+
+PRDW0408SCDG uPAD_NRST_I (
+ .IE(tiehi),
+ .C(nrst_i),
+ .PE(tielo),
+ .DS(tielo),
+ .I(tielo),
+ .OEN(tiehi),
+ .PAD(NRST)
+ );
+
+PRDW0408SCDG uPAD_SWDIO_IO (
+ .IE(swdio_z),
+ .C(swdio_i),
+ .PE(tielo),
+ .DS(tielo),
+ .I(swdio_o),
+ .OEN(swdio_z),
+ .PAD(SWDIO)
+ );
+
+PRDW0408SCDG uPAD_SWDCK_I (
+ .IE(tiehi),
+ .C(swdclk_i),
+ .PE(tielo),
+ .DS(tielo),
+ .I(tielo),
+ .OEN(tiehi),
+ .PAD(SWDCK)
+ );
+
+// GPI.I Port 0 x 16
+
+PRDW0408SCDG uPAD_P0_00 (
+ .IE(p0_z[00]),
+ .C(p0_i[00]),
+ .PE(p0_z[00]&p0_o[00]),
+ .DS(tielo),
+ .I(p0_o[00]),
+ .OEN(p0_z[00]),
+ .PAD(P0[00])
+ );
+
+PRDW0408SCDG uPAD_P0_01 (
+ .IE(p0_z[01]),
+ .C(p0_i[01]),
+ .PE(p0_z[01]&p0_o[01]),
+ .DS(tielo),
+ .I(p0_o[01]),
+ .OEN(p0_z[01]),
+ .PAD(P0[01])
+ );
+
+PRDW0408SCDG uPAD_P0_02 (
+ .IE(p0_z[02]),
+ .C(p0_i[02]),
+ .PE(p0_z[02]&p0_o[02]),
+ .DS(tielo),
+ .I(p0_o[02]),
+ .OEN(p0_z[02]),
+ .PAD(P0[02])
+ );
+
+PRDW0408SCDG uPAD_P0_03 (
+ .IE(p0_z[03]),
+ .C(p0_i[03]),
+ .PE(p0_z[03]&p0_o[03]),
+ .DS(tielo),
+ .I(p0_o[03]),
+ .OEN(p0_z[03]),
+ .PAD(P0[03])
+ );
+
+PRDW0408SCDG uPAD_P0_04 (
+ .IE(p0_z[04]),
+ .C(p0_i[04]),
+ .PE(p0_z[04]&p0_o[04]),
+ .DS(tielo),
+ .I(p0_o[04]),
+ .OEN(p0_z[04]),
+ .PAD(P0[04])
+ );
+
+PRDW0408SCDG uPAD_P0_05 (
+ .IE(p0_z[05]),
+ .C(p0_i[05]),
+ .PE(p0_z[05]&p0_o[05]),
+ .DS(tielo),
+ .I(p0_o[05]),
+ .OEN(p0_z[05]),
+ .PAD(P0[05])
+ );
+
+PRDW0408SCDG uPAD_P0_06 (
+ .IE(p0_z[06]),
+ .C(p0_i[06]),
+ .PE(p0_z[06]&p0_o[06]),
+ .DS(tielo),
+ .I(p0_o[06]),
+ .OEN(p0_z[06]),
+ .PAD(P0[06])
+ );
+
+PRDW0408SCDG uPAD_P0_07 (
+ .IE(p0_z[07]),
+ .C(p0_i[07]),
+ .PE(p0_z[07]&p0_o[07]),
+ .DS(tielo),
+ .I(p0_o[07]),
+ .OEN(p0_z[07]),
+ .PAD(P0[07])
+ );
+
+PRDW0408SCDG uPAD_P0_08 (
+ .IE(p0_z[08]),
+ .C(p0_i[08]),
+ .PE(p0_z[08]&p0_o[08]),
+ .DS(tielo),
+ .I(p0_o[08]),
+ .OEN(p0_z[08]),
+ .PAD(P0[08])
+ );
+
+PRDW0408SCDG uPAD_P0_09 (
+ .IE(p0_z[09]),
+ .C(p0_i[09]),
+ .PE(p0_z[09]&p0_o[09]),
+ .DS(tielo),
+ .I(p0_o[09]),
+ .OEN(p0_z[09]),
+ .PAD(P0[09])
+ );
+
+PRDW0408SCDG uPAD_P0_10 (
+ .IE(p0_z[10]),
+ .C(p0_i[10]),
+ .PE(p0_z[10]&p0_o[10]),
+ .DS(tielo),
+ .I(p0_o[10]),
+ .OEN(p0_z[10]),
+ .PAD(P0[10])
+ );
+
+PRDW0408SCDG uPAD_P0_11 (
+ .IE(p0_z[11]),
+ .C(p0_i[11]),
+ .PE(p0_z[11]&p0_o[11]),
+ .DS(tielo),
+ .I(p0_o[11]),
+ .OEN(p0_z[11]),
+ .PAD(P0[11])
+ );
+
+PRDW0408SCDG uPAD_P0_12 (
+ .IE(p0_z[12]),
+ .C(p0_i[12]),
+ .PE(p0_z[12]&p0_o[12]),
+ .DS(tielo),
+ .I(p0_o[12]),
+ .OEN(p0_z[12]),
+ .PAD(P0[12])
+ );
+
+PRDW0408SCDG uPAD_P0_13 (
+ .IE(p0_z[13]),
+ .C(p0_i[13]),
+ .PE(p0_z[13]&p0_o[13]),
+ .DS(tielo),
+ .I(p0_o[13]),
+ .OEN(p0_z[13]),
+ .PAD(P0[13])
+ );
+
+PRDW0408SCDG uPAD_P0_14 (
+ .IE(p0_z[14]),
+ .C(p0_i[14]),
+ .PE(p0_z[14]&p0_o[14]),
+ .DS(tielo),
+ .I(p0_o[14]),
+ .OEN(p0_z[14]),
+ .PAD(P0[14])
+ );
+
+PRDW0408SCDG uPAD_P0_15 (
+ .IE(p0_z[15]),
+ .C(p0_i[15]),
+ .PE(p0_z[15]&p0_o[15]),
+ .DS(tielo),
+ .I(p0_o[15]),
+ .OEN(p0_z[15]),
+ .PAD(P0[15])
+ );
+
+// GPI.I Port 1 x 16
+
+PRDW0408SCDG uPAD_P1_00 (
+ .IE(p1_z[00]),
+ .C(p1_i[00]),
+ .PE(p1_z[00]&p1_o[00]),
+ .DS(tielo),
+ .I(p1_o[00]),
+ .OEN(p1_z[00]),
+ .PAD(P1[00])
+ );
+
+PRDW0408SCDG uPAD_P1_01 (
+ .IE(p1_z[01]),
+ .C(p1_i[01]),
+ .PE(p1_z[01]&p1_o[01]),
+ .DS(tielo),
+ .I(p1_o[01]),
+ .OEN(p1_z[01]),
+ .PAD(P1[01])
+ );
+
+PRDW0408SCDG uPAD_P1_02 (
+ .IE(p1_z[02]),
+ .C(p1_i[02]),
+ .PE(p1_z[02]&p1_o[02]),
+ .DS(tielo),
+ .I(p1_o[02]),
+ .OEN(p1_z[02]),
+ .PAD(P1[02])
+ );
+
+PRDW0408SCDG uPAD_P1_03 (
+ .IE(p1_z[03]),
+ .C(p1_i[03]),
+ .PE(p1_z[03]&p1_o[03]),
+ .DS(tielo),
+ .I(p1_o[03]),
+ .OEN(p1_z[03]),
+ .PAD(P1[03])
+ );
+
+PRDW0408SCDG uPAD_P1_04 (
+ .IE(p1_z[04]),
+ .C(p1_i[04]),
+ .PE(p1_z[04]&p1_o[04]),
+ .DS(tielo),
+ .I(p1_o[04]),
+ .OEN(p1_z[04]),
+ .PAD(P1[04])
+ );
+
+PRDW0408SCDG uPAD_P1_05 (
+ .IE(p1_z[05]),
+ .C(p1_i[05]),
+ .PE(p1_z[05]&p1_o[05]),
+ .DS(tielo),
+ .I(p1_o[05]),
+ .OEN(p1_z[05]),
+ .PAD(P1[05])
+ );
+
+PRDW0408SCDG uPAD_P1_06 (
+ .IE(p1_z[06]),
+ .C(p1_i[06]),
+ .PE(p1_z[06]&p1_o[06]),
+ .DS(tielo),
+ .I(p1_o[06]),
+ .OEN(p1_z[06]),
+ .PAD(P1[06])
+ );
+
+PRDW0408SCDG uPAD_P1_07 (
+ .IE(p1_z[07]),
+ .C(p1_i[07]),
+ .PE(p1_z[07]&p1_o[07]),
+ .DS(tielo),
+ .I(p1_o[07]),
+ .OEN(p1_z[07]),
+ .PAD(P1[07])
+ );
+
+PRDW0408SCDG uPAD_P1_08 (
+ .IE(p1_z[08]),
+ .C(p1_i[08]),
+ .PE(p1_z[08]&p1_o[08]),
+ .DS(tielo),
+ .I(p1_o[08]),
+ .OEN(p1_z[08]),
+ .PAD(P1[08])
+ );
+
+PRDW0408SCDG uPAD_P1_09 (
+ .IE(p1_z[09]),
+ .C(p1_i[09]),
+ .PE(p1_z[09]&p1_o[09]),
+ .DS(tielo),
+ .I(p1_o[09]),
+ .OEN(p1_z[09]),
+ .PAD(P1[09])
+ );
+
+PRDW0408SCDG uPAD_P1_10 (
+ .IE(p1_z[10]),
+ .C(p1_i[10]),
+ .PE(p1_z[10]&p1_o[10]),
+ .DS(tielo),
+ .I(p1_o[10]),
+ .OEN(p1_z[10]),
+ .PAD(P1[10])
+ );
+
+PRDW0408SCDG uPAD_P1_11 (
+ .IE(p1_z[11]),
+ .C(p1_i[11]),
+ .PE(p1_z[11]&p1_o[11]),
+ .DS(tielo),
+ .I(p1_o[11]),
+ .OEN(p1_z[11]),
+ .PAD(P1[11])
+ );
+
+PRDW0408SCDG uPAD_P1_12 (
+ .IE(p1_z[12]),
+ .C(p1_i[12]),
+ .PE(p1_z[12]&p1_o[12]),
+ .DS(tielo),
+ .I(p1_o[12]),
+ .OEN(p1_z[12]),
+ .PAD(P1[12])
+ );
+
+PRDW0408SCDG uPAD_P1_13 (
+ .IE(p1_z[13]),
+ .C(p1_i[13]),
+ .PE(p1_z[13]&p1_o[13]),
+ .DS(tielo),
+ .I(p1_o[13]),
+ .OEN(p1_z[13]),
+ .PAD(P1[13])
+ );
+
+PRDW0408SCDG uPAD_P1_14 (
+ .IE(p1_z[14]),
+ .C(p1_i[14]),
+ .PE(p1_z[14]&p1_o[14]),
+ .DS(tielo),
+ .I(p1_o[14]),
+ .OEN(p1_z[14]),
+ .PAD(P1[14])
+ );
+
+PRDW0408SCDG uPAD_P1_15 (
+ .IE(p1_z[15]),
+ .C(p1_i[15]),
+ .PE(p1_z[15]&p1_o[15]),
+ .DS(tielo),
+ .I(p1_o[15]),
+ .OEN(p1_z[15]),
+ .PAD(P1[15])
+ );
+
+endmodule
+
+
+
diff --git a/ASIC/rf_08k.spec b/ASIC/rf_08k.spec
new file mode 100644
index 0000000000000000000000000000000000000000..b42d0e44b9c36c27c4ff388c0be0b2289f7373e0
--- /dev/null
+++ b/ASIC/rf_08k.spec
@@ -0,0 +1,33 @@
+# user spec file, compiler rf_sp_hdf_hvt_rvt, version r0p0
+
+activity_factor = 20
+back_biasing = off
+bits = 32
+bmux = off
+bus_notation = on
+check_instname = on
+corners = ff_1p32v_1p32v_125c,ff_1p32v_1p32v_m40c,ss_1p08v_1p08v_125c,ss_1p08v_1p08v_m40c,tt_1p20v_1p20v_25c
+cust_comment =
+diodes = on
+drive = 6
+ema = on
+frequency = 250
+instname = rf_08k
+left_bus_delim = [
+libertyviewstyle = nldm
+libname = RF_LIB_08K
+mux = 8
+mvt =
+name_case = upper
+power_type = otc
+prefix =
+pwr_gnd_rename = vddpe:VDD,vddce:VDD,vsse:VSS
+retention = on
+right_bus_delim = ]
+ser = none
+site_def = off
+top_layer = m5-m10
+words = 2048
+wp_size = 1
+write_mask = on
+write_thru = off
diff --git a/ASIC/rf_sp_hdf.spec b/ASIC/rf_16k.spec
similarity index 90%
rename from ASIC/rf_sp_hdf.spec
rename to ASIC/rf_16k.spec
index 00b3c8d420d184817f99cec2e9e6655f31d75305..7e50754ebfc82df8ad9e2651813a14d3025f72d4 100644
--- a/ASIC/rf_sp_hdf.spec
+++ b/ASIC/rf_16k.spec
@@ -1,6 +1,6 @@
# user spec file, compiler rf_sp_hdf_hvt_rvt, version r0p0
-activity_factor = 50
+activity_factor = 20
back_biasing = off
bits = 32
bmux = off
@@ -12,10 +12,10 @@ diodes = on
drive = 6
ema = on
frequency = 250
-instname = rf_sp_hdf
+instname = rf_16k
left_bus_delim = [
libertyviewstyle = nldm
-libname = RF_LIB
+libname = RF_LIB_16K
mux = 8
mvt =
name_case = upper
diff --git a/flist/nanosoc.flist b/flist/nanosoc.flist
index c03f413750128622aa98d3a4bf44f7a6ca646899..28733147b0ec1df350a86b41d40c6c6a6156aa69 100644
--- a/flist/nanosoc.flist
+++ b/flist/nanosoc.flist
@@ -18,6 +18,9 @@
// ============= NanoSoC IP search path =============
+// NanoSoC Chip Pads Level
+$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v
+
// Include NanoSoC IP
-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_ip.flist
diff --git a/flist/nanosoc_ASIC.flist b/flist/nanosoc_ASIC.flist
index d4455e34a5a5b1ff7789711f0f76b6108e228c34..9699ae142b54720d1a2c0bf3e1f63aac175d06a4 100644
--- a/flist/nanosoc_ASIC.flist
+++ b/flist/nanosoc_ASIC.flist
@@ -17,6 +17,11 @@
// ============= NanoSoC IP search path =============
+// NanoSoC Chip Pads Level
+// $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_28pin.v
+$(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_40pin.v
+// $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_60pin.v
+
// Include NanoSoC IP
-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_ip.flist
diff --git a/flist/nanosoc_ip.flist b/flist/nanosoc_ip.flist
index ea78c8ca5db2f8d9f5fdb1dd21b83be9cddd1bd8..b62da6467aaaf3cbea2c301ccda37fa5fc10ff8a 100644
--- a/flist/nanosoc_ip.flist
+++ b/flist/nanosoc_ip.flist
@@ -17,9 +17,6 @@
// ============= NanoSoC IP search path =============
-// NanoSoC Chip Pads Level
-$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v
-
// NanoSoC Chip Level
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_chip/chip/verilog/nanosoc_chip.v
diff --git a/flows/makefile.asic b/flows/makefile.asic
index 96490605ceec4b1683efc3903e1698194e61603d..46aa340923ad1fcc42faa0c128a72b9b57c723b8 100644
--- a/flows/makefile.asic
+++ b/flows/makefile.asic
@@ -35,10 +35,12 @@ DC_OUTPUT_FILELIST := $(TCL_ASIC_FLIST_DIR)/dc_flist.tcl
# Location of outputs from synthesis
MEMORIES_DIR := $(SOCLABS_PROJECT_DIR)/memories
-RF_SPEC_FILE := $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/rf_sp_hdf.spec
+RF_16K_SPEC_FILE := $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/rf_16k.spec
+RF_08K_SPEC_FILE := $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/rf_08k.spec
ROM_SPEC_FILE := $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/rom_via.spec
BOOTROM_BIN_FILE := $(SOCLABS_PROJECT_DIR)/system/src/bootrom/bintxt/bootrom.bintxt
-RF_DIR := $(MEMORIES_DIR)/rf
+RF_16K_DIR := $(MEMORIES_DIR)/rf_16k
+RF_08K_DIR := $(MEMORIES_DIR)/rf_08k
ROM_DIR := $(MEMORIES_DIR)/bootrom
REPORTS_FOLDER := $(IMP_NANOSOC_ASIC_DIR)/reports
SYN_LOGS := $(IMP_NANOSOC_ASIC_DIR)/logs
@@ -72,11 +74,16 @@ flist_formality_nanosoc: gen_defs
gen_memories: bootrom
@mkdir -p $(MEMORIES_DIR)
- @mkdir -p $(RF_DIR)
+ @mkdir -p $(RF_16K_DIR)
+ @mkdir -p $(RF_08K_DIR)
@mkdir -p $(ROM_DIR)
echo "Generating register file memory libraries"
- cd $(RF_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rf_sp_hdf_hvt_rvt/r0p0/bin/rf_sp_hdf_hvt_rvt all -spec $(RF_SPEC_FILE);
- cd $(RF_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rf_sp_hdf_hvt_rvt/r0p0/bin/rf_sp_hdf_hvt_rvt liberty -spec $(RF_SPEC_FILE);
+ echo "16K RF"
+ cd $(RF_16K_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rf_sp_hdf_hvt_rvt/r0p0/bin/rf_sp_hdf_hvt_rvt all -spec $(RF_16K_SPEC_FILE);
+ cd $(RF_16K_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rf_sp_hdf_hvt_rvt/r0p0/bin/rf_sp_hdf_hvt_rvt liberty -spec $(RF_16K_SPEC_FILE);
+ echo "8K RF"
+ cd $(RF_08K_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rf_sp_hdf_hvt_rvt/r0p0/bin/rf_sp_hdf_hvt_rvt all -spec $(RF_08K_SPEC_FILE);
+ cd $(RF_08K_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rf_sp_hdf_hvt_rvt/r0p0/bin/rf_sp_hdf_hvt_rvt liberty -spec $(RF_08K_SPEC_FILE);
cd $(ROM_DIR)
echo "Generating ROM Libraries"
cd $(ROM_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rom_via_hdd_rvt_rvt/r0p0/bin/rom_via_hdd_rvt_rvt liberty -spec $(ROM_SPEC_FILE) -code_file $(BOOTROM_BIN_FILE);
diff --git a/nanosoc/nanosoc_regions/exp/verilog/nanosoc_region_exp.v b/nanosoc/nanosoc_regions/exp/verilog/nanosoc_region_exp.v
index 423ac87f4f508a55c6e84be45cff6a0d430dd1d8..36b27aad03a26368e836092378943541500bc0b1 100644
--- a/nanosoc/nanosoc_regions/exp/verilog/nanosoc_region_exp.v
+++ b/nanosoc/nanosoc_regions/exp/verilog/nanosoc_region_exp.v
@@ -32,6 +32,7 @@ module nanosoc_region_exp #(
output wire [SYS_DATA_W-1:0] HRDATA,
// DMAC Stream interfaces
`ifdef DMAC_DMA350
+`ifdef DMA350_STREAM_2
input wire EXP_STR_IN_0_TVALID,
output wire EXP_STR_IN_0_TREADY,
input wire [SYS_DATA_W-1:0] EXP_STR_IN_0_TDATA,
@@ -57,6 +58,7 @@ module nanosoc_region_exp #(
output wire [3:0] EXP_STR_OUT_1_TSTRB,
output wire EXP_STR_OUT_1_TLAST,
input wire EXP_STR_OUT_1_FLUSH,
+`endif
`endif
// Interrupt and DMAC Connections
@@ -85,6 +87,7 @@ module nanosoc_region_exp #(
.HRESP(HRESP),
.HRDATA(HRDATA),
`ifdef DMAC_DMA350
+`ifdef DMA350_STREAM_2
.EXP_STR_IN_0_TVALID(EXP_STR_IN_0_TVALID),
.EXP_STR_IN_0_TREADY(EXP_STR_IN_0_TREADY),
.EXP_STR_IN_0_TDATA(EXP_STR_IN_0_TDATA),
@@ -111,6 +114,8 @@ module nanosoc_region_exp #(
.EXP_STR_OUT_1_TLAST(EXP_STR_OUT_1_TLAST),
.EXP_STR_OUT_1_FLUSH(EXP_STR_OUT_1_FLUSH),
`endif
+`endif
+
.EXP_IRQ(EXP_IRQ),
.EXP_DRQ(EXP_DRQ),
.EXP_DLAST(EXP_DLAST)
diff --git a/nanosoc/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v b/nanosoc/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v
index 685c9d06161ddca89264b1349b1f5bc28a3dcc3a..e9b4b2770233bdc6742418dd3d397734fd9a24d5 100644
--- a/nanosoc/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v
+++ b/nanosoc/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v
@@ -77,7 +77,8 @@ module nanosoc_ss_dma #(
output wire DMAC_1_PREADY, // APB Ready
output wire DMAC_1_PSLVERR, // APB Slave Error
-`ifdef DMAC_DMA350
+`ifdef DMAC_DMA350
+`ifdef DMA350_STREAM_2
// DMAC Channel 0 AXI stream out
output wire DMAC_STR_OUT_0_TVALID,
input wire DMAC_STR_OUT_0_TREADY,
@@ -107,6 +108,7 @@ module nanosoc_ss_dma #(
input wire [4-1:0] DMAC_STR_IN_1_TSTRB,
input wire DMAC_STR_IN_1_TLAST,
output wire DMAC_STR_IN_1_FLUSH,
+`endif
`endif
// DMAC 1 DMA Request and Status Port
@@ -174,10 +176,7 @@ module nanosoc_ss_dma #(
.PREADY(DMAC_1_PREADY),
.PSLVERR(DMAC_1_PSLVERR),
// DMA Request and Status Port
- .DMA_REQ(DMAC_0_DMA_REQ),
- .DMA_DONE(DMAC_0_DMA_DONE),
- .DMA_ERR(DMAC_0_DMA_ERR),
-
+`ifdef DMA350_STREAM_2
.DMAC_STR_OUT_0_TVALID(DMAC_STR_OUT_0_TVALID),
.DMAC_STR_OUT_0_TREADY(DMAC_STR_OUT_0_TREADY),
.DMAC_STR_OUT_0_TDATA(DMAC_STR_OUT_0_TDATA),
@@ -199,7 +198,13 @@ module nanosoc_ss_dma #(
.DMAC_STR_IN_1_TDATA(DMAC_STR_IN_1_TDATA),
.DMAC_STR_IN_1_TSTRB(DMAC_STR_IN_1_TSTRB),
.DMAC_STR_IN_1_TLAST(DMAC_STR_IN_1_TLAST),
- .DMAC_STR_IN_1_FLUSH(DMAC_STR_IN_1_FLUSH)
+ .DMAC_STR_IN_1_FLUSH(DMAC_STR_IN_1_FLUSH),
+`endif
+
+ .DMA_REQ(DMAC_0_DMA_REQ),
+ .DMA_DONE(DMAC_0_DMA_DONE),
+ .DMA_ERR(DMAC_0_DMA_ERR)
+
);
diff --git a/nanosoc/nanosoc_subsystems/expansion/verilog/nanosoc_ss_expansion.v b/nanosoc/nanosoc_subsystems/expansion/verilog/nanosoc_ss_expansion.v
index 66ff10f47da3bceb488a3c71bd1ddf3545f8246d..8e30b0ff08071149afb2a57fe4968a8b62b10874 100644
--- a/nanosoc/nanosoc_subsystems/expansion/verilog/nanosoc_ss_expansion.v
+++ b/nanosoc/nanosoc_subsystems/expansion/verilog/nanosoc_ss_expansion.v
@@ -45,6 +45,7 @@ module nanosoc_ss_expansion #(
// DMAC Stream interfaces
`ifdef DMAC_DMA350
+`ifdef DMA350_STREAM_2
input wire EXP_STR_IN_0_TVALID,
output wire EXP_STR_IN_0_TREADY,
input wire [SYS_DATA_W-1:0] EXP_STR_IN_0_TDATA,
@@ -70,6 +71,7 @@ module nanosoc_ss_expansion #(
output wire [3:0] EXP_STR_OUT_1_TSTRB,
output wire EXP_STR_OUT_1_TLAST,
input wire EXP_STR_OUT_1_FLUSH,
+`endif
`endif
// SRAM Low Region AHB Port
@@ -132,6 +134,7 @@ module nanosoc_ss_expansion #(
.HRESP(EXP_HRESP),
.HRDATA(EXP_HRDATA),
`ifdef DMAC_DMA350
+`ifdef DMA350_STREAM_2
.EXP_STR_IN_0_TVALID(EXP_STR_IN_0_TVALID),
.EXP_STR_IN_0_TREADY(EXP_STR_IN_0_TREADY),
.EXP_STR_IN_0_TDATA(EXP_STR_IN_0_TDATA),
@@ -157,6 +160,7 @@ module nanosoc_ss_expansion #(
.EXP_STR_OUT_1_TSTRB(EXP_STR_OUT_1_TSTRB),
.EXP_STR_OUT_1_TLAST(EXP_STR_OUT_1_TLAST),
.EXP_STR_OUT_1_FLUSH(EXP_STR_OUT_1_FLUSH),
+`endif
`endif
// Interrupt and DMAC Connections
diff --git a/nanosoc/nanosoc_system/verilog/nanosoc_system.v b/nanosoc/nanosoc_system/verilog/nanosoc_system.v
index 488ec1cb5c50b5811660f496edcd5dd957c4b3b2..47a49c6ec25e764312cf5b4d733bf88fee037550 100644
--- a/nanosoc/nanosoc_system/verilog/nanosoc_system.v
+++ b/nanosoc/nanosoc_system/verilog/nanosoc_system.v
@@ -447,6 +447,7 @@ module nanosoc_system #(
assign DMAC_1_DMA_REQ = {DMAC_1_CHANNEL_NUM{1'b0}};
`ifdef DMAC_DMA350
+`ifdef DMA350_STREAM_2
// DMAC Channel 0 AXI stream out
wire DMAC_STR_OUT_0_TVALID;
wire DMAC_STR_OUT_0_TREADY;
@@ -473,6 +474,7 @@ module nanosoc_system #(
wire [4-1:0] DMAC_STR_IN_1_TSTRB;
wire DMAC_STR_IN_1_TLAST;
wire DMAC_STR_IN_1_FLUSH;
+`endif
`endif
// Instantiate Subsystem
@@ -547,6 +549,8 @@ module nanosoc_system #(
.DMAC_1_PSLVERR(DMAC_1_PSLVERR),
`ifdef DMAC_DMA350
+`ifdef DMA350_STREAM_2
+
.DMAC_STR_OUT_0_TVALID(DMAC_STR_OUT_0_TVALID),
.DMAC_STR_OUT_0_TREADY(DMAC_STR_OUT_0_TREADY),
.DMAC_STR_OUT_0_TDATA(DMAC_STR_OUT_0_TDATA),
@@ -572,6 +576,7 @@ module nanosoc_system #(
.DMAC_STR_IN_1_TSTRB(DMAC_STR_IN_1_TSTRB),
.DMAC_STR_IN_1_TLAST(DMAC_STR_IN_1_TLAST),
.DMAC_STR_IN_1_FLUSH(DMAC_STR_IN_1_FLUSH),
+`endif
`endif
// DMAC 1 DMA Request and Status Port
@@ -783,6 +788,7 @@ module nanosoc_system #(
.EXP_HRDATA(EXP_HRDATA),
`ifdef DMAC_DMA350
+`ifdef DMA350_STREAM_2
.EXP_STR_IN_0_TVALID(DMAC_STR_OUT_0_TVALID),
.EXP_STR_IN_0_TREADY(DMAC_STR_OUT_0_TREADY),
.EXP_STR_IN_0_TDATA(DMAC_STR_OUT_0_TDATA),
@@ -809,6 +815,8 @@ module nanosoc_system #(
.EXP_STR_OUT_1_TLAST(DMAC_STR_IN_1_TLAST),
.EXP_STR_OUT_1_FLUSH(DMAC_STR_IN_1_FLUSH),
`endif
+`endif
+
// SRAM Low Region AHB Port
.EXPRAM_L_HSEL(EXPRAM_L_HSEL),
diff --git a/nanosoc/sldma350_tech b/nanosoc/sldma350_tech
index d7b4b1b62b891668ca6554fe1806c45ff80ed76d..40601e44099d064d254b8ec53877682cc586b3ac 160000
--- a/nanosoc/sldma350_tech
+++ b/nanosoc/sldma350_tech
@@ -1 +1 @@
-Subproject commit d7b4b1b62b891668ca6554fe1806c45ff80ed76d
+Subproject commit 40601e44099d064d254b8ec53877682cc586b3ac