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nanosoc_ip.waive
nanosoc_ip.waive 1.43 KiB
//-----------------------------------------------------------------------------
// NanoSoC Lint Waivers
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : HAL Wavier file for NanoSoC Chip Pads
//-----------------------------------------------------------------------------
lint_checking designunit = nanosoc_chip_pads
{
// Combinatorial Wiring of outputs in top level of hierarchy
CBPAHI off;
// Input/Output PIns decalred as inout so may have multiple drivers
GLTASR off;
}
lint_checking designunit = nanosoc_chip
{
// Combinatorial Wiring of outputs in top level of hierarchy
CBPAHI off;
}
lint_checking designunit = bootrom
{
// Combinatorial wiring through multiple levels of hierarchy to bootrom (wrappers)
CBPAHI off;
}
lint_checking designunit = nanosoc_clkctrl
{
// Based Off of Arm IP
CBPAHI off;
}
lint_checking designunit = nanosoc_sysctrl
{
// Based off of Arm IP
CBPAHI off;
}
lint_checking designunit = nanosoc_sysio_apb_ss
{
// Based off of Arm IP
CBPAHI off;
}
lint_checking designunit = nanosoc_clkctrl
{
// Reset Bypass select
GLTASR off;
}