Initial project structure

.gitignore

+.socinit
+.metadata
+CheckResults.log
+CoherencyCheckConfiguration.config
\ No newline at end of file

.gitmodules

+[submodule "expansion_subsystem_tech"]
+	path = expansion_subsystem_tech
+	url = https://git.soton.ac.uk/soclabs/expansion_subsystem_tech.git
+[submodule "megasoc_tech"]
+	path = megasoc_tech
+	url = https://git.soton.ac.uk/soclabs/megasoc_tech.git

.slprojroot

+#-----------------------------------------------------------------------------
+# SoC Labs Project Root Marker
+# - This file tells environment setter that this is root of a SoC Labs Project
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# David Mapstone (d.a.mapstone@soton.ac.uk)
+#
+# Copyright  2023, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
\ No newline at end of file

env/dependency_env.sh

+#-----------------------------------------------------------------------------
+# SoC Labs Dependency Repository Environment Setup Script
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# David Mapstone (d.a.mapstone@soton.ac.uk)
+#
+# Copyright  2023, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+#!/bin/bash
+
+#-----------------------------------------------------------------------------
+# Technologies
+#-----------------------------------------------------------------------------
+
+# MilliSoC Tech
+export SOCLABS_MEGASOC_TECH_DIR="$SOCLABS_PROJECT_DIR/millisoc_tech"
+
+# MilliSoC Expansion Tech
+export SOCLABS_MEGASOC_EXP_TECH_DIR="$SOCLABS_PROJECT_DIR/expansion_subsystem_tech"
+
+#-----------------------------------------------------------------------------
+# Flows
+#-----------------------------------------------------------------------------
+
+# SoCTools - Toolkit of scripts related to SoCLabs projects
+export SOCLABS_SOCTOOLS_FLOW_DIR="$SOCLABS_PROJECT_DIR/soctools_flow"

expansion_subsystem_tech @ 9fae7319

+Subproject commit 9fae73198dcf7e9b44b4a62815821b1585ac9f18

megasoc_chip/chip/logical/millisoc_chip.v

+//-----------------------------------------------------------------------------
+// MegaSoC Chip
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// Daniel Newbrook (d.newbrook@soton.ac.uk)
+// 
+// Copyright � 2021-4, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+// Modules instantiated:
+//  megasoc_system
+
+module megasoc_chip(
+
+);
+
+
+
+endmodule
\ No newline at end of file

megasoc_chip/pads/cln28ht/logical/megasoc_chip_pads.v

+//-----------------------------------------------------------------------------
+// MegaSoC Chip Pads for TSMC 28nm node
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// Daniel Newbrook (d.newbrook@soton.ac.uk)
+// 
+// Copyright � 2021-4, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+// Modules instantiated:
+//  megasoc_chip
+
+module megasoc_chip_pads(
+
+);
+
+megasoc_chip u_megasoc_chip(
+
+);
+
+endmodule

megasoc_chip/pads/glib/logical/megasoc_chip_pads.v

+//-----------------------------------------------------------------------------
+// MegaSoC Chip Pads for Generic Libraries
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// Daniel Newbrook (d.newbrook@soton.ac.uk)
+// 
+// Copyright � 2021-4, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+// Modules instantiated:
+//  megasoc_chip
+
+module megasoc_chip_pads(
+
+);
+
+
+megasoc_chip u_megasoc_chip(
+
+);
+
+
+endmodule
\ No newline at end of file

megasoc_system/logical/megasoc_system.v

+//-----------------------------------------------------------------------------
+// MegaSoC System
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// Daniel Newbrook (d.newbrook@soton.ac.uk)
+// 
+// Copyright � 2021-4, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+// Modules instantiated:
+//  megasoc_tech_wrapper
+//  expansion_subsystem_wrapper
+
+module megasoc_system(
+
+);
+
+
+
+megasoc_tech_wrapper u_megasoc_tech_wrapper(
+
+);
+
+expansion_subsystem_wrapper u_megasoc_expansion_wrapper(
+
+);
+
+endmodule

megasoc_tech @ 3f666e24

+Subproject commit 3f666e24aae6e227d0d5f87ca718c9e01744df3f

projbranch

+#-----------------------------------------------------------------------------
+# SoC Labs Sub repository branch setup
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# David Mapstone (d.a.mapstone@soton.ac.uk)
+#
+# Copyright  2023, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+# Each Repo needs to have its branch set manually in here - they will defaultly be checked out to main
+# Project Repository Subrepository Branch Index
+# Add your Accelerator Repository here
+
+megasoc_tech: main
+expansion_subsystem_tech: main
+soctools_flow: main

set_env.sh

+#-----------------------------------------------------------------------------
+# SoC Labs Environment Setup Script
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# David Mapstone (d.a.mapstone@soton.ac.uk)
+#
+# Copyright  2023, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+#!/bin/bash
+
+# Source set_env script from soctools_flow
+source soctools_flow/bin/project_setup.sh $@
+

verif/testbench/logical/megasoc_project_tb.v

+//-----------------------------------------------------------------------------
+// MegaSoC Chip testbench
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// Daniel Newbrook (d.newbrook@soton.ac.uk)
+// 
+// Copyright � 2021-4, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+// Modules instantiated:
+//  megasoc_chip_pads
+`timescale 1ns/1ps
+
+module megasoc_chip_tb
+
+
+
+
+megasoc_chip_pads u_megasoc_chip_pads(
+
+)
+
+
+endmodule