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Commit 0ae37a6d authored by Daniel Newbrook's avatar Daniel Newbrook
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V1.4 update megasoc tech, add ADP and docs

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.gitignore
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......@@ -7,3 +7,8 @@ imp/
system/src/bootrom
system/src/defines
doc/tex/*.aux
doc/tex/*.log
doc/tex/*.out
doc/tex/*.toc
doc/megasoc_configuration_manual.pdf 0 → 100644
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doc/megasoc_datasheet.pdf 0 → 100644
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doc/tex/megasoc_configuration_manual.tex 0 → 100644
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\documentclass{report}
\usepackage{hyperref}
\usepackage{tcolorbox,float}
\usepackage{listings}
\makeatletter
\newfloat{info@box}{tbp}{loi}[section]% 1: Name of float environment. 2: Default placement (top, bottom, ...). 3: File extension if written to an aux-file (like toc, lof, lot, loa, ...). 4: Numbering within <section/subsection/...>.
\makeatother
\floatname{info@box}{Infobox}% Adapt caption.
\newenvironment{infobox}[1][]{% Create new environment using info@box and tcolorbox
\begin{info@box}%
\begin{tcolorbox}[colback=red!15!white,% background color
colframe=red!75!black,% frame color
title=Additional information\ifstrempty{#1}{}{: #1}.% title
]%
}{%
\end{tcolorbox}%
\end{info@box}%
}
\title{megaSoC Configuration Manual}
\author{\href{http://www.soclabs.org}{SoC Labs}}
\begin{document}
\maketitle
\input{preamble.tex}
\begin{infobox}
You must run 'source set\_env.sh' from the megasoc-project directory every time you open a new terminal!
\end{infobox} \par
\tableofcontents
\clearpage
\chapter{Introduction}
\end{document}
\ No newline at end of file
doc/tex/megasoc_datasheet.tex 0 → 100644
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\documentclass{report}
\usepackage{hyperref}
\title{megaSoC Datasheet}
\author{\href{http://www.soclabs.org}{SoC Labs}}
\begin{document}
\maketitle
\input{preamble.tex}
\tableofcontents
\clearpage
\chapter{Introduction}
\section{Summary}
\chapter{System}
\section{Bus Interconnect}
\section{Address Map}
\subsection{Summary}
\input{megasoc_sys_address_map.tex}
\subsection{Peripheral Region}
Below are the address regions for the System IO/Peripherals, detailed address maps for each peripheral are in chapter \ref{peripherals}
\begin{center}
\begin{tabular}{||c | c | c ||}
\hline
Region & Start Address & End Address \\
\hline\hline
UART 0 & 0x40000000 & 0x40000FFF \\
\hline
Timer 1 & 0x40001000 & 0x40001FFF \\
\hline
\end{tabular}
\end{center}
\section{}
\chapter{Peripherals} \label{peripherals}
\chapter{Recommended Testboard}
\end{document}
doc/tex/megasoc_sys_address_map.tex 0 → 100644
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\begin{center}
\begin{tabular}{||c | c | c ||}
\hline
Region & Start Address & End Address \\
\hline\hline
Boot-Rom & 0x00000000 & 0x0000FFFF \\
\hline
FLASH & 0x00400000 & 0x007FFFFF \\
\hline
SRAM & 0x00800000 & 0x0080FFFF \\
\hline
FLASH CTRL & 0x01000000 & 0x0100FFFF \\
\hline
DMA CTRL & 0x01010000 & 0x01011FFF \\
\hline
GIC & 0x01100000 & 0x01107FFF \\
\hline
PERIPHERAL & 0x40000000 & 0x5FFFFFFF \\
\hline
DEBUG & 0x60000000 & 0x7FFFFFFF \\
\hline
DRAM & 0x80000000 & 0xFFFFFFFF \\
\hline
\end{tabular}
\end{center}
doc/tex/preamble.tex 0 → 100644
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Preamble, copyrights licenses etc.
\ No newline at end of file
flist/project/megasoc_tb.flist
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......@@ -23,5 +23,9 @@ $(SOCLABS_PROJECT_DIR)/verif/trace/megasoc_uart_capture.v
$(SOCLABS_PROJECT_DIR)/verif/trace/megasoc_qspi_capture.v
$(SOCLABS_PROJECT_DIR)/verif/control/logical/megasoc_clkreset.v
$(SOCLABS_PROJECT_DIR)/verif/trace/megasoc_axi_stream_io_8_rxd_to_file.v
$(SOCLABS_PROJECT_DIR)/verif/trace/megasoc_ft1248x4_to_axi_streamio_v1_0.v
$(SOCLABS_PROJECT_DIR)/verif/trace/megasoc_ft1248x1_track.v
$(SOCLABS_PROJECT_DIR)/megasoc_tech/logical/socdebug_tech/socket/f232h_ft1248_stream/verilog/SYNCHRONIZER_EDGES.v
// $(SOCLABS_MEGASOC_TECH_DIR)/logical/MS_QSPI_XIP_CACHE/verify/vip/sst26wf080b.v
fpga/CICD/procs.tcl
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− 1
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......@@ -147,7 +147,15 @@ proc connect_zc702 {} {
}
proc connect_haps_sx {} {
open_hw_manager
connect_hw_server -allow_non_jtag
open_hw_target -xvc_url 10.22.13.34:2542
set_property PROBES.FILE {/home/dwn1c21/SoC-Labs/megasoc_project/imp/fpga/megasoc/tmp_edit_project.runs/impl_1/megasoc_design_wrapper.ltx} [get_hw_devices xcvu19p_0]
set_property FULL_PROBES.FILE {/home/dwn1c21/SoC-Labs/megasoc_project/imp/fpga/megasoc/tmp_edit_project.runs/impl_1/megasoc_design_wrapper.ltx} [get_hw_devices xcvu19p_0]
set_property PROGRAM.FILE {/home/dwn1c21/SoC-Labs/megasoc_project/imp/fpga/megasoc/tmp_edit_project.runs/impl_1/megasoc_design_wrapper.bit} [get_hw_devices xcvu19p_0]
program_hw_devices [get_hw_devices xcvu19p_0]
refresh_hw_device [lindex [get_hw_devices xcvu19p_0] 0]
reset_hw_axi [get_hw_axis]
}
......
fpga/targets/haps_sx/fpga_pinmap.xdc
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set_property PACKAGE_PIN BK44 [get_ports nRESET_0]
set_property PACKAGE_PIN BM44 [get_ports CLK_IN_P]
set_property PACKAGE_PIN BN44 [get_ports CLK_IN_N]
set_property PACKAGE_PIN AW16 [get_ports PMOD1_IO[0]]
set_property PACKAGE_PIN AW15 [get_ports PMOD1_IO[1]]
set_property PACKAGE_PIN AY14 [get_ports PMOD1_IO[2]]
set_property PACKAGE_PIN AY13 [get_ports PMOD1_IO[3]]
set_property PACKAGE_PIN AV16 [get_ports PMOD1_IO[4]]
set_property PACKAGE_PIN AV15 [get_ports PMOD1_IO[5]]
set_property PACKAGE_PIN AU17 [get_ports PMOD1_IO[6]]
set_property PACKAGE_PIN AU16 [get_ports PMOD1_IO[7]]
set_property IOSTANDARD DIFF_SSTL12 [get_ports CLK_IN_P]
set_property IOSTANDARD DIFF_SSTL12 [get_ports CLK_IN_N]
......
fpga/targets/haps_sx/fpga_timing.xdc
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create_clock -name CLK_IN_P -period 10 [get_ports CLK_IN_P]
create_clock -name EXT_CLK -period 10 [get_ports CLK_IN_P]
fpga/targets/haps_sx/megasoc_design_wrapper.v
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......@@ -10,33 +10,18 @@
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module megasoc_design_wrapper
(CLK_IN_P,
CLK_IN_N,
//QSPI_IO_e_0,
//QSPI_IO_i_0,
//QSPI_IO_o_0,
//QSPI_SCLK_0,
//QSPI_nCS_0,
nRESET_0);
input CLK_IN_P;
input CLK_IN_N;
//output [3:0]QSPI_IO_e_0;
//input [3:0]QSPI_IO_i_0;
//output [3:0]QSPI_IO_o_0;
//output QSPI_SCLK_0;
//output QSPI_nCS_0;
input nRESET_0;
module megasoc_design_wrapper(
input wire CLK_IN_P,
input wire CLK_IN_N,
input wire nRESET_0,
inout wire [7:0] PMOD1_IO
);
wire CLK_IN_P;
wire CLK_IN_N;
wire [3:0]QSPI_IO_e_0;
wire [3:0]QSPI_IO_i_0;
wire [3:0]QSPI_IO_o_0;
wire QSPI_SCLK_0;
wire QSPI_nCS_0;
wire nRESET_0;
megasoc_design megasoc_design_i
(.CLK_P(CLK_IN_P),
......
makefile
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......@@ -131,5 +131,12 @@ get_flash_model:
first_time_setup: make_project build_ip get_flash_model
docs:
pdflatex --output-directory=./doc/tex/ ./doc/tex/megasoc_datasheet.tex
pdflatex --output-directory=./doc/tex/ ./doc/tex/megasoc_datasheet.tex
pdflatex --output-directory=./doc/tex/ ./doc/tex/megasoc_configuration_manual.tex
pdflatex --output-directory=./doc/tex/ ./doc/tex/megasoc_configuration_manual.tex
mv ./doc/tex/megasoc_datasheet.pdf ./doc/megasoc_datasheet.pdf
mv ./doc/tex/megasoc_configuration_manual.pdf ./doc/megasoc_configuration_manual.pdf
clean: clean_sim clean_all_code
\ No newline at end of file
megasoc_chip/chip/logical/megasoc_chip.v
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......@@ -12,7 +12,8 @@
// megasoc_system
module megasoc_chip(
input wire CLK_IN,
input wire CLK_IN, // Main system clock input
input wire RT_CLK, // 32kHz real time clock
input wire nRESET,
// QSPI signals
......@@ -27,6 +28,16 @@ module megasoc_chip(
output wire UARTTXD,
output wire UARTTXEN,
// FT1248 Signals
output wire FT_CLK_O, // SCLK
output wire FT_SSN_O, // SS_N
input wire FT_MISO_I, // MISO
output wire FT_MIOSIO_O, // MIOSIO tristate output when enabled
output wire FT_MIOSIO_E, // MIOSIO tristate output enable (active hi)
output wire FT_MIOSIO_Z, // MIOSIO tristate output enable (active lo)
input wire FT_MIOSIO_I, // MIOSIO tristate input
// DAP-lite Signals
input wire nTRST,
input wire SWCLKTCK,
......@@ -41,15 +52,27 @@ module megasoc_chip(
megasoc_system u_megasoc_system(
.CLK_IN(CLK_IN),
.RT_CLK(RT_CLK),
.nRESET(nRESET),
.QSPI_SCLK(QSPI_SCLK),
.QSPI_nCS(QSPI_nCS),
.QSPI_IO_o(QSPI_IO_o),
.QSPI_IO_i(QSPI_IO_i),
.QSPI_IO_e(QSPI_IO_e),
.UARTRXD(UARTRXD),
.UARTTXD(UARTTXD),
.UARTTXEN(UARTTXEN),
.FT_CLK_O(FT_CLK_O),
.FT_SSN_O(FT_SSN_O),
.FT_MISO_I(FT_MISO_I),
.FT_MIOSIO_O(FT_MIOSIO_O),
.FT_MIOSIO_E(FT_MIOSIO_E),
.FT_MIOSIO_Z(FT_MIOSIO_Z),
.FT_MIOSIO_I(FT_MIOSIO_I),
.nTRST(nTRST),
.SWCLKTCK(SWCLKTCK),
.SWDITMS(SWDITMS),
......
megasoc_chip/pads/glib/logical/megasoc_chip_pads.v
+ 32
− 1
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......@@ -22,6 +22,8 @@ module megasoc_chip_pads(
// Clocks and Reset
input wire REF_CLK_XTAL1,
output wire REF_CLK_XTAL2,
input wire RT_CLK_XTAL1,
output wire RT_CLK_XTAL2,
input wire PORESTn,
input wire nSRST,
......@@ -45,7 +47,13 @@ module megasoc_chip_pads(
// QSPI Interface
output wire QSPI_SCLK,
inout wire [3:0] QSPI_IO,
output wire QSPI_nCS
output wire QSPI_nCS,
// FT1248
output wire FT_CLK, // SCLK
output wire FT_SSN, // SS_N
input wire FT_MISO, // MISO
inout wire FT_MIOSIO // MIOSIO
// Ethernet
......@@ -56,6 +64,7 @@ module megasoc_chip_pads(
);
// QSPI
wire [3:0] QSPI_IO_o;
wire [3:0] QSPI_IO_i;
wire [3:0] QSPI_IO_e;
......@@ -70,19 +79,41 @@ assign QSPI_IO_i[1] = QSPI_IO[1];
assign QSPI_IO_i[2] = QSPI_IO[2];
assign QSPI_IO_i[3] = QSPI_IO[3];
// FT1248
wire FT_MIOSIO_O;
wire FT_MIOSIO_E;
wire FT_MIOSIO_Z;
wire FT_MIOSIO_I;
assign FT_MIOSIO = FT_MIOSIO_E ? FT_MIOSIO_O : 1'bz;
assign FT_MIOSIO_I = FT_MIOSIO;
assign REF_CLK_XTAL2 = REF_CLK_XTAL1;
assign RT_CLK_XTAL2 = RT_CLK_XTAL1;
megasoc_chip u_megasoc_chip(
.CLK_IN(REF_CLK_XTAL1),
.RT_CLK(RT_CLK_XTAL1),
.nRESET(PORESTn),
.QSPI_SCLK(QSPI_SCLK),
.QSPI_nCS(QSPI_nCS),
.QSPI_IO_o(QSPI_IO_o),
.QSPI_IO_i(QSPI_IO_i),
.QSPI_IO_e(QSPI_IO_e),
.UARTRXD(),
.UARTTXD(),
.UARTTXEN(),
.FT_CLK_O(FT_CLK),
.FT_SSN_O(FT_SSN),
.FT_MISO_I(FT_MISO),
.FT_MIOSIO_O(FT_MIOSIO_O),
.FT_MIOSIO_E(FT_MIOSIO_E),
.FT_MIOSIO_Z(FT_MIOSIO_Z),
.FT_MIOSIO_I(FT_MIOSIO_I),
.nTRST(),
.SWCLKTCK(),
.SWDITMS(),
......
megasoc_system/logical/megasoc_system.v
+ 202
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......@@ -15,6 +15,7 @@
`include "gen_defines.v"
module megasoc_system(
input wire CLK_IN,
input wire RT_CLK, // 32kHz real time clock
input wire nRESET,
// QSPI Signals
......@@ -29,6 +30,15 @@ module megasoc_system(
output wire UARTTXD,
output wire UARTTXEN,
// FT1248 Signals
output wire FT_CLK_O, // SCLK
output wire FT_SSN_O, // SS_N
input wire FT_MISO_I, // MISO
output wire FT_MIOSIO_O, // MIOSIO tristate output when enabled
output wire FT_MIOSIO_E, // MIOSIO tristate output enable (active hi)
output wire FT_MIOSIO_Z, // MIOSIO tristate output enable (active lo)
input wire FT_MIOSIO_I, // MIOSIO tristate input
// DAP-LITE external signals
input wire nTRST,
input wire SWCLKTCK,
......@@ -42,6 +52,64 @@ module megasoc_system(
);
// DMA 350 APB Interface Wires
wire [31:0] PADDR_DMA_CTRL;
wire [31:0] PWDATA_DMA_CTRL;
wire PWRITE_DMA_CTRL;
wire [2:0] PPROT_DMA_CTRL;
wire [3:0] PSTRB_DMA_CTRL;
wire PENABLE_DMA_CTRL;
wire PSELx_DMA_CTRL;
wire [31:0] PRDATA_DMA_CTRL;
wire PSLVERR_DMA_CTRL;
wire PREADY_DMA_CTRL;
// DMA 350 AXI Interface Wires
wire [1:0] AWID_DMA350;
wire [43:0] AWADDR_DMA350;
wire [7:0] AWLEN_DMA350;
wire [2:0] AWSIZE_DMA350;
wire [1:0] AWBURST_DMA350;
wire AWLOCK_DMA350;
wire [3:0] AWCACHE_DMA350;
wire [2:0] AWPROT_DMA350;
wire AWVALID_DMA350;
wire AWREADY_DMA350;
wire [127:0] WDATA_DMA350;
wire [15:0] WSTRB_DMA350;
wire WLAST_DMA350;
wire WVALID_DMA350;
wire WREADY_DMA350;
wire [1:0] BID_DMA350;
wire [1:0] BRESP_DMA350;
wire BVALID_DMA350;
wire BREADY_DMA350;
wire [1:0] ARID_DMA350;
wire [43:0] ARADDR_DMA350;
wire [7:0] ARLEN_DMA350;
wire [2:0] ARSIZE_DMA350;
wire [1:0] ARBURST_DMA350;
wire ARLOCK_DMA350;
wire [3:0] ARCACHE_DMA350;
wire [2:0] ARPROT_DMA350;
wire ARVALID_DMA350;
wire ARREADY_DMA350;
wire [1:0] RID_DMA350;
wire [127:0] RDATA_DMA350;
wire [1:0] RRESP_DMA350;
wire RLAST_DMA350;
wire RVALID_DMA350;
wire RREADY_DMA350;
wire [3:0] DMA350_irq_channel;
wire DMA350_irq_comb_nonsec;
wire [1:0] AXI_SYS_EXP_awid;
wire [31:0] AXI_SYS_EXP_awaddr;
wire [7:0] AXI_SYS_EXP_awlen;
......@@ -117,6 +185,7 @@ wire AXI_EXP_SYS_rready;
megasoc_tech_wrapper u_megasoc_tech_wrapper(
.SYS_CLK(CLK_IN),
.SYS_CLKEN(1'b1),
.RT_CLK(RT_CLK),
.SYS_RESETn(nRESET),
// Millisoc system AXI Manager
......@@ -193,6 +262,58 @@ megasoc_tech_wrapper u_megasoc_tech_wrapper(
.AXI_EXP_SYS_rlast(AXI_EXP_SYS_rlast),
.AXI_EXP_SYS_rvalid(AXI_EXP_SYS_rvalid),
.AXI_EXP_SYS_rready(AXI_EXP_SYS_rready),
.PADDR_DMA_CTRL(PADDR_DMA_CTRL),
.PWDATA_DMA_CTRL(PWDATA_DMA_CTRL),
.PWRITE_DMA_CTRL(PWRITE_DMA_CTRL),
.PPROT_DMA_CTRL(PPROT_DMA_CTRL),
.PSTRB_DMA_CTRL(PSTRB_DMA_CTRL),
.PENABLE_DMA_CTRL(PENABLE_DMA_CTRL),
.PSELx_DMA_CTRL(PSELx_DMA_CTRL),
.PRDATA_DMA_CTRL(PRDATA_DMA_CTRL),
.PSLVERR_DMA_CTRL(PSLVERR_DMA_CTRL),
.PREADY_DMA_CTRL(PREADY_DMA_CTRL),
.AWID_DMA350(AWID_DMA350),
.AWADDR_DMA350(AWADDR_DMA350),
.AWLEN_DMA350(AWLEN_DMA350),
.AWSIZE_DMA350(AWSIZE_DMA350),
.AWBURST_DMA350(AWBURST_DMA350),
.AWLOCK_DMA350(AWLOCK_DMA350),
.AWCACHE_DMA350(AWCACHE_DMA350),
.AWPROT_DMA350(AWPROT_DMA350),
.AWVALID_DMA350(AWVALID_DMA350),
.AWREADY_DMA350(AWREADY_DMA350),
.WDATA_DMA350(WDATA_DMA350),
.WSTRB_DMA350(WSTRB_DMA350),
.WLAST_DMA350(WLAST_DMA350),
.WVALID_DMA350(WVALID_DMA350),
.WREADY_DMA350(WREADY_DMA350),
.BID_DMA350(BID_DMA350),
.BRESP_DMA350(BRESP_DMA350),
.BVALID_DMA350(BVALID_DMA350),
.BREADY_DMA350(BREADY_DMA350),
.ARID_DMA350(ARID_DMA350),
.ARADDR_DMA350(ARADDR_DMA350),
.ARLEN_DMA350(ARLEN_DMA350),
.ARSIZE_DMA350(ARSIZE_DMA350),
.ARBURST_DMA350(ARBURST_DMA350),
.ARLOCK_DMA350(ARLOCK_DMA350),
.ARCACHE_DMA350(ARCACHE_DMA350),
.ARPROT_DMA350(ARPROT_DMA350),
.ARVALID_DMA350(ARVALID_DMA350),
.ARREADY_DMA350(ARREADY_DMA350),
.RID_DMA350(RID_DMA350),
.RDATA_DMA350(RDATA_DMA350),
.RRESP_DMA350(RRESP_DMA350),
.RLAST_DMA350(RLAST_DMA350),
.RVALID_DMA350(RVALID_DMA350),
.RREADY_DMA350(RREADY_DMA350),
.DMA350_irq_channel(DMA350_irq_channel),
.DMA350_irq_comb_nonsec(DMA350_irq_comb_nonsec),
.QSPI_SCLK(QSPI_SCLK),
.QSPI_nCS(QSPI_nCS),
.QSPI_IO_o(QSPI_IO_o),
......@@ -201,6 +322,15 @@ megasoc_tech_wrapper u_megasoc_tech_wrapper(
.UARTRXD(UARTRXD),
.UARTTXD(UARTTXD),
.UARTTXEN(UARTTXEN),
.FT_CLK_O(FT_CLK_O),
.FT_SSN_O(FT_SSN_O),
.FT_MISO_I(FT_MISO_I),
.FT_MIOSIO_O(FT_MIOSIO_O),
.FT_MIOSIO_E(FT_MIOSIO_E),
.FT_MIOSIO_Z(FT_MIOSIO_Z),
.FT_MIOSIO_I(FT_MIOSIO_I),
.nTRST(nTRST),
.SWCLKTCK(SWCLKTCK),
.SWDITMS(SWDITMS),
......@@ -211,6 +341,76 @@ megasoc_tech_wrapper u_megasoc_tech_wrapper(
.SWDOEN(SWDOEN)
);
megasoc_tech_system_wrapper u_megasoc_tech_system_wrapper(
.CLK(CLK_IN),
.RESETn(nRESET),
.DMA350_PWAKEUP(1'b1),
.DMA350_PDEBUG(1'b0),
.DMA350_PSEL(PSELx_DMA_CTRL),
.DMA350_PENABLE(PENABLE_DMA_CTRL),
.DMA350_PPROT(PPROT_DMA_CTRL),
.DMA350_PWRITE(PWRITE_DMA_CTRL),
.DMA350_PADDR(PADDR_DMA_CTRL),
.DMA350_PWDATA(PWDATA_DMA_CTRL),
.DMA350_PSTRB(PSTRB_DMA_CTRL),
.DMA350_PREADY(PREADY_DMA_CTRL),
.DMA350_PSLVERR(PSLVERR_DMA_CTRL),
.DMA350_PRDATA(PRDATA_DMA_CTRL),
.DMA350_AWAKEUP_M0(),
.DMA350_AWVALID_M0(AWVALID_DMA350),
.DMA350_AWADDR_M0(AWADDR_DMA350),
.DMA350_AWBURST_M0(AWBURST_DMA350),
.DMA350_AWID_M0(AWID_DMA350),
.DMA350_AWLEN_M0(AWLEN_DMA350),
.DMA350_AWSIZE_M0(AWSIZE_DMA350),
.DMA350_AWQOS_M0(),
.DMA350_AWPROT_M0(AWPROT_DMA350),
.DMA350_AWREADY_M0(AWREADY_DMA350),
.DMA350_AWCACHE_M0(AWCACHE_DMA350),
.DMA350_AWINNER_M0(),
.DMA350_AWDOMAIN_M0(),
.DMA350_ARVALID_M0(ARVALID_DMA350),
.DMA350_ARADDR_M0(ARADDR_DMA350),
.DMA350_ARBURST_M0(ARBURST_DMA350),
.DMA350_ARID_M0(ARID_DMA350),
.DMA350_ARLEN_M0(ARLEN_DMA350),
.DMA350_ARSIZE_M0(ARSIZE_DMA350),
.DMA350_ARQOS_M0(),
.DMA350_ARPROT_M0(ARPROT_DMA350),
.DMA350_ARREADY_M0(ARREADY_DMA350),
.DMA350_ARCACHE_M0(ARCACHE_DMA350),
.DMA350_ARINNER_M0(),
.DMA350_ARDOMAIN_M0(),
.DMA350_ARCMDLINK_M0(),
.DMA350_WVALID_M0(WVALID_DMA350),
.DMA350_WLAST_M0(WLAST_DMA350),
.DMA350_WSTRB_M0(WSTRB_DMA350),
.DMA350_WDATA_M0(WDATA_DMA350),
.DMA350_WREADY_M0(WREADY_DMA350),
.DMA350_RVALID_M0(RVALID_DMA350),
.DMA350_RID_M0(RID_DMA350),
.DMA350_RLAST_M0(RLAST_DMA350),
.DMA350_RDATA_M0(RDATA_DMA350),
.DMA350_RPOISON_M0(2'b00),
.DMA350_RRESP_M0(RRESP_DMA350),
.DMA350_RREADY_M0(RREADY_DMA350),
.DMA350_BVALID_M0(BVALID_DMA350),
.DMA350_BID_M0(BID_DMA350),
.DMA350_BRESP_M0(BRESP_DMA350),
.DMA350_BREADY_M0(BREADY_DMA350),
.DMA350_irq_channel(DMA350_irq_channel),
.DMA350_irq_comb_nonsec(DMA350_irq_comb_nonsec)
);
`ifdef INC_EXP
expansion_subsystem_wrapper u_megasoc_expansion_wrapper(
.sys_clk(),
......
megasoc_tech @ 43c6ae6a
Compare 13691c8c...43c6ae6a
Subproject commit 13691c8c10cb58199dc78da621b29d58b8b732de
Subproject commit 43c6ae6ac778989b0ea09101aea347d7c460729a
verif/control/logical/megasoc_clkreset.v
+ 10
− 1
View file @ 0ae37a6d
......@@ -38,6 +38,7 @@
module megasoc_clkreset(
output wire CLK,
output wire CLK_RT,
output wire NRST,
output wire NRST_early,
output wire NRST_late,
......@@ -45,20 +46,28 @@ module megasoc_clkreset(
);
reg clock_q;
reg clock_rt;
reg [15:0] shifter;
initial
begin
clock_q <= 1'b0;
clock_rt <= 1'b0;
shifter <= 16'h0000;
#40 clock_q <= 1'b1;
clock_rt <= 1'b1;
end
always @(clock_q)
#5 clock_q <= !clock_q; // 10ns period, 100MHz
always @(clock_rt)
#15259 clock_rt <= !clock_rt; // nearly 32.678 KHz
assign CLK = clock_q;
assign CLK_RT = clock_rt;
always @(posedge clock_q)
if (! (&shifter)) // until full...
......
verif/testbench/logical/megasoc_tb.sv
+ 86
− 2
View file @ 0ae37a6d
......@@ -17,15 +17,29 @@ module megasoc_tb();
`define CORTEXA53_UNIVENT_DPI_CAPTURE
`define CORTEXA53_UNIVENT
wire EXT_CLK;
wire EXT_CLK; // 100 MHz crystal clock
wire RT_CLK; // 32.768 kHz crystal clock
wire nRESET;
wire QSPI_SCLK;
wire [3:0] QSPI_IO;
wire QSPI_nCS;
wire FT_CLK;
wire FT_SSN;
wire FT_MISO;
wire FT_MIOSIO;
wire ft_miosio_i;
wire ft_miosio_o;
wire ft_miosio_z;
assign ft_miosio_i = FT_MIOSIO;
bufif1 #1 (FT_MIOSIO, ft_miosio_o, !ft_miosio_z);
megasoc_clkreset u_megasoc_clkreset(
.CLK(EXT_CLK),
.CLK_RT(RT_CLK),
.NRST(nRESET)
);
......@@ -43,6 +57,8 @@ end
megasoc_chip_pads u_megasoc_chip_pads(
.REF_CLK_XTAL1(EXT_CLK),
.REF_CLK_XTAL2(),
.RT_CLK_XTAL1(RT_CLK),
.RT_CLK_XTAL2(),
.PORESTn(nRESET),
.nSRST(nRESET),
.GPIO_P0(),
......@@ -60,7 +76,11 @@ megasoc_chip_pads u_megasoc_chip_pads(
.DBGACK(),
.QSPI_SCLK(QSPI_SCLK),
.QSPI_IO(QSPI_IO),
.QSPI_nCS(QSPI_nCS)
.QSPI_nCS(QSPI_nCS),
.FT_CLK(FT_CLK),
.FT_SSN(FT_SSN),
.FT_MISO(FT_MISO),
.FT_MIOSIO(FT_MIOSIO)
);
sst26vf064b FLASH(
......@@ -138,4 +158,68 @@ megasoc_qspi_capture #(
.HRESP_o(`MEGASOC_QSPI_SUBSYSTEM.HRESP)
);
wire rxd8_tvalid;
wire rxd8_tready;
wire[7:0] rxd8_tdata;
megasoc_ft1248x1_to_axi_streamio_v1_0 u_ft1248_to_axi_stream(
.ft_clk_i(FT_CLK),
.ft_ssn_i(FT_SSN),
.ft_miso_o(FT_MISO),
.ft_miosio_i(ft_miosio_i),
.ft_miosio_o(ft_miosio_o),
.ft_miosio_z(ft_miosio_z),
.aclk(EXT_CLK),
.aresetn(nRESET),
.txd_tvalid_o(rxd8_tvalid),
.txd_tdata8_o(rxd8_tdata),
.txd_tready_i(rxd8_tready),
.rxd_tready_o(),
.rxd_tdata8_i(8'h00),
.rxd_tvalid_i(1'b0)
);
megasoc_axi_stream_io_8_rxd_to_file#(
.RXDFILENAME("logs/ft1248_out.log")
) u_megasoc_axi_stream_io_8_rxd_to_file (
.aclk (EXT_CLK),
.aresetn (nRESET),
.eof_received ( ),
.rxd8_ready (rxd8_tready),
.rxd8_valid (rxd8_tvalid),
.rxd8_data (rxd8_tdata)
);
wire ft_clk2uart;
wire ft_rxd2uart;
wire ft_txd2uart;
megasoc_ft1248x1_track
u_megasoc_ft1248x1_track
(
.ft_clk_i (FT_CLK),
.ft_ssn_i (FT_SSN),
.ft_miso_i (FT_MISO),
.ft_miosio_i (ft_miosio_i),
.aclk (EXT_CLK),
.aresetn (nRESET),
.FTDI_CLK2UART_o (ft_clk2uart), // Clock (baud rate)
.FTDI_OP2UART_o (ft_rxd2uart), // Received data to UART capture
.FTDI_IP2UART_o (ft_txd2uart) // Transmitted data to UART capture
);
megasoc_uart_capture #(.LOGFILENAME("logs/ft1248_op.log"), .VERBOSE(1))
u_megasoc_uart_capture1(
.RESETn (nRESET),
.CLK (ft_clk2uart),
.RXD (ft_rxd2uart),
.DEBUG_TESTER_ENABLE ( ), //debug_test_en2), //driven by u_nanosoc_track_tb_iostream
.SIMULATIONEND (), // This signal set to 1 at the end of simulation.
.AUXCTRL ()
);
endmodule
verif/trace/megasoc_axi_stream_io_8_rxd_to_file.v 0 → 100644
+ 81
− 0
View file @ 0ae37a6d
//-----------------------------------------------------------------------------
// customised example Cortex-M0 controller UART with file logging
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Copyright (C) 2023, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : FT1248 1-bit data off-chip interface (emulate FT232H device)
// and allows cmsdk_uart_capture testbench models to log ADP ip, op streams
//-----------------------------------------------------------------------------
module megasoc_axi_stream_io_8_rxd_to_file
#(parameter RXDFILENAME = "rxd.log",
parameter VERBOSE = 0)
(
input wire aclk,
input wire aresetn,
output wire eof_received,
output wire rxd8_ready,
input wire rxd8_valid,
input wire [7:0] rxd8_data
);
//----------------------------------------------
//-- File I/O
//----------------------------------------------
integer fd; // channel descriptor for cmd file input
integer ch;
`define EOF -1
reg ready;
reg [7:0] data8;
reg nxt_end_simulation;
reg reg_end_simulation;
assign eof_received = nxt_end_simulation;
initial
begin
ready <= 0;
nxt_end_simulation <= 1'b0;
reg_end_simulation <= 1'b0;
fd= $fopen(RXDFILENAME,"w");
if (fd == 0)
$write("** %m : output log file failed to open **\n");
else begin
@(posedge aresetn);
while (!nxt_end_simulation) begin
@(posedge aclk);
ready <= 1'b1;
@(posedge aclk);
while (rxd8_valid == 1'b0)
@(posedge aclk);
ready <=0;
data8 <= rxd8_data;
ch = (rxd8_data & 8'hff);
if (ch==8'h04) // Stop simulation if 0x04 is received
nxt_end_simulation <= 1'b1;
else begin
$fwrite(fd, "%c", ch);
if (VERBOSE) $write("%c", ch);
end
end
$write("** %m : log file closed after stream RX terminated **\n");
$fclose(fd);
ready <= 0;
end
end
assign rxd8_ready = ready ;
endmodule
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