SOC1-167: Added FPGA library files to fpga lib repo

pads/verilog/PAD_INOUT8MA_NOE.v

+// from GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright  2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module PAD_INOUT8MA_NOE (
+   // Inouts
+   PAD, 
+   // Outputs
+   I, 
+   // Inputs
+   O,
+   NOE
+   );
+   inout PAD;
+   output I;
+   input O;
+   input NOE;
+
+  IOBUF #(
+    .IOSTANDARD ("LVCMOS33"),
+    .DRIVE(8)
+  ) IOBUF3V3 (
+    .O(I),
+    .IO(PAD),
+    .I(O),
+    .T(NOE)
+  );
+    
+endmodule // PAD_INOUT8MA_NOE

pads/verilog/PAD_VDDIO.v

+// from GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright  2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module PAD_VDDIO (
+   // Inouts
+   PAD
+   );
+   inout PAD;
+
+  IOBUF #(
+    .IOSTANDARD ("LVCMOS33"),
+    .DRIVE(8)
+  ) IOBUF3V3 (
+    .O( ),
+    .IO(PAD),
+    .I(1'b1),
+    .T(1'b1)
+  );
+   
+endmodule // PAD_VDDIO

pads/verilog/PAD_VDDSOC.v

+// from GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright  2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module PAD_VDDSOC (
+   // Inouts
+   PAD
+   );
+   inout PAD;
+
+  IOBUF #(
+    .IOSTANDARD ("LVCMOS33"),
+    .DRIVE(8)
+  ) IOBUF3V3 (
+    .O( ),
+    .IO(PAD),
+    .I(1'b1),
+    .T(1'b1)
+  );
+    
+endmodule // PAD_VDDSOC

pads/verilog/PAD_VSS.v

+// from GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright  2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module PAD_VSS (
+   // Inouts
+   PAD
+   );
+   inout PAD;
+
+  IOBUF #(
+    .IOSTANDARD ("LVCMOS33"),
+    .DRIVE(8)
+  ) IOBUF3V3 (
+    .O( ),
+    .IO(PAD),
+    .I(1'b1),
+    .T(1'b1)
+  );
+    
+endmodule // PAD_VSS

pads/verilog/PAD_VSSIO.v

+// from GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright  2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module PAD_VSSIO (
+   // Inouts
+   PAD
+   );
+   inout PAD;
+
+  IOBUF #(
+    .IOSTANDARD ("LVCMOS33"),
+    .DRIVE(8)
+  ) IOBUF3V3 (
+    .O( ),
+    .IO(PAD),
+    .I(1'b1),
+    .T(1'b1)
+  );
+    
+endmodule // PAD_VSSIO