From c51fa197a1d89ed556653fd7743c4aba20383b39 Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Thu, 27 Apr 2023 13:45:27 +0100
Subject: [PATCH] SOC1-167: Added FPGA library files to fpga lib repo
---
pads/verilog/PAD_INOUT8MA_NOE.v | 37 +++++++++++++++++++++++++++++++++
pads/verilog/PAD_VDDIO.v | 29 ++++++++++++++++++++++++++
pads/verilog/PAD_VDDSOC.v | 29 ++++++++++++++++++++++++++
pads/verilog/PAD_VSS.v | 29 ++++++++++++++++++++++++++
pads/verilog/PAD_VSSIO.v | 29 ++++++++++++++++++++++++++
5 files changed, 153 insertions(+)
create mode 100644 pads/verilog/PAD_INOUT8MA_NOE.v
create mode 100644 pads/verilog/PAD_VDDIO.v
create mode 100644 pads/verilog/PAD_VDDSOC.v
create mode 100644 pads/verilog/PAD_VSS.v
create mode 100644 pads/verilog/PAD_VSSIO.v
diff --git a/pads/verilog/PAD_INOUT8MA_NOE.v b/pads/verilog/PAD_INOUT8MA_NOE.v
new file mode 100644
index 0000000..fa92fec
--- /dev/null
+++ b/pads/verilog/PAD_INOUT8MA_NOE.v
@@ -0,0 +1,37 @@
+// from GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module PAD_INOUT8MA_NOE (
+ // Inouts
+ PAD,
+ // Outputs
+ I,
+ // Inputs
+ O,
+ NOE
+ );
+ inout PAD;
+ output I;
+ input O;
+ input NOE;
+
+ IOBUF #(
+ .IOSTANDARD ("LVCMOS33"),
+ .DRIVE(8)
+ ) IOBUF3V3 (
+ .O(I),
+ .IO(PAD),
+ .I(O),
+ .T(NOE)
+ );
+
+endmodule // PAD_INOUT8MA_NOE
diff --git a/pads/verilog/PAD_VDDIO.v b/pads/verilog/PAD_VDDIO.v
new file mode 100644
index 0000000..4fd7137
--- /dev/null
+++ b/pads/verilog/PAD_VDDIO.v
@@ -0,0 +1,29 @@
+// from GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module PAD_VDDIO (
+ // Inouts
+ PAD
+ );
+ inout PAD;
+
+ IOBUF #(
+ .IOSTANDARD ("LVCMOS33"),
+ .DRIVE(8)
+ ) IOBUF3V3 (
+ .O( ),
+ .IO(PAD),
+ .I(1'b1),
+ .T(1'b1)
+ );
+
+endmodule // PAD_VDDIO
diff --git a/pads/verilog/PAD_VDDSOC.v b/pads/verilog/PAD_VDDSOC.v
new file mode 100644
index 0000000..80f6a72
--- /dev/null
+++ b/pads/verilog/PAD_VDDSOC.v
@@ -0,0 +1,29 @@
+// from GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module PAD_VDDSOC (
+ // Inouts
+ PAD
+ );
+ inout PAD;
+
+ IOBUF #(
+ .IOSTANDARD ("LVCMOS33"),
+ .DRIVE(8)
+ ) IOBUF3V3 (
+ .O( ),
+ .IO(PAD),
+ .I(1'b1),
+ .T(1'b1)
+ );
+
+endmodule // PAD_VDDSOC
diff --git a/pads/verilog/PAD_VSS.v b/pads/verilog/PAD_VSS.v
new file mode 100644
index 0000000..046a389
--- /dev/null
+++ b/pads/verilog/PAD_VSS.v
@@ -0,0 +1,29 @@
+// from GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module PAD_VSS (
+ // Inouts
+ PAD
+ );
+ inout PAD;
+
+ IOBUF #(
+ .IOSTANDARD ("LVCMOS33"),
+ .DRIVE(8)
+ ) IOBUF3V3 (
+ .O( ),
+ .IO(PAD),
+ .I(1'b1),
+ .T(1'b1)
+ );
+
+endmodule // PAD_VSS
diff --git a/pads/verilog/PAD_VSSIO.v b/pads/verilog/PAD_VSSIO.v
new file mode 100644
index 0000000..6bfb333
--- /dev/null
+++ b/pads/verilog/PAD_VSSIO.v
@@ -0,0 +1,29 @@
+// from GLIB_PADLIB.v
+//-----------------------------------------------------------------------------
+// soclabs generic IO pad model
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module PAD_VSSIO (
+ // Inouts
+ PAD
+ );
+ inout PAD;
+
+ IOBUF #(
+ .IOSTANDARD ("LVCMOS33"),
+ .DRIVE(8)
+ ) IOBUF3V3 (
+ .O( ),
+ .IO(PAD),
+ .I(1'b1),
+ .T(1'b1)
+ );
+
+endmodule // PAD_VSSIO
--
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