Update verilog testbench + add cocotb test ext ram

.gitignore

flist/expansion_subsystem.vc

flows/makefile.simulate

...expansion_subsystem/verilog/expansion_subsystem_wrapper.v

makefile

verif/cocotb/expansion_subsystem_tests.py

verif/testbench/logical/clk_ctrl.v

verif/testbench/logical/clk_reset.v

verif/testbench/logical/expansion_subsystem_tb.v

verif/testbench/logical/expansion_subsystem_tb.vc

verif/testbench/logical/trickbox/trickbox.v