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Update verilog testbench + add cocotb test ext ram
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- .gitignore 2 additions, 0 deletions.gitignore
- flist/expansion_subsystem.vc 10 additions, 0 deletionsflist/expansion_subsystem.vc
- flows/makefile.simulate 151 additions, 2 deletionsflows/makefile.simulate
- logical/top_expansion_subsystem/verilog/expansion_subsystem_wrapper.v 4 additions, 4 deletions...expansion_subsystem/verilog/expansion_subsystem_wrapper.v
- makefile 36 additions, 0 deletionsmakefile
- verif/cocotb/expansion_subsystem_tests.py 99 additions, 2 deletionsverif/cocotb/expansion_subsystem_tests.py
- verif/testbench/logical/clk_ctrl.v 112 additions, 0 deletionsverif/testbench/logical/clk_ctrl.v
- verif/testbench/logical/clk_reset.v 86 additions, 0 deletionsverif/testbench/logical/clk_reset.v
- verif/testbench/logical/expansion_subsystem_tb.v 241 additions, 1 deletionverif/testbench/logical/expansion_subsystem_tb.v
- verif/testbench/logical/expansion_subsystem_tb.vc 6 additions, 0 deletionsverif/testbench/logical/expansion_subsystem_tb.vc
- verif/testbench/logical/trickbox/trickbox.v 45 additions, 0 deletionsverif/testbench/logical/trickbox/trickbox.v
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