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Commit 6cfc1e41 authored by Daniel Newbrook's avatar Daniel Newbrook
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Update set_env

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flist/millisoc_expansion_cocotb.flist
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VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/expansion_region/verilog/expansion_region.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/expansion_region/verilog/expansion_region.v
#SRAM files #SRAM files
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/SRAM/verilog/SRAM_wrapper.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SRAM/verilog/SRAM_wrapper.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/SRAM/verilog/SRAM.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SRAM/verilog/SRAM.v
#BP301 SRAM controller files #BP301 SRAM controller files
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/SMC/logical/models/cells/generic/sie300_arm_and2.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/models/cells/generic/sie300_arm_and2.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/SMC/logical/models/cells/generic/sie300_arm_or2.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/models/cells/generic/sie300_arm_or2.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/SMC/logical/models/cells/generic/sie300_arm_sdff2yrpq.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/models/cells/generic/sie300_arm_sdff2yrpq.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/SMC/logical/models/cells/generic/sie300_arm_xor2.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/models/cells/generic/sie300_arm_xor2.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/SMC/logical/shared/verilog/sie300_or_tree/verilog/sie300_or_tree.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/shared/verilog/sie300_or_tree/verilog/sie300_or_tree.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/SMC/logical/shared/verilog/sie300_sync/verilog/sie300_sync.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/shared/verilog/sie300_sync/verilog/sie300_sync.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_addr_dec.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_addr_dec.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_arb.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_arb.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_arq.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_arq.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_awq.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_awq.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_axi_mux.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_axi_mux.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_bq.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_bq.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_clamp.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_clamp.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_eam.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_eam.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_fifo.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_fifo.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_fifo_core.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_fifo_core.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_lpi_ctrl.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_lpi_ctrl.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_one_hot.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_one_hot.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_rbeat.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_rbeat.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_resp_gen.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_resp_gen.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_rq.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_rq.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_wbeat.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_wbeat.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_wq.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/SMC/logical/sie300_axi5_sram_ctrl_millisoc_exp/verilog/sie300_axi5_sram_ctrl_millisoc_exp_wq.sv
#DMA350 files #DMA350 files
EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/shared/verilog EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/shared/verilog
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/shared/verilog/ada_gen_regmap_sldma350_pkg.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_gen_regmap_sldma350_pkg.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/shared/verilog/ada_apb_regmap_conv_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_apb_regmap_conv_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/shared/verilog/ada_reg_field_ro_ro_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_reg_field_ro_ro_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/shared/verilog/ada_reg_field_rw_ro_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_reg_field_rw_ro_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/shared/verilog/ada_reg_field_rw_w1c_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_reg_field_rw_w1c_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/shared/verilog/ada_reg_field_rw_w1s_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_reg_field_rw_w1s_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/shared/verilog/ada_reg_field_rw_rw_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_reg_field_rw_rw_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/shared/verilog/ada_gen_coreif_dmach_sldma350_pkg.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_gen_coreif_dmach_sldma350_pkg.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/shared/verilog/ada_gen_addrmap_dmach_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_gen_addrmap_dmach_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/shared/verilog/ada_interface_sldma350_pkg.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_interface_sldma350_pkg.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/shared/verilog/ada_flop_en/verilog/ada_flop_en.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_flop_en/verilog/ada_flop_en.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/shared/verilog/ada_or_tree/verilog/ada_or_tree.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_or_tree/verilog/ada_or_tree.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/shared/verilog/ada_gen_regif_dmainfo_sldma350_pkg.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_gen_regif_dmainfo_sldma350_pkg.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/models/cells/generic/ada_arm_flop.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/models/cells/generic/ada_arm_flop.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/models/cells/generic/ada_arm_sync.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/models/cells/generic/ada_arm_sync.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/models/cells/generic/ada_arm_mux2.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/models/cells/generic/ada_arm_mux2.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/models/cells/generic/ada_arm_or.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/models/cells/generic/ada_arm_or.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/models/cells/generic/ada_arm_idbit_v1.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/models/cells/generic/ada_arm_idbit_v1.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/shared/verilog/ada_ecorevnum.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/shared/verilog/ada_ecorevnum.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_top_sldma350/verilog/ada_top_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_top_sldma350/verilog/ada_top_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_gen_regif_dmach_0_sldma350_pkg.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_gen_regif_dmach_0_sldma350_pkg.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_gen_regif_dmach_0_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_gen_regif_dmach_0_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_gen_regmap_dmach_0_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_gen_regmap_dmach_0_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_gen_fields_coreif_dmach_0_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_gen_fields_coreif_dmach_0_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_gen_coreif_res_dmach_0_sldma350_pkg.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_gen_coreif_res_dmach_0_sldma350_pkg.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_sldma350_pkg.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_sldma350_pkg.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_ctrl_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_ctrl_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_1d_wr_ctrl_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_1d_wr_ctrl_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_2d_wr_ctrl_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_2d_wr_ctrl_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_1d_rd_ctrl_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_1d_rd_ctrl_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_2d_rd_ctrl_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_2d_rd_ctrl_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_fifo_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_fifo_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_cmdlink_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_cmdlink_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_axi_rd_if_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_axi_rd_if_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_axi_wr_if_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_axi_wr_if_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_axi_stop_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_axi_stop_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_reg_bank_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_reg_bank_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_inc_gen_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_inc_gen_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_wrapper_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_wrapper_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_slave_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_slave_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_master_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_master_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_bypass_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_bypass_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_trig_in_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_trig_in_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_trig_out_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_0_sldma350/verilog/ada_channel_0_trig_out_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_gen_regif_dmach_1_sldma350_pkg.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_gen_regif_dmach_1_sldma350_pkg.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_gen_regif_dmach_1_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_gen_regif_dmach_1_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_gen_regmap_dmach_1_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_gen_regmap_dmach_1_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_gen_fields_coreif_dmach_1_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_gen_fields_coreif_dmach_1_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_gen_coreif_res_dmach_1_sldma350_pkg.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_gen_coreif_res_dmach_1_sldma350_pkg.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_sldma350_pkg.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_sldma350_pkg.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_ctrl_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_ctrl_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_1d_wr_ctrl_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_1d_wr_ctrl_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_2d_wr_ctrl_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_2d_wr_ctrl_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_1d_rd_ctrl_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_1d_rd_ctrl_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_2d_rd_ctrl_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_2d_rd_ctrl_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_fifo_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_fifo_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_cmdlink_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_cmdlink_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_axi_rd_if_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_axi_rd_if_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_axi_wr_if_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_axi_wr_if_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_axi_stop_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_axi_stop_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_reg_bank_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_reg_bank_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_inc_gen_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_inc_gen_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_stream_wrapper_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_stream_wrapper_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_stream_slave_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_stream_slave_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_stream_master_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_stream_master_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_stream_bypass_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_stream_bypass_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_trig_in_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_trig_in_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_trig_out_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_1_sldma350/verilog/ada_channel_1_trig_out_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_gen_regif_dmach_2_sldma350_pkg.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_gen_regif_dmach_2_sldma350_pkg.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_gen_regif_dmach_2_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_gen_regif_dmach_2_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_gen_regmap_dmach_2_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_gen_regmap_dmach_2_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_gen_fields_coreif_dmach_2_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_gen_fields_coreif_dmach_2_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_gen_coreif_res_dmach_2_sldma350_pkg.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_gen_coreif_res_dmach_2_sldma350_pkg.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_sldma350_pkg.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_sldma350_pkg.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_ctrl_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_ctrl_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_1d_wr_ctrl_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_1d_wr_ctrl_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_1d_rd_ctrl_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_1d_rd_ctrl_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_fifo_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_fifo_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_cmdlink_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_cmdlink_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_axi_rd_if_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_axi_rd_if_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_axi_wr_if_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_axi_wr_if_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_axi_stop_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_axi_stop_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_reg_bank_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_reg_bank_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_trig_in_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_trig_in_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_trig_out_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_2_sldma350/verilog/ada_channel_2_trig_out_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_gen_regif_dmach_3_sldma350_pkg.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_gen_regif_dmach_3_sldma350_pkg.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_gen_regif_dmach_3_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_gen_regif_dmach_3_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_gen_regmap_dmach_3_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_gen_regmap_dmach_3_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_gen_fields_coreif_dmach_3_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_gen_fields_coreif_dmach_3_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_gen_coreif_res_dmach_3_sldma350_pkg.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_gen_coreif_res_dmach_3_sldma350_pkg.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_sldma350_pkg.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_sldma350_pkg.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_ctrl_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_ctrl_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_1d_wr_ctrl_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_1d_wr_ctrl_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_1d_rd_ctrl_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_1d_rd_ctrl_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_fifo_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_fifo_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_cmdlink_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_cmdlink_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_axi_rd_if_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_axi_rd_if_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_axi_wr_if_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_axi_wr_if_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_axi_stop_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_axi_stop_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_reg_bank_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_reg_bank_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_trig_in_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_trig_in_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_trig_out_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_channel_3_sldma350/verilog/ada_channel_3_trig_out_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_read_switch_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_read_switch_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_read_switch_wrapper_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_read_switch_wrapper_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_write_switch_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_write_switch_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_write_switch_wrapper_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_write_switch_wrapper_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_arbiter_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_arbiter_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_qv_cmp_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_qv_cmp_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_lrg_arb_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_lrg_arb_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_grant_queue_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_grant_queue_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_full_f2s_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_full_f2s_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_reverse_s2f_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_biu_sldma350/verilog/ada_biu_reverse_s2f_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_regif_dmainfo_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_regif_dmainfo_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_regmap_dmainfo_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_regmap_dmainfo_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_fields_coreif_dmainfo_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_fields_coreif_dmainfo_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_addrmap_dmainfo_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_addrmap_dmainfo_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_coreif_dmansecctrl_sldma350_pkg.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_coreif_dmansecctrl_sldma350_pkg.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_regif_dmansecctrl_sldma350_pkg.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_regif_dmansecctrl_sldma350_pkg.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_regif_dmansecctrl_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_regif_dmansecctrl_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_regmap_dmansecctrl_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_regmap_dmansecctrl_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_fields_coreif_dmansecctrl_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_fields_coreif_dmansecctrl_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_addrmap_dmansecctrl_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_gen_addrmap_dmansecctrl_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_ctrl_apb_slave_mux_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_ctrl_apb_slave_mux_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_ctrl_dmainfo_reg_bank_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_ctrl_dmainfo_reg_bank_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_ctrl_dmansecctrl_reg_bank_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_ctrl_dmansecctrl_reg_bank_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_ctrl_trigmask_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_ctrl_trigmask_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_ctrl_trigin_used_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_ctrl_trigin_used_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_ctrl_trigout_used_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_ctrl_trigout_used_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_ctrl_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_ctrl_sldma350/verilog/ada_ctrl_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_trigmtx_sldma350/verilog/ada_trigmtx_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_trigmtx_sldma350/verilog/ada_trigmtx_sldma350.sv
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/dma350/logical/ada_qctrl_sldma350/verilog/ada_qctrl_sldma350.sv VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/dma350/logical/ada_qctrl_sldma350/verilog/ada_qctrl_sldma350.sv
#NIC400 files #NIC400 files
EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_EXPANSION/verilog EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_EXPANSION/verilog
EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_EXP_SRAM_0/verilog EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_EXP_SRAM_0/verilog
EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_EXP_SRAM_1/verilog EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_EXP_SRAM_1/verilog
EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_SYS/verilog EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_SYS/verilog
EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_apb_group0/verilog EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_apb_group0/verilog
EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_0/verilog EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_0/verilog
EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_1/verilog EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_1/verilog
EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_EXP_SS/verilog EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_EXP_SS/verilog
EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog
EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog
EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog
EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/default_slave_ds_3/verilog EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/default_slave_ds_3/verilog
EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/default_slave_ds_4/verilog EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/default_slave_ds_4/verilog
EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/dmu_exp/verilog EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/dmu_exp/verilog
EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/dmu_sys/verilog EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/dmu_sys/verilog
EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog
EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog
EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog
EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/reg_slice/verilog EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/reg_slice/verilog
EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/nic400/verilog EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/nic400/verilog
EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/reg_slice/verilog EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/reg_slice/verilog
EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/shared/validation/tb_components/Axi4Frm EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/shared/validation/tb_components/Axi4Frm
EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/shared/validation/tb_components EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/shared/validation/tb_components
EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/shared/validation/tb_components/AxiFrm EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/shared/validation/tb_components/AxiFrm
EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/shared/validation/tb_components/AxiFrs EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/shared/validation/tb_components/AxiFrs
EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/nic400/verilog/Axi EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/nic400/verilog/Axi
EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/nic400/verilog/ApbPC EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/nic400/verilog/ApbPC
EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/nic400/verilog/Apb4PC EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/nic400/verilog/Apb4PC
EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/nic400/verilog/AxiPC EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/nic400/verilog/AxiPC
EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/nic400/verilog/Axi4PC EXTRA_ARGS += +incdir+$(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/nic400/verilog/Axi4PC
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/nic400/verilog/nic400_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/nic400/verilog/nic400_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_EXPANSION/verilog/nic400_amib_AXI_EXPANSION_chan_slice_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_EXPANSION/verilog/nic400_amib_AXI_EXPANSION_chan_slice_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_EXPANSION/verilog/nic400_amib_AXI_EXPANSION_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_EXPANSION/verilog/nic400_amib_AXI_EXPANSION_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_EXP_SRAM_0/verilog/nic400_amib_AXI_EXP_SRAM_0_chan_slice_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_EXP_SRAM_0/verilog/nic400_amib_AXI_EXP_SRAM_0_chan_slice_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_EXP_SRAM_0/verilog/nic400_amib_AXI_EXP_SRAM_0_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_EXP_SRAM_0/verilog/nic400_amib_AXI_EXP_SRAM_0_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_EXP_SRAM_1/verilog/nic400_amib_AXI_EXP_SRAM_1_chan_slice_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_EXP_SRAM_1/verilog/nic400_amib_AXI_EXP_SRAM_1_chan_slice_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_EXP_SRAM_1/verilog/nic400_amib_AXI_EXP_SRAM_1_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_EXP_SRAM_1/verilog/nic400_amib_AXI_EXP_SRAM_1_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_SYS/verilog/nic400_amib_AXI_SYS_chan_slice_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_SYS/verilog/nic400_amib_AXI_SYS_chan_slice_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_SYS/verilog/nic400_amib_AXI_SYS_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_AXI_SYS/verilog/nic400_amib_AXI_SYS_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_apb_group0/verilog/nic400_amib_apb_group0_a_gen_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_apb_group0/verilog/nic400_amib_apb_group0_a_gen_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_apb_group0/verilog/nic400_amib_apb_group0_apb_m_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_apb_group0/verilog/nic400_amib_apb_group0_apb_m_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_apb_group0/verilog/nic400_amib_apb_group0_chan_slice_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_apb_group0/verilog/nic400_amib_apb_group0_chan_slice_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_apb_group0/verilog/nic400_amib_apb_group0_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/amib_apb_group0/verilog/nic400_amib_apb_group0_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_0/verilog/nic400_asib_AXI_DMA_0_chan_slice_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_0/verilog/nic400_asib_AXI_DMA_0_chan_slice_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_0/verilog/nic400_asib_AXI_DMA_0_decode_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_0/verilog/nic400_asib_AXI_DMA_0_decode_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_0/verilog/nic400_asib_AXI_DMA_0_maskcntl_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_0/verilog/nic400_asib_AXI_DMA_0_maskcntl_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_0/verilog/nic400_asib_AXI_DMA_0_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_0/verilog/nic400_asib_AXI_DMA_0_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_0/verilog/nic400_asib_AXI_DMA_0_rd_ss_cdas_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_0/verilog/nic400_asib_AXI_DMA_0_rd_ss_cdas_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_0/verilog/nic400_asib_AXI_DMA_0_wr_ss_cdas_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_0/verilog/nic400_asib_AXI_DMA_0_wr_ss_cdas_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_1/verilog/nic400_asib_AXI_DMA_1_chan_slice_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_1/verilog/nic400_asib_AXI_DMA_1_chan_slice_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_1/verilog/nic400_asib_AXI_DMA_1_decode_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_1/verilog/nic400_asib_AXI_DMA_1_decode_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_1/verilog/nic400_asib_AXI_DMA_1_maskcntl_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_1/verilog/nic400_asib_AXI_DMA_1_maskcntl_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_1/verilog/nic400_asib_AXI_DMA_1_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_1/verilog/nic400_asib_AXI_DMA_1_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_1/verilog/nic400_asib_AXI_DMA_1_rd_ss_cdas_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_1/verilog/nic400_asib_AXI_DMA_1_rd_ss_cdas_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_1/verilog/nic400_asib_AXI_DMA_1_wr_ss_cdas_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_DMA_1/verilog/nic400_asib_AXI_DMA_1_wr_ss_cdas_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_EXP_SS/verilog/nic400_asib_AXI_EXP_SS_chan_slice_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_EXP_SS/verilog/nic400_asib_AXI_EXP_SS_chan_slice_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_EXP_SS/verilog/nic400_asib_AXI_EXP_SS_decode_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_EXP_SS/verilog/nic400_asib_AXI_EXP_SS_decode_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_EXP_SS/verilog/nic400_asib_AXI_EXP_SS_maskcntl_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_EXP_SS/verilog/nic400_asib_AXI_EXP_SS_maskcntl_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_EXP_SS/verilog/nic400_asib_AXI_EXP_SS_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_EXP_SS/verilog/nic400_asib_AXI_EXP_SS_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_EXP_SS/verilog/nic400_asib_AXI_EXP_SS_rd_ss_cdas_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_EXP_SS/verilog/nic400_asib_AXI_EXP_SS_rd_ss_cdas_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_EXP_SS/verilog/nic400_asib_AXI_EXP_SS_wr_ss_cdas_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/asib_AXI_EXP_SS/verilog/nic400_asib_AXI_EXP_SS_wr_ss_cdas_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml0_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml0_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml1_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml1_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml2_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_add_sel_ml2_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml0_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml0_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml1_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml1_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml2_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_maskcntl_ml2_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_ml_blayer_0_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_ml_blayer_0_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_ml_build_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_ml_build_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_ml_map_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_ml_map_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_0_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_0_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_1_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_1_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_2_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_ml_mlayer_2_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_rd_ss_tt_s0_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_rd_ss_tt_s0_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml0_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml0_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml1_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml1_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml2_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_ret_sel_ml2_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml0_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml0_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml1_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml1_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml2_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_wr_sel_ml2_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_wr_ss_tt_s0_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm0/verilog/nic400_bm0_wr_ss_tt_s0_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_add_arb_ml0_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_add_arb_ml0_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_add_arb_ml1_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_add_arb_ml1_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_add_arb_ml2_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_add_arb_ml2_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_add_arb_ml3_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_add_arb_ml3_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_add_arb_ml4_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_add_arb_ml4_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_add_sel_ml0_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_add_sel_ml0_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_add_sel_ml1_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_add_sel_ml1_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_add_sel_ml2_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_add_sel_ml2_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_add_sel_ml3_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_add_sel_ml3_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_add_sel_ml4_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_add_sel_ml4_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_lrg_arb_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_lrg_arb_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_maskcntl_ml0_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_maskcntl_ml0_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_maskcntl_ml1_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_maskcntl_ml1_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_maskcntl_ml2_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_maskcntl_ml2_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_maskcntl_ml3_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_maskcntl_ml3_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_maskcntl_ml4_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_maskcntl_ml4_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ml_blayer_0_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ml_blayer_0_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ml_blayer_1_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ml_blayer_1_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ml_blayer_2_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ml_blayer_2_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ml_build_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ml_build_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ml_map_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ml_map_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ml_mlayer_0_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ml_mlayer_0_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ml_mlayer_1_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ml_mlayer_1_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ml_mlayer_2_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ml_mlayer_2_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ml_mlayer_3_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ml_mlayer_3_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ml_mlayer_4_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ml_mlayer_4_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_qv_cmp_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_qv_cmp_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_rd_spi_tt_s2_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_rd_spi_tt_s2_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_rd_ss_tt_s0_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_rd_ss_tt_s0_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_rd_ss_tt_s1_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_rd_ss_tt_s1_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_rd_wr_arb_0_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_rd_wr_arb_0_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_rd_wr_arb_1_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_rd_wr_arb_1_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_rd_wr_arb_2_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_rd_wr_arb_2_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ret_sel_ml0_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ret_sel_ml0_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ret_sel_ml1_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ret_sel_ml1_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ret_sel_ml2_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ret_sel_ml2_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ret_sel_ml3_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ret_sel_ml3_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ret_sel_ml4_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_ret_sel_ml4_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_wr_sel_ml0_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_wr_sel_ml0_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_wr_sel_ml1_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_wr_sel_ml1_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_wr_sel_ml2_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_wr_sel_ml2_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_wr_sel_ml3_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_wr_sel_ml3_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_wr_sel_ml4_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_wr_sel_ml4_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_wr_spi_tt_s2_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_wr_spi_tt_s2_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_wr_ss_tt_s0_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_wr_ss_tt_s0_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_wr_ss_tt_s1_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/busmatrix_bm1/verilog/nic400_bm1_wr_ss_tt_s1_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cd_exp_cdc_comb_or_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cd_exp_cdc_comb_or_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cd_sys_cdc_comb_or_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cd_sys_cdc_comb_or_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cdc_bypass_sync_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cdc_bypass_sync_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cdc_capt_nosync_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cdc_capt_nosync_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cdc_capt_sync_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cdc_capt_sync_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cdc_comb_and2_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cdc_comb_and2_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cdc_comb_mux2_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cdc_comb_mux2_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cdc_comb_or2_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cdc_comb_or2_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cdc_comb_or3_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cdc_comb_or3_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cdc_corrupt_gry_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cdc_corrupt_gry_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cdc_launch_gry_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cdc_launch_gry_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cdc_random_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/cdc_blocks/verilog/nic400_cdc_random_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/default_slave_ds_3/verilog/nic400_default_slave_ds_3_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/default_slave_ds_3/verilog/nic400_default_slave_ds_3_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/default_slave_ds_4/verilog/nic400_default_slave_ds_4_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/default_slave_ds_4/verilog/nic400_default_slave_ds_4_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/dmu_exp/verilog/nic400_dmu_exp_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/dmu_exp/verilog/nic400_dmu_exp_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/dmu_sys/verilog/nic400_dmu_sys_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/dmu_sys/verilog/nic400_dmu_sys_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_ar_fifo_rd_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_ar_fifo_rd_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_ar_fifo_sync_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_ar_fifo_sync_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_ar_fifo_wr_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_ar_fifo_wr_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_ar_fifo_wr_mux2_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_ar_fifo_wr_mux2_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_ar_fifo_wr_mux_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_ar_fifo_wr_mux_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_aw_fifo_rd_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_aw_fifo_rd_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_aw_fifo_sync_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_aw_fifo_sync_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_aw_fifo_wr_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_aw_fifo_wr_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_aw_fifo_wr_mux2_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_aw_fifo_wr_mux2_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_aw_fifo_wr_mux_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_aw_fifo_wr_mux_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_b_fifo_rd_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_b_fifo_rd_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_b_fifo_sync_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_b_fifo_sync_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_b_fifo_wr_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_b_fifo_wr_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_b_fifo_wr_mux2_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_b_fifo_wr_mux2_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_b_fifo_wr_mux_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_b_fifo_wr_mux_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_chan_slice_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_chan_slice_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_rd_addr_fmt_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_rd_addr_fmt_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_rd_cam_slice_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_rd_cam_slice_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_rd_chan_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_rd_chan_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_rd_cntrl_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_rd_cntrl_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_resp_cam_slice_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_resp_cam_slice_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_wr_addr_fmt_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_wr_addr_fmt_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_wr_cntrl_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_wr_cntrl_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_wr_merge_buffer_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_wr_merge_buffer_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_wr_mux_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_wr_mux_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_wr_resp_block_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_downsize_wr_resp_block_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_maskcntl_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_maskcntl_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_master_domain_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_master_domain_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_r_fifo_rd_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_r_fifo_rd_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_r_fifo_sync_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_r_fifo_sync_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_r_fifo_wr_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_r_fifo_wr_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_r_fifo_wr_mux2_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_r_fifo_wr_mux2_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_r_fifo_wr_mux_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_r_fifo_wr_mux_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_slave_domain_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_slave_domain_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_w_fifo_rd_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_w_fifo_rd_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_w_fifo_sync_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_w_fifo_sync_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_w_fifo_wr_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_w_fifo_wr_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_w_fifo_wr_mux2_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_w_fifo_wr_mux2_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_w_fifo_wr_mux_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_AXI_SYS_ib/verilog/nic400_ib_AXI_SYS_ib_w_fifo_wr_mux_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_a_fifo_rd_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_a_fifo_rd_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_a_fifo_sync_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_a_fifo_sync_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_a_fifo_wr_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_a_fifo_wr_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_a_fifo_wr_mux2_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_a_fifo_wr_mux2_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_a_fifo_wr_mux_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_a_fifo_wr_mux_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_axi_to_itb_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_axi_to_itb_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_chan_slice_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_chan_slice_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_d_fifo_rd_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_d_fifo_rd_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_d_fifo_sync_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_d_fifo_sync_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_d_fifo_wr_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_d_fifo_wr_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_d_fifo_wr_mux2_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_d_fifo_wr_mux2_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_d_fifo_wr_mux_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_d_fifo_wr_mux_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_itb_addr_fmt_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_itb_addr_fmt_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_rd_cam_slice_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_rd_cam_slice_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_rd_chan_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_rd_chan_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_rd_cntrl_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_rd_cntrl_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_resp_cam_slice_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_resp_cam_slice_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_wr_cntrl_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_wr_cntrl_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_wr_merge_buffer_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_wr_merge_buffer_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_wr_mux_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_wr_mux_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_wr_resp_block_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_downsize_wr_resp_block_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_itb_to_axi_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_itb_to_axi_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_itb_trans_counter_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_itb_trans_counter_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_master_domain_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_master_domain_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_slave_domain_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_slave_domain_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_w_fifo_rd_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_w_fifo_rd_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_w_fifo_sync_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_w_fifo_sync_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_w_fifo_wr_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_w_fifo_wr_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_w_fifo_wr_mux2_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_w_fifo_wr_mux2_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_w_fifo_wr_mux_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_apb_group0_ib/verilog/nic400_ib_apb_group0_ib_w_fifo_wr_mux_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_ar_fifo_rd_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_ar_fifo_rd_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_ar_fifo_sync_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_ar_fifo_sync_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_ar_fifo_wr_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_ar_fifo_wr_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_ar_fifo_wr_mux2_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_ar_fifo_wr_mux2_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_ar_fifo_wr_mux_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_ar_fifo_wr_mux_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_aw_fifo_rd_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_aw_fifo_rd_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_aw_fifo_sync_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_aw_fifo_sync_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_aw_fifo_wr_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_aw_fifo_wr_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_aw_fifo_wr_mux2_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_aw_fifo_wr_mux2_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_aw_fifo_wr_mux_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_aw_fifo_wr_mux_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_b_fifo_rd_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_b_fifo_rd_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_b_fifo_sync_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_b_fifo_sync_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_b_fifo_wr_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_b_fifo_wr_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_b_fifo_wr_mux2_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_b_fifo_wr_mux2_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_b_fifo_wr_mux_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_b_fifo_wr_mux_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_chan_slice_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_chan_slice_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_maskcntl_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_maskcntl_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_master_domain_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_master_domain_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_r_fifo_rd_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_r_fifo_rd_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_r_fifo_sync_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_r_fifo_sync_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_r_fifo_wr_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_r_fifo_wr_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_r_fifo_wr_mux2_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_r_fifo_wr_mux2_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_r_fifo_wr_mux_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_r_fifo_wr_mux_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_slave_domain_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_slave_domain_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_upsize_rd_addr_fmt_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_upsize_rd_addr_fmt_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_upsize_rd_cam_slice_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_upsize_rd_cam_slice_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_upsize_rd_chan_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_upsize_rd_chan_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_upsize_resp_cam_slice_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_upsize_resp_cam_slice_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_upsize_wr_addr_fmt_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_upsize_wr_addr_fmt_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_upsize_wr_cntrl_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_upsize_wr_cntrl_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_upsize_wr_merge_buffer_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_upsize_wr_merge_buffer_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_upsize_wr_resp_block_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_upsize_wr_resp_block_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_w_fifo_rd_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_w_fifo_rd_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_w_fifo_sync_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_w_fifo_sync_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_w_fifo_wr_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_w_fifo_wr_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_w_fifo_wr_mux2_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_w_fifo_wr_mux2_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_w_fifo_wr_mux_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/ib_ib2/verilog/nic400_ib_ib2_w_fifo_wr_mux_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/nic400/verilog/nic400_cd_exp_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/nic400/verilog/nic400_cd_exp_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/nic400/verilog/nic400_cd_sys_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/nic400/verilog/nic400_cd_sys_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/reg_slice/verilog/nic400_ax4_reg_slice_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/reg_slice/verilog/nic400_ax4_reg_slice_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/reg_slice/verilog/nic400_buf_reg_slice_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/reg_slice/verilog/nic400_buf_reg_slice_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/reg_slice/verilog/nic400_ful_regd_slice_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/reg_slice/verilog/nic400_ful_regd_slice_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/reg_slice/verilog/nic400_fwd_regd_slice_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/reg_slice/verilog/nic400_fwd_regd_slice_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/reg_slice/verilog/nic400_rd_reg_slice_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/reg_slice/verilog/nic400_rd_reg_slice_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/reg_slice/verilog/nic400_reg_slice_axi_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/reg_slice/verilog/nic400_reg_slice_axi_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/reg_slice/verilog/nic400_rev_regd_slice_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/reg_slice/verilog/nic400_rev_regd_slice_millisoc_expansion.v
VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/reg_slice/verilog/nic400_wr_reg_slice_millisoc_expansion.v VERILOG_SOURCES += $(SOCLABS_MILLISOC_EXP_TECH_DIR)/logical/nic400_millisoc_expansion/logical/nic400_millisoc_expansion/reg_slice/verilog/nic400_wr_reg_slice_millisoc_expansion.v
set_exp_env.sh
+ 1
− 1
View file @ 6cfc1e41
...@@ -9,4 +9,4 @@ ...@@ -9,4 +9,4 @@
# Copyright � 2021-4, SoC Labs (www.soclabs.org) # Copyright � 2021-4, SoC Labs (www.soclabs.org)
#----------------------------------------------------------------------------- #-----------------------------------------------------------------------------
export SOCLABS_MILLISOC_EXP_DIR=$(pwd) export SOCLABS_MILLISOC_EXP_TECH_DIR=$(pwd)
\ No newline at end of file \ No newline at end of file
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