Part of the milliSoC SoC reference design. This expansion sub-system is where you will integrate your accelerator IP into.
Part of the milliSoC SoC reference design. This expansion sub-system is where you will integrate your accelerator IP into.
This subsystem includes a DMA-350, 2x 128 bit SRAMs, and an adress region for your accelerator.
This subsystem includes a DMA-350, 2x 128 bit SRAMs, and an adress region for your accelerator.
The purpose of this subsystem is deliver high bandwidth data to and from your hardware accelerator. The NIC400 bus with DMA-350 as master can reach bandwidths of 106 Gbps at a clock speed of 1 GHz
The purpose of this subsystem is deliver high bandwidth data to and from your hardware accelerator. The NIC400 bus with DMA-350 as master can reach bandwidths of 106 Gbps at a clock speed of 1 GHz
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@@ -38,7 +41,7 @@ The subsystem has an expansion region where you can integrate your accelerator.
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@@ -38,7 +41,7 @@ The subsystem has an expansion region where you can integrate your accelerator.
## Support
## Support
For support please go to soclabs.org
For support please go to [soclabs.org](https://soclabs.org/)
## Contributing
## Contributing
Open to collaborations, if you're interested please head over to soclabs.org and register your interest on the millisoc reference design project
Open to collaborations, if you're interested please head over to soclabs.org and register your interest on the millisoc reference design project