@@ -24,6 +24,19 @@ For FPGA development you will need a Vivado installation
## Accelerator integration
The subsystem has an expansion region where you can integrate your accelerator. This includes a full AXI slave port with 128-bit data width, an APB port for register interfacing with your accelerator, as well as clock and power control (Q and P-channel).
## Memory Map
| Region | Base Adress | Size | End Adress |
| ------ | ------ | ------ | ------ |
| System (AXI) | 0x00000000 | 0x100000 | 0x001FFFFF |
