From 0d1f1990312f91febc669e77fa77d4df754248ac Mon Sep 17 00:00:00 2001
From: dwn1c21 <d.newbrook@soton.ac.uk>
Date: Tue, 9 Apr 2024 19:57:59 +0000
Subject: [PATCH] Update README.md

---
 README.md | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/README.md b/README.md
index ffe662f..36518bc 100644
--- a/README.md
+++ b/README.md
@@ -24,6 +24,19 @@ For FPGA development you will need a Vivado installation
 ## Accelerator integration
 The subsystem has an expansion region where you can integrate your accelerator. This includes a full AXI slave port with 128-bit data width, an APB port for register interfacing with your accelerator, as well as clock and power control (Q and P-channel).
 
+## Memory Map
+|    Region       | Base Adress | Size     | End Adress |
+| ------          | ------      | ------   | ------     |
+| System (AXI)    | 0x00000000  | 0x100000 | 0x001FFFFF | 
+| SRAM 0          | 0x60000000  | 0x40000  | 0x6003FFFF |
+| SRAM 1          | 0x60040000  | 0x40000  | 0x6007FFFF |
+| Expansion (AXI) | 0x60080000  | 0x40000  | 0x600BFFFF |
+| DMA (APB)       | 0x600C0000  | 0x2000   | 0x600C1FFF |
+| Expansion (APB) | 0x600C2000  | 0x1000   | 0x600C2FFF |
+| SRAM 0 (Alias)  | 0x68000000  | 0x40000  | 0x6803FFFF |
+| SRAM 1 (Alias)  | 0x68040000  | 0x40000  | 0x6807FFFF |
+
+
 ## Support
 For support please go to soclabs.org
 
-- 
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