reference log files for CPU trace and UART2 added (cac739f9) · Commits · SoCLabs / Cortex M0 Baseline Tech · GitLab

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cac739f9

Commit cac739f9 authored 3 years ago by dwf1m12

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reference log files for CPU trace and UART2 added

parent 8e53e93e

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Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/rtl_sim/tarmac0.log_ref 206821 additions, 0 deletions

...oclabs_demo/systems/cortex_m0_mcu/rtl_sim/tarmac0.log_ref
Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/rtl_sim/uart2.log_ref 8 additions, 0 deletions

.../soclabs_demo/systems/cortex_m0_mcu/rtl_sim/uart2.log_ref

with 206829 additions and 0 deletions

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