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Commit 8e53e93e authored by dwf1m12's avatar dwf1m12
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added header and date stamp to bootrom.v generator

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Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/bootrom.v
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//------------------------------------------------------------------------------------
// customised auto-generated synthesizable ROM module abstraction
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
// Date: 220107
// Copyright (c) 2021-2, SoC Labs (www.soclabs.org)
//------------------------------------------------------------------------------------
module bootrom ( module bootrom (
input wire CLK, input wire CLK,
input wire EN, input wire EN,
......
Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu.v
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...@@ -36,7 +36,7 @@ ...@@ -36,7 +36,7 @@
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
// //
`define SYNTHBOOT 1 `define SYNTHBOOTROM 1
`include "cmsdk_mcu_defs.v" `include "cmsdk_mcu_defs.v"
......
GLIB/mem/verilog/SROM_Ax32.v
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//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
// //
// Synthesizable byte-write addressible R/W (random-access) memory // Synthesizable byte-write addressible R/W (random-access) memory
// //
// Synchronous data write, flow-though (non-pipeline registered) read data // Synchronous data write, flow-though (non-pipeline registered) read data
// //
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. // A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
// //
// Contributors // Contributors
// //
// David Flynn (d.w.flynn@soton.ac.uk) // David Flynn (d.w.flynn@soton.ac.uk)
// //
// Copyright 2021, SoC Labs (www.soclabs.org) // Copyright 2021, SoC Labs (www.soclabs.org)
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
module SROM_Ax32 module SROM_Ax32
#(parameter ADDRWIDTH = 10, #(parameter ADDRWIDTH = 10,
parameter filename = "rom32.hex", parameter filename = "rom32.hex",
parameter romgen = 0 parameter romgen = 0
) )
(input wire CLK, (input wire CLK,
input wire [ADDRWIDTH-1:0] ADDR, //Address Input input wire [ADDRWIDTH-1:0] ADDR, //Address Input
input wire SEL, //Select (active-high) input wire SEL, //Select (active-high)
output wire [31:0] RDATA); //Read Data output wire [31:0] RDATA); //Read Data
localparam MEMDEPTH = (1 << (ADDRWIDTH)-1)-1; localparam MEMDEPTH = (1 << (ADDRWIDTH)-1)-1;
localparam romgenfile = "rom32_bootmem.v"; localparam romgenfile = "bootmem.v";
// Reg declarations // Reg declarations
reg [7:0] rombyte0 [0:MEMDEPTH]; reg [7:0] rombyte0 [0:MEMDEPTH];
reg [7:0] rombyte1 [0:MEMDEPTH]; reg [7:0] rombyte1 [0:MEMDEPTH];
reg [7:0] rombyte2 [0:MEMDEPTH]; reg [7:0] rombyte2 [0:MEMDEPTH];
reg [7:0] rombyte3 [0:MEMDEPTH]; reg [7:0] rombyte3 [0:MEMDEPTH];
reg [ADDRWIDTH-1:0] addr_r; // registered Address for read access reg [ADDRWIDTH-1:0] addr_r; // registered Address for read access
// optional simulation RAM_INIT option to suppress 'X' initial contents // optional simulation RAM_INIT option to suppress 'X' initial contents
`ifdef MEM_INIT `ifdef MEM_INIT
reg [7:0] fileimage [((4<<ADDRWIDTH)-1):0]; reg [7:0] fileimage [((4<<ADDRWIDTH)-1):0];
function [31:0] NoX32; input [31:0] n; NoX32 = (((^n) === 1'bx) ? 32'h0 : n); endfunction function [31:0] NoX32; input [31:0] n; NoX32 = (((^n) === 1'bx) ? 32'h0 : n); endfunction
integer fd; // file descriptor for file output integer fd; // file descriptor for file output
integer i; integer i;
initial reg [23:0] today [0:1];
begin
for (i=0; i<= MEMDEPTH; i=i+1) begin initial
rombyte0[i] <= 8'he5; begin
rombyte1[i] <= 8'he5; $system("date +%y%m%d >date_file"); //format yymmdd
rombyte2[i] <= 8'he5; $readmemh("date_file", today);
rombyte3[i] <= 8'he5; $display("data_file: %x", today[0]);
end
if (filename != "") begin for (i=0; i<= MEMDEPTH; i=i+1) begin
$readmemh(filename, fileimage); rombyte0[i] <= 8'he5;
for (i = 0; i <= MEMDEPTH; i=i+1) begin rombyte1[i] <= 8'he5;
rombyte0[i] <= fileimage[(i<<2)+0]; rombyte2[i] <= 8'he5;
rombyte1[i] <= fileimage[(i<<2)+1]; rombyte3[i] <= 8'he5;
rombyte2[i] <= fileimage[(i<<2)+2]; end
rombyte3[i] <= fileimage[(i<<2)+3]; if (filename != "") begin
end $readmemh(filename, fileimage);
end for (i = 0; i <= MEMDEPTH; i=i+1) begin
if (romgen != 0) rombyte0[i] <= fileimage[(i<<2)+0];
begin rombyte1[i] <= fileimage[(i<<2)+1];
fd = $fopen(romgenfile); rombyte2[i] <= fileimage[(i<<2)+2];
if(fd == 0) begin rombyte3[i] <= fileimage[(i<<2)+3];
$display("rom32gen: Error, zero returned in response to $fopen\n"); end
end end
else begin if (romgen != 0)
$display(fd,"rom32gen: Generating output file\n"); begin
$fwrite(fd,"module bootrom (\n"); fd = $fopen(romgenfile);
$fwrite(fd," input wire CLK,\n"); if(fd == 0) begin
$fwrite(fd," input wire EN,\n"); $display("rom32gen: Error, zero returned in response to $fopen\n");
$fwrite(fd," input wire [%0d:2] ADDR,\n", ADDRWIDTH+1); end
$fwrite(fd," output reg [31:0] RDATA );\n"); else begin
$fwrite(fd,"reg [%0d:2] addr_r;\n", ADDRWIDTH+1); $display(fd,"rom32gen: Generating output file\n");
$fwrite(fd,"always @(posedge CLK) if (EN) addr_r <= ADDR;\n"); $fwrite(fd,"//------------------------------------------------------------------------------------\n");
$fwrite(fd,"always @(addr_r)"); $fwrite(fd,"// customised auto-generated synthesizable ROM module abstraction\n");
$fwrite(fd," case(addr_r[%0d:2]) \n", ADDRWIDTH+1); $fwrite(fd,"// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.\n");
for (i = 0; i < 4 << (ADDRWIDTH); i=i+4) $fwrite(fd,"//\n");
$fwrite(fd," %2d'h%2x : RDATA <= 32'h%8x; // 0x%04x\n", ADDRWIDTH, i>>2, NoX32({fileimage[i+3],fileimage[i+2],fileimage[i+1],fileimage[i+0]}), i ); $fwrite(fd,"// Contributors\n");
$fwrite(fd," default : RDATA <=32'h0;\n"); $fwrite(fd,"//\n");
$fwrite(fd," endcase\n"); $fwrite(fd,"// David Flynn (d.w.flynn@soton.ac.uk)\n");
$fwrite(fd,"endmodule\n"); $fwrite(fd,"// Date: %x\n", today[0]);
$fclose(fd); $fwrite(fd,"// Copyright (c) 2021-2, SoC Labs (www.soclabs.org)\n");
end $fwrite(fd,"//------------------------------------------------------------------------------------\n");
end $fwrite(fd,"module bootrom (\n");
end $fwrite(fd," input wire CLK,\n");
`endif $fwrite(fd," input wire EN,\n");
$fwrite(fd," input wire [%0d:2] ADDR,\n", ADDRWIDTH+1);
// synchonous address and control $fwrite(fd," output reg [31:0] RDATA );\n");
$fwrite(fd,"reg [%0d:2] addr_r;\n", ADDRWIDTH+1);
always @(posedge CLK) // update on any byte lane read $fwrite(fd,"always @(posedge CLK) if (EN) addr_r <= ADDR;\n");
if (SEL) $fwrite(fd,"always @(addr_r)");
addr_r <= ADDR[ADDRWIDTH-1:0]; $fwrite(fd," case(addr_r[%0d:2]) \n", ADDRWIDTH+1);
for (i = 0; i < 4 << (ADDRWIDTH); i=i+4)
assign RDATA = {rombyte3[addr_r],rombyte2[addr_r],rombyte1[addr_r],rombyte0[addr_r]}; $fwrite(fd," %2d'h%2x : RDATA <= 32'h%8x; // 0x%04x\n", ADDRWIDTH, i>>2, NoX32({fileimage[i+3],fileimage[i+2],fileimage[i+1],fileimage[i+0]}), i );
$fwrite(fd," default : RDATA <=32'h0;\n");
endmodule $fwrite(fd," endcase\n");
$fwrite(fd,"endmodule\n");
$fclose(fd);
end
end
end
`endif
// synchonous address and control
always @(posedge CLK) // update on any byte lane read
if (SEL)
addr_r <= ADDR[ADDRWIDTH-1:0];
assign RDATA = {rombyte3[addr_r],rombyte2[addr_r],rombyte1[addr_r],rombyte0[addr_r]};
endmodule
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