added header and date stamp to bootrom.v generator

Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/bootrom.v

+//------------------------------------------------------------------------------------
+// customised auto-generated synthesizable ROM module abstraction
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//    Date:    220107
+// Copyright (c) 2021-2, SoC Labs (www.soclabs.org)
+//------------------------------------------------------------------------------------
 module bootrom (
   input  wire CLK,
   input  wire EN,

Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu.v

@@ -36,7 +36,7 @@
 //-----------------------------------------------------------------------------
 //
 
-`define SYNTHBOOT 1
+`define SYNTHBOOTROM 1
 
 `include "cmsdk_mcu_defs.v"
 

GLIB/mem/verilog/SROM_Ax32.v

@@ -24,7 +24,7 @@ module SROM_Ax32
     output wire [31:0] RDATA);        //Read Data
     
    localparam MEMDEPTH = (1 << (ADDRWIDTH)-1)-1;
-   localparam romgenfile = "rom32_bootmem.v";
+   localparam romgenfile = "bootmem.v";
 
    // Reg declarations
    reg  [7:0] rombyte0 [0:MEMDEPTH];
@@ -40,8 +40,14 @@ module SROM_Ax32
   function [31:0] NoX32; input [31:0] n; NoX32 = (((^n) === 1'bx) ? 32'h0 : n); endfunction
   integer fd; // file descriptor for file output
   integer i;
+  reg [23:0] today [0:1];
+  
 initial
   begin
+    $system("date +%y%m%d >date_file"); //format yymmdd
+    $readmemh("date_file", today);
+    $display("data_file: %x", today[0]);
+    
     for (i=0; i<= MEMDEPTH; i=i+1) begin
       rombyte0[i] <= 8'he5;
       rombyte1[i] <= 8'he5;
@@ -65,6 +71,16 @@ initial
        end
        else begin
          $display(fd,"rom32gen: Generating output file\n");
+         $fwrite(fd,"//------------------------------------------------------------------------------------\n");
+         $fwrite(fd,"// customised auto-generated synthesizable ROM module abstraction\n");
+         $fwrite(fd,"// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.\n");
+         $fwrite(fd,"//\n");
+         $fwrite(fd,"// Contributors\n");
+         $fwrite(fd,"//\n");
+         $fwrite(fd,"// David Flynn (d.w.flynn@soton.ac.uk)\n");
+         $fwrite(fd,"//    Date:    %x\n", today[0]);
+         $fwrite(fd,"// Copyright (c) 2021-2, SoC Labs (www.soclabs.org)\n");
+         $fwrite(fd,"//------------------------------------------------------------------------------------\n");
          $fwrite(fd,"module bootrom (\n");
          $fwrite(fd,"  input  wire CLK,\n");
          $fwrite(fd,"  input  wire EN,\n");