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Commit c5e46524 authored by dwf1m12's avatar dwf1m12
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Add UART2 and FT1248 boot code message support, 20MHz for FPGA, 9600baud serial

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Cortex-M0/soclabs_demo/software/cmsis/Device/ARM/CMSDK_CM0/Include/CMSDK_CM0.h
+ 3
− 1
View file @ c5e46524
......@@ -1268,7 +1268,8 @@ __IO uint32_t MODECTRL;
#define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL)
#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL)
#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL)
#define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0xE000UL) //0x6000UL)
#define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL)
#define CMSDK_USRT2_BASE (CMSDK_APB_BASE + 0xE000UL) //0x6000UL)
#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
#define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL)
......@@ -1290,6 +1291,7 @@ __IO uint32_t MODECTRL;
#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
#define CMSDK_USRT2 ((CMSDK_UART_TypeDef *) CMSDK_USRT2_BASE )
#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )
......
Cortex-M0/soclabs_demo/software/common/bootloader/bootloader.c
+ 5
− 2
View file @ c5e46524
......@@ -46,8 +46,9 @@ void UartStdOutInit(void)
{
// CMSDK_UART2->BAUDDIV = 16;
// CMSDK_UART2->CTRL = 0x41; // High speed test mode, TX only
CMSDK_UART2->BAUDDIV = 208; //(1MHz/9600)
CMSDK_UART2->BAUDDIV = 2080; //(20MHz/9600)
CMSDK_UART2->CTRL = 0x01; //TX only, standard UART
CMSDK_USRT2->CTRL = 0x01; //TX only, FT1248 USRT
CMSDK_GPIO1->ALTFUNCSET = (1<<5);
return;
}
......@@ -56,6 +57,8 @@ unsigned char UartPutc(unsigned char my_ch)
{
while ((CMSDK_UART2->STATE & 1)); // Wait if Transmit Holding register is full
CMSDK_UART2->DATA = my_ch; // write to transmit holding register
while ((CMSDK_USRT2->STATE & 1)); // Wait if Transmit Holding register is full
CMSDK_USRT2->DATA = my_ch; // write to transmit holding register
return (my_ch);
}
// Uart string output
......@@ -103,7 +106,7 @@ void FlashLoader(void)
Likely that the user is trying to run bootloader as a test,
which is not what this program is for.
*/
UartPuts("- Error: REMAP is already clear\n");
UartPuts("- Error: REMAP cleared\n");
UartPutc(0x4); // Terminate simulation
while (1);
}
......
Cortex-M0/soclabs_demo/software/common/retarget/uart_stdout.c
+ 5
− 1
View file @ c5e46524
......@@ -47,8 +47,10 @@ void UartStdOutInit(void)
{
// CMSDK_UART2->BAUDDIV = 16;
// CMSDK_UART2->CTRL = 0x41; // High speed test mode, TX only
CMSDK_UART2->BAUDDIV = 208; //(1MHz/9600)
CMSDK_UART2->BAUDDIV = 2080; //(1MHz/9600)
CMSDK_UART2->CTRL = 0x01; //TX only, standard UART
CMSDK_USRT2->BAUDDIV = 2080; //(1MHz/9600)
CMSDK_USRT2->CTRL = 0x01; //TX only, standard UART
CMSDK_GPIO1->ALTFUNCSET = (1<<5);
return;
}
......@@ -57,6 +59,8 @@ unsigned char UartPutc(unsigned char my_ch)
{
while ((CMSDK_UART2->STATE & 1)); // Wait if Transmit Holding register is full
CMSDK_UART2->DATA = my_ch; // write to transmit holding register
while ((CMSDK_USRT2->STATE & 1)); // Wait if Transmit Holding register is full
CMSDK_USRT2->DATA = my_ch; // write to transmit holding register
return (my_ch);
}
// Get a character
......
Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/v2html_doc.tgz
+ 0
− 0
View file @ c5e46524
No preview for this file type
Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/bootrom.v
+ 204
− 204
View file @ c5e46524
......@@ -5,7 +5,7 @@
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
// Date: 2203311024
// Date: 2207011724
// Copyright (c) 2021-2, SoC Labs (www.soclabs.org)
//------------------------------------------------------------------------------------
module bootrom (
......@@ -17,9 +17,9 @@ reg [9:2] addr_r;
always @(posedge CLK) if (EN) addr_r <= ADDR;
always @(addr_r) case(addr_r[9:2])
8'h00 : RDATA <= 32'h20000368; // 0x0000
8'h01 : RDATA <= 32'h010002dd; // 0x0004
8'h02 : RDATA <= 32'h010002e5; // 0x0008
8'h03 : RDATA <= 32'h010002e7; // 0x000c
8'h01 : RDATA <= 32'h01000329; // 0x0004
8'h02 : RDATA <= 32'h01000331; // 0x0008
8'h03 : RDATA <= 32'h01000333; // 0x000c
8'h04 : RDATA <= 32'h00000000; // 0x0010
8'h05 : RDATA <= 32'h00000000; // 0x0014
8'h06 : RDATA <= 32'h00000000; // 0x0018
......@@ -27,43 +27,43 @@ always @(addr_r) case(addr_r[9:2])
8'h08 : RDATA <= 32'h00000000; // 0x0020
8'h09 : RDATA <= 32'h00000000; // 0x0024
8'h0a : RDATA <= 32'h00000000; // 0x0028
8'h0b : RDATA <= 32'h010002e9; // 0x002c
8'h0b : RDATA <= 32'h01000335; // 0x002c
8'h0c : RDATA <= 32'h00000000; // 0x0030
8'h0d : RDATA <= 32'h00000000; // 0x0034
8'h0e : RDATA <= 32'h010002eb; // 0x0038
8'h0f : RDATA <= 32'h010002ed; // 0x003c
8'h10 : RDATA <= 32'h010002ef; // 0x0040
8'h11 : RDATA <= 32'h010002ef; // 0x0044
8'h12 : RDATA <= 32'h010002ef; // 0x0048
8'h13 : RDATA <= 32'h010002ef; // 0x004c
8'h14 : RDATA <= 32'h010002ef; // 0x0050
8'h15 : RDATA <= 32'h010002ef; // 0x0054
8'h16 : RDATA <= 32'h010002ef; // 0x0058
8'h17 : RDATA <= 32'h010002ef; // 0x005c
8'h18 : RDATA <= 32'h010002ef; // 0x0060
8'h19 : RDATA <= 32'h010002ef; // 0x0064
8'h1a : RDATA <= 32'h010002ef; // 0x0068
8'h0e : RDATA <= 32'h01000337; // 0x0038
8'h0f : RDATA <= 32'h01000339; // 0x003c
8'h10 : RDATA <= 32'h0100033b; // 0x0040
8'h11 : RDATA <= 32'h0100033b; // 0x0044
8'h12 : RDATA <= 32'h0100033b; // 0x0048
8'h13 : RDATA <= 32'h0100033b; // 0x004c
8'h14 : RDATA <= 32'h0100033b; // 0x0050
8'h15 : RDATA <= 32'h0100033b; // 0x0054
8'h16 : RDATA <= 32'h0100033b; // 0x0058
8'h17 : RDATA <= 32'h0100033b; // 0x005c
8'h18 : RDATA <= 32'h0100033b; // 0x0060
8'h19 : RDATA <= 32'h0100033b; // 0x0064
8'h1a : RDATA <= 32'h0100033b; // 0x0068
8'h1b : RDATA <= 32'h00000000; // 0x006c
8'h1c : RDATA <= 32'h010002ef; // 0x0070
8'h1d : RDATA <= 32'h010002ef; // 0x0074
8'h1e : RDATA <= 32'h010002ef; // 0x0078
8'h1f : RDATA <= 32'h010002ef; // 0x007c
8'h20 : RDATA <= 32'h010002ef; // 0x0080
8'h21 : RDATA <= 32'h010002ef; // 0x0084
8'h22 : RDATA <= 32'h010002ef; // 0x0088
8'h23 : RDATA <= 32'h010002ef; // 0x008c
8'h24 : RDATA <= 32'h010002ef; // 0x0090
8'h25 : RDATA <= 32'h010002ef; // 0x0094
8'h26 : RDATA <= 32'h010002ef; // 0x0098
8'h27 : RDATA <= 32'h010002ef; // 0x009c
8'h28 : RDATA <= 32'h010002ef; // 0x00a0
8'h29 : RDATA <= 32'h010002ef; // 0x00a4
8'h2a : RDATA <= 32'h010002ef; // 0x00a8
8'h2b : RDATA <= 32'h010002ef; // 0x00ac
8'h2c : RDATA <= 32'h010002ef; // 0x00b0
8'h2d : RDATA <= 32'h010002ef; // 0x00b4
8'h2e : RDATA <= 32'h010002ef; // 0x00b8
8'h2f : RDATA <= 32'h010002ef; // 0x00bc
8'h1c : RDATA <= 32'h0100033b; // 0x0070
8'h1d : RDATA <= 32'h0100033b; // 0x0074
8'h1e : RDATA <= 32'h0100033b; // 0x0078
8'h1f : RDATA <= 32'h0100033b; // 0x007c
8'h20 : RDATA <= 32'h0100033b; // 0x0080
8'h21 : RDATA <= 32'h0100033b; // 0x0084
8'h22 : RDATA <= 32'h0100033b; // 0x0088
8'h23 : RDATA <= 32'h0100033b; // 0x008c
8'h24 : RDATA <= 32'h0100033b; // 0x0090
8'h25 : RDATA <= 32'h0100033b; // 0x0094
8'h26 : RDATA <= 32'h0100033b; // 0x0098
8'h27 : RDATA <= 32'h0100033b; // 0x009c
8'h28 : RDATA <= 32'h0100033b; // 0x00a0
8'h29 : RDATA <= 32'h0100033b; // 0x00a4
8'h2a : RDATA <= 32'h0100033b; // 0x00a8
8'h2b : RDATA <= 32'h0100033b; // 0x00ac
8'h2c : RDATA <= 32'h0100033b; // 0x00b0
8'h2d : RDATA <= 32'h0100033b; // 0x00b4
8'h2e : RDATA <= 32'h0100033b; // 0x00b8
8'h2f : RDATA <= 32'h0100033b; // 0x00bc
8'h30 : RDATA <= 32'hf802f000; // 0x00c0
8'h31 : RDATA <= 32'hf83ef000; // 0x00c4
8'h32 : RDATA <= 32'hc830a00c; // 0x00c8
......@@ -79,8 +79,8 @@ always @(addr_r) case(addr_r[9:2])
8'h3c : RDATA <= 32'h1afbd000; // 0x00f0
8'h3d : RDATA <= 32'h46ab46a2; // 0x00f4
8'h3e : RDATA <= 32'h47184333; // 0x00f8
8'h3f : RDATA <= 32'h00000284; // 0x00fc
8'h40 : RDATA <= 32'h000002a4; // 0x0100
8'h3f : RDATA <= 32'h000002d0; // 0x00fc
8'h40 : RDATA <= 32'h000002f0; // 0x0100
8'h41 : RDATA <= 32'hd3023a10; // 0x0104
8'h42 : RDATA <= 32'hc178c878; // 0x0108
8'h43 : RDATA <= 32'h0752d8fa; // 0x010c
......@@ -97,177 +97,177 @@ always @(addr_r) case(addr_r[9:2])
8'h4e : RDATA <= 32'h4770600b; // 0x0138
8'h4f : RDATA <= 32'hbd1fb51f; // 0x013c
8'h50 : RDATA <= 32'hbd10b510; // 0x0140
8'h51 : RDATA <= 32'hf8e9f000; // 0x0144
8'h51 : RDATA <= 32'hf90ff000; // 0x0144
8'h52 : RDATA <= 32'hf7ff4611; // 0x0148
8'h53 : RDATA <= 32'hf000fff7; // 0x014c
8'h54 : RDATA <= 32'hf000f84a; // 0x0150
8'h55 : RDATA <= 32'hb403f901; // 0x0154
8'h54 : RDATA <= 32'hf000f862; // 0x0150
8'h55 : RDATA <= 32'hb403f927; // 0x0154
8'h56 : RDATA <= 32'hfff2f7ff; // 0x0158
8'h57 : RDATA <= 32'hf000bc03; // 0x015c
8'h58 : RDATA <= 32'h0000f907; // 0x0160
8'h58 : RDATA <= 32'h0000f92d; // 0x0160
8'h59 : RDATA <= 32'h68012000; // 0x0164
8'h5a : RDATA <= 32'h6841468d; // 0x0168
8'h5b : RDATA <= 32'h00004708; // 0x016c
8'h5c : RDATA <= 32'h21d0483c; // 0x0170
8'h5d : RDATA <= 32'h21016101; // 0x0174
8'h5e : RDATA <= 32'h493b6081; // 0x0178
8'h5f : RDATA <= 32'h61882020; // 0x017c
8'h60 : RDATA <= 32'h49384770; // 0x0180
8'h61 : RDATA <= 32'h07d2684a; // 0x0184
8'h62 : RDATA <= 32'h6008d1fc; // 0x0188
8'h63 : RDATA <= 32'h49354770; // 0x018c
8'h64 : RDATA <= 32'h2b007803; // 0x0190
8'h65 : RDATA <= 32'h684ad006; // 0x0194
8'h66 : RDATA <= 32'hd1fc07d2; // 0x0198
8'h67 : RDATA <= 32'h1c40600b; // 0x019c
8'h68 : RDATA <= 32'hd1f52b00; // 0x01a0
8'h69 : RDATA <= 32'hb5104770; // 0x01a4
8'h6a : RDATA <= 32'h68014830; // 0x01a8
8'h6b : RDATA <= 32'hd0082900; // 0x01ac
8'h6c : RDATA <= 32'h60012100; // 0x01b0
8'h6d : RDATA <= 32'h8f4ff3bf; // 0x01b4
8'h6e : RDATA <= 32'h8f6ff3bf; // 0x01b8
8'h6f : RDATA <= 32'hffd2f7ff; // 0x01bc
8'h70 : RDATA <= 32'h4828bd10; // 0x01c0
8'h71 : RDATA <= 32'h781aa32a; // 0x01c4
8'h72 : RDATA <= 32'hd0062a00; // 0x01c8
8'h73 : RDATA <= 32'h07c96841; // 0x01cc
8'h74 : RDATA <= 32'h6002d1fc; // 0x01d0
8'h75 : RDATA <= 32'h2a001c5b; // 0x01d4
8'h76 : RDATA <= 32'h2104d1f5; // 0x01d8
8'h77 : RDATA <= 32'h07d26842; // 0x01dc
8'h78 : RDATA <= 32'h6001d1fc; // 0x01e0
8'h79 : RDATA <= 32'hb510e7fe; // 0x01e4
8'h7a : RDATA <= 32'h21d0481e; // 0x01e8
8'h7b : RDATA <= 32'h21016101; // 0x01ec
8'h7c : RDATA <= 32'h4a1d6081; // 0x01f0
8'h7d : RDATA <= 32'h61912120; // 0x01f4
8'h7e : RDATA <= 32'h781aa326; // 0x01f8
8'h7f : RDATA <= 32'hd0062a00; // 0x01fc
8'h80 : RDATA <= 32'h07c96841; // 0x0200
8'h81 : RDATA <= 32'h6002d1fc; // 0x0204
8'h82 : RDATA <= 32'h2a001c5b; // 0x0208
8'h83 : RDATA <= 32'ha329d1f5; // 0x020c
8'h84 : RDATA <= 32'h2a00781a; // 0x0210
8'h85 : RDATA <= 32'h6841d006; // 0x0214
8'h86 : RDATA <= 32'hd1fc07c9; // 0x0218
8'h87 : RDATA <= 32'h1c5b6002; // 0x021c
8'h88 : RDATA <= 32'hd1f52a00; // 0x0220
8'h89 : RDATA <= 32'h680a4911; // 0x0224
8'h8a : RDATA <= 32'hd0092a00; // 0x0228
8'h8b : RDATA <= 32'h60082000; // 0x022c
8'h8c : RDATA <= 32'h8f4ff3bf; // 0x0230
8'h8d : RDATA <= 32'h8f6ff3bf; // 0x0234
8'h8e : RDATA <= 32'hff94f7ff; // 0x0238
8'h8f : RDATA <= 32'hbd102000; // 0x023c
8'h90 : RDATA <= 32'h781aa30b; // 0x0240
8'h91 : RDATA <= 32'hd0062a00; // 0x0244
8'h92 : RDATA <= 32'h07c96841; // 0x0248
8'h93 : RDATA <= 32'h6002d1fc; // 0x024c
8'h94 : RDATA <= 32'h2a001c5b; // 0x0250
8'h95 : RDATA <= 32'h2204d1f5; // 0x0254
8'h96 : RDATA <= 32'h07c96841; // 0x0258
8'h97 : RDATA <= 32'h6002d1fc; // 0x025c
8'h98 : RDATA <= 32'h0000e7fe; // 0x0260
8'h99 : RDATA <= 32'h4000e000; // 0x0264
8'h9a : RDATA <= 32'h40011000; // 0x0268
8'h9b : RDATA <= 32'h4001f000; // 0x026c
8'h9c : RDATA <= 32'h7245202d; // 0x0270
8'h9d : RDATA <= 32'h3a726f72; // 0x0274
8'h9e : RDATA <= 32'h4d455220; // 0x0278
8'h9f : RDATA <= 32'h69205041; // 0x027c
8'ha0 : RDATA <= 32'h6c612073; // 0x0280
8'ha1 : RDATA <= 32'h64616572; // 0x0284
8'ha2 : RDATA <= 32'h6c632079; // 0x0288
8'ha3 : RDATA <= 32'h0a726165; // 0x028c
8'ha4 : RDATA <= 32'h00000000; // 0x0290
8'ha5 : RDATA <= 32'h434f530a; // 0x0294
8'ha6 : RDATA <= 32'h5342414c; // 0x0298
8'ha7 : RDATA <= 32'h5241203a; // 0x029c
8'ha8 : RDATA <= 32'h6f43204d; // 0x02a0
8'ha9 : RDATA <= 32'h78657472; // 0x02a4
8'haa : RDATA <= 32'h20304d2d; // 0x02a8
8'hab : RDATA <= 32'h0a4b4453; // 0x02ac
8'hac : RDATA <= 32'h00000000; // 0x02b0
8'had : RDATA <= 32'h6c202d20; // 0x02b4
8'hae : RDATA <= 32'h2064616f; // 0x02b8
8'haf : RDATA <= 32'h73616c66; // 0x02bc
8'hb0 : RDATA <= 32'h000a0a68; // 0x02c0
8'hb1 : RDATA <= 32'h48034904; // 0x02c4
8'hb2 : RDATA <= 32'h47706008; // 0x02c8
8'hb3 : RDATA <= 32'h48014902; // 0x02cc
8'hb4 : RDATA <= 32'h47706008; // 0x02d0
8'hb5 : RDATA <= 32'h05f5e100; // 0x02d4
8'hb6 : RDATA <= 32'h20000000; // 0x02d8
8'hb7 : RDATA <= 32'h47804807; // 0x02dc
8'hb8 : RDATA <= 32'h47004807; // 0x02e0
8'hb9 : RDATA <= 32'he7fee7fe; // 0x02e4
8'hba : RDATA <= 32'he7fee7fe; // 0x02e8
8'hbb : RDATA <= 32'he7fee7fe; // 0x02ec
8'hbc : RDATA <= 32'h49054804; // 0x02f0
8'hbd : RDATA <= 32'h4b064a05; // 0x02f4
8'hbe : RDATA <= 32'h00004770; // 0x02f8
8'hbf : RDATA <= 32'h010002cd; // 0x02fc
8'hc0 : RDATA <= 32'h010000c1; // 0x0300
8'hc1 : RDATA <= 32'h20000068; // 0x0304
8'hc2 : RDATA <= 32'h20000368; // 0x0308
8'hc3 : RDATA <= 32'h20000168; // 0x030c
8'hc4 : RDATA <= 32'h20000168; // 0x0310
8'hc5 : RDATA <= 32'h47704770; // 0x0314
8'hc6 : RDATA <= 32'h46754770; // 0x0318
8'hc7 : RDATA <= 32'hf824f000; // 0x031c
8'hc8 : RDATA <= 32'h000546ae; // 0x0320
8'hc9 : RDATA <= 32'h46534669; // 0x0324
8'hca : RDATA <= 32'h00c008c0; // 0x0328
8'hcb : RDATA <= 32'hb0184685; // 0x032c
8'hcc : RDATA <= 32'hf7ffb520; // 0x0330
8'hcd : RDATA <= 32'hbc60ffdd; // 0x0334
8'hce : RDATA <= 32'h08492700; // 0x0338
8'hcf : RDATA <= 32'h260046b6; // 0x033c
8'hd0 : RDATA <= 32'hc5c0c5c0; // 0x0340
8'hd1 : RDATA <= 32'hc5c0c5c0; // 0x0344
8'hd2 : RDATA <= 32'hc5c0c5c0; // 0x0348
8'hd3 : RDATA <= 32'hc5c0c5c0; // 0x034c
8'hd4 : RDATA <= 32'h00493d40; // 0x0350
8'hd5 : RDATA <= 32'h4770468d; // 0x0354
8'hd6 : RDATA <= 32'h4604b510; // 0x0358
8'hd7 : RDATA <= 32'h46c046c0; // 0x035c
8'hd8 : RDATA <= 32'hf7ff4620; // 0x0360
8'hd9 : RDATA <= 32'hbd10fef8; // 0x0364
8'hda : RDATA <= 32'h47704800; // 0x0368
8'hdb : RDATA <= 32'h20000004; // 0x036c
8'hdc : RDATA <= 32'h20184901; // 0x0370
8'hdd : RDATA <= 32'he7febeab; // 0x0374
8'hde : RDATA <= 32'h00020026; // 0x0378
8'hdf : RDATA <= 32'h00004770; // 0x037c
8'he0 : RDATA <= 32'h010003a0; // 0x0380
8'he1 : RDATA <= 32'h20000000; // 0x0384
8'he2 : RDATA <= 32'h00000004; // 0x0388
8'he3 : RDATA <= 32'h01000104; // 0x038c
8'he4 : RDATA <= 32'h010003a4; // 0x0390
8'he5 : RDATA <= 32'h20000004; // 0x0394
8'he6 : RDATA <= 32'h00000364; // 0x0398
8'he7 : RDATA <= 32'h01000120; // 0x039c
8'he8 : RDATA <= 32'h05f5e100; // 0x03a0
8'he9 : RDATA <= 32'h00000000; // 0x03a4
8'hea : RDATA <= 32'h00000000; // 0x03a8
8'heb : RDATA <= 32'h00000000; // 0x03ac
8'hec : RDATA <= 32'h00000000; // 0x03b0
8'hed : RDATA <= 32'h00000000; // 0x03b4
8'hee : RDATA <= 32'h00000000; // 0x03b8
8'hef : RDATA <= 32'h00000000; // 0x03bc
8'hf0 : RDATA <= 32'h00000000; // 0x03c0
8'hf1 : RDATA <= 32'h00000000; // 0x03c4
8'hf2 : RDATA <= 32'h00000000; // 0x03c8
8'hf3 : RDATA <= 32'h00000000; // 0x03cc
8'hf4 : RDATA <= 32'h00000000; // 0x03d0
8'hf5 : RDATA <= 32'h00000000; // 0x03d4
8'hf6 : RDATA <= 32'h00000000; // 0x03d8
8'hf7 : RDATA <= 32'h00000000; // 0x03dc
8'hf8 : RDATA <= 32'h00000000; // 0x03e0
8'hf9 : RDATA <= 32'h00000000; // 0x03e4
8'hfa : RDATA <= 32'h00000000; // 0x03e8
8'hfb : RDATA <= 32'h00000000; // 0x03ec
8'h5c : RDATA <= 32'h48512141; // 0x0170
8'h5d : RDATA <= 32'h61010149; // 0x0174
8'h5e : RDATA <= 32'h60812101; // 0x0178
8'h5f : RDATA <= 32'h6081484f; // 0x017c
8'h60 : RDATA <= 32'h2020494f; // 0x0180
8'h61 : RDATA <= 32'h47706188; // 0x0184
8'h62 : RDATA <= 32'h684a494b; // 0x0188
8'h63 : RDATA <= 32'hd1fc07d2; // 0x018c
8'h64 : RDATA <= 32'h494a6008; // 0x0190
8'h65 : RDATA <= 32'h07d2684a; // 0x0194
8'h66 : RDATA <= 32'h6008d1fc; // 0x0198
8'h67 : RDATA <= 32'hb4104770; // 0x019c
8'h68 : RDATA <= 32'h4a464945; // 0x01a0
8'h69 : RDATA <= 32'h2c007804; // 0x01a4
8'h6a : RDATA <= 32'h684bd00a; // 0x01a8
8'h6b : RDATA <= 32'hd1fc07db; // 0x01ac
8'h6c : RDATA <= 32'h6853600c; // 0x01b0
8'h6d : RDATA <= 32'hd1fc07db; // 0x01b4
8'h6e : RDATA <= 32'h1c406014; // 0x01b8
8'h6f : RDATA <= 32'hd1f12c00; // 0x01bc
8'h70 : RDATA <= 32'h4770bc10; // 0x01c0
8'h71 : RDATA <= 32'h483fb510; // 0x01c4
8'h72 : RDATA <= 32'h29006801; // 0x01c8
8'h73 : RDATA <= 32'h2100d008; // 0x01cc
8'h74 : RDATA <= 32'hf3bf6001; // 0x01d0
8'h75 : RDATA <= 32'hf3bf8f4f; // 0x01d4
8'h76 : RDATA <= 32'hf7ff8f6f; // 0x01d8
8'h77 : RDATA <= 32'hbd10ffc3; // 0x01dc
8'h78 : RDATA <= 32'h49364835; // 0x01e0
8'h79 : RDATA <= 32'h7823a438; // 0x01e4
8'h7a : RDATA <= 32'hd00a2b00; // 0x01e8
8'h7b : RDATA <= 32'h07d26842; // 0x01ec
8'h7c : RDATA <= 32'h6003d1fc; // 0x01f0
8'h7d : RDATA <= 32'h07d2684a; // 0x01f4
8'h7e : RDATA <= 32'h600bd1fc; // 0x01f8
8'h7f : RDATA <= 32'h2b001c64; // 0x01fc
8'h80 : RDATA <= 32'h2204d1f1; // 0x0200
8'h81 : RDATA <= 32'h07db6843; // 0x0204
8'h82 : RDATA <= 32'h6002d1fc; // 0x0208
8'h83 : RDATA <= 32'h07c06848; // 0x020c
8'h84 : RDATA <= 32'h600ad1fc; // 0x0210
8'h85 : RDATA <= 32'hb510e7fe; // 0x0214
8'h86 : RDATA <= 32'h48272141; // 0x0218
8'h87 : RDATA <= 32'h61010149; // 0x021c
8'h88 : RDATA <= 32'h60822201; // 0x0220
8'h89 : RDATA <= 32'h608a4925; // 0x0224
8'h8a : RDATA <= 32'h22204b25; // 0x0228
8'h8b : RDATA <= 32'ha42c619a; // 0x022c
8'h8c : RDATA <= 32'h2b007823; // 0x0230
8'h8d : RDATA <= 32'h6842d00a; // 0x0234
8'h8e : RDATA <= 32'hd1fc07d2; // 0x0238
8'h8f : RDATA <= 32'h684a6003; // 0x023c
8'h90 : RDATA <= 32'hd1fc07d2; // 0x0240
8'h91 : RDATA <= 32'h1c64600b; // 0x0244
8'h92 : RDATA <= 32'hd1f12b00; // 0x0248
8'h93 : RDATA <= 32'h7823a42c; // 0x024c
8'h94 : RDATA <= 32'hd00a2b00; // 0x0250
8'h95 : RDATA <= 32'h07d26842; // 0x0254
8'h96 : RDATA <= 32'h6003d1fc; // 0x0258
8'h97 : RDATA <= 32'h07d2684a; // 0x025c
8'h98 : RDATA <= 32'h600bd1fc; // 0x0260
8'h99 : RDATA <= 32'h2b001c64; // 0x0264
8'h9a : RDATA <= 32'h4a16d1f1; // 0x0268
8'h9b : RDATA <= 32'h2b006813; // 0x026c
8'h9c : RDATA <= 32'h2000d009; // 0x0270
8'h9d : RDATA <= 32'hf3bf6010; // 0x0274
8'h9e : RDATA <= 32'hf3bf8f4f; // 0x0278
8'h9f : RDATA <= 32'hf7ff8f6f; // 0x027c
8'ha0 : RDATA <= 32'h2000ff71; // 0x0280
8'ha1 : RDATA <= 32'ha410bd10; // 0x0284
8'ha2 : RDATA <= 32'h2b007823; // 0x0288
8'ha3 : RDATA <= 32'h6842d00a; // 0x028c
8'ha4 : RDATA <= 32'hd1fc07d2; // 0x0290
8'ha5 : RDATA <= 32'h684a6003; // 0x0294
8'ha6 : RDATA <= 32'hd1fc07d2; // 0x0298
8'ha7 : RDATA <= 32'h1c64600b; // 0x029c
8'ha8 : RDATA <= 32'hd1f12b00; // 0x02a0
8'ha9 : RDATA <= 32'h68432204; // 0x02a4
8'haa : RDATA <= 32'hd1fc07db; // 0x02a8
8'hab : RDATA <= 32'h68486002; // 0x02ac
8'hac : RDATA <= 32'hd1fc07c0; // 0x02b0
8'had : RDATA <= 32'he7fe600a; // 0x02b4
8'hae : RDATA <= 32'h40006000; // 0x02b8
8'haf : RDATA <= 32'h4000e000; // 0x02bc
8'hb0 : RDATA <= 32'h40011000; // 0x02c0
8'hb1 : RDATA <= 32'h4001f000; // 0x02c4
8'hb2 : RDATA <= 32'h7245202d; // 0x02c8
8'hb3 : RDATA <= 32'h3a726f72; // 0x02cc
8'hb4 : RDATA <= 32'h4d455220; // 0x02d0
8'hb5 : RDATA <= 32'h63205041; // 0x02d4
8'hb6 : RDATA <= 32'h7261656c; // 0x02d8
8'hb7 : RDATA <= 32'h000a6465; // 0x02dc
8'hb8 : RDATA <= 32'h434f530a; // 0x02e0
8'hb9 : RDATA <= 32'h5342414c; // 0x02e4
8'hba : RDATA <= 32'h5241203a; // 0x02e8
8'hbb : RDATA <= 32'h6f43204d; // 0x02ec
8'hbc : RDATA <= 32'h78657472; // 0x02f0
8'hbd : RDATA <= 32'h20304d2d; // 0x02f4
8'hbe : RDATA <= 32'h0a4b4453; // 0x02f8
8'hbf : RDATA <= 32'h00000000; // 0x02fc
8'hc0 : RDATA <= 32'h6c202d20; // 0x0300
8'hc1 : RDATA <= 32'h2064616f; // 0x0304
8'hc2 : RDATA <= 32'h73616c66; // 0x0308
8'hc3 : RDATA <= 32'h000a0a68; // 0x030c
8'hc4 : RDATA <= 32'h48034904; // 0x0310
8'hc5 : RDATA <= 32'h47706008; // 0x0314
8'hc6 : RDATA <= 32'h48014902; // 0x0318
8'hc7 : RDATA <= 32'h47706008; // 0x031c
8'hc8 : RDATA <= 32'h05f5e100; // 0x0320
8'hc9 : RDATA <= 32'h20000000; // 0x0324
8'hca : RDATA <= 32'h47804807; // 0x0328
8'hcb : RDATA <= 32'h47004807; // 0x032c
8'hcc : RDATA <= 32'he7fee7fe; // 0x0330
8'hcd : RDATA <= 32'he7fee7fe; // 0x0334
8'hce : RDATA <= 32'he7fee7fe; // 0x0338
8'hcf : RDATA <= 32'h49054804; // 0x033c
8'hd0 : RDATA <= 32'h4b064a05; // 0x0340
8'hd1 : RDATA <= 32'h00004770; // 0x0344
8'hd2 : RDATA <= 32'h01000319; // 0x0348
8'hd3 : RDATA <= 32'h010000c1; // 0x034c
8'hd4 : RDATA <= 32'h20000068; // 0x0350
8'hd5 : RDATA <= 32'h20000368; // 0x0354
8'hd6 : RDATA <= 32'h20000168; // 0x0358
8'hd7 : RDATA <= 32'h20000168; // 0x035c
8'hd8 : RDATA <= 32'h47704770; // 0x0360
8'hd9 : RDATA <= 32'h46754770; // 0x0364
8'hda : RDATA <= 32'hf824f000; // 0x0368
8'hdb : RDATA <= 32'h000546ae; // 0x036c
8'hdc : RDATA <= 32'h46534669; // 0x0370
8'hdd : RDATA <= 32'h00c008c0; // 0x0374
8'hde : RDATA <= 32'hb0184685; // 0x0378
8'hdf : RDATA <= 32'hf7ffb520; // 0x037c
8'he0 : RDATA <= 32'hbc60ffdd; // 0x0380
8'he1 : RDATA <= 32'h08492700; // 0x0384
8'he2 : RDATA <= 32'h260046b6; // 0x0388
8'he3 : RDATA <= 32'hc5c0c5c0; // 0x038c
8'he4 : RDATA <= 32'hc5c0c5c0; // 0x0390
8'he5 : RDATA <= 32'hc5c0c5c0; // 0x0394
8'he6 : RDATA <= 32'hc5c0c5c0; // 0x0398
8'he7 : RDATA <= 32'h00493d40; // 0x039c
8'he8 : RDATA <= 32'h4770468d; // 0x03a0
8'he9 : RDATA <= 32'h4604b510; // 0x03a4
8'hea : RDATA <= 32'h46c046c0; // 0x03a8
8'heb : RDATA <= 32'hf7ff4620; // 0x03ac
8'hec : RDATA <= 32'hbd10fed2; // 0x03b0
8'hed : RDATA <= 32'h47704800; // 0x03b4
8'hee : RDATA <= 32'h20000004; // 0x03b8
8'hef : RDATA <= 32'h20184901; // 0x03bc
8'hf0 : RDATA <= 32'he7febeab; // 0x03c0
8'hf1 : RDATA <= 32'h00020026; // 0x03c4
8'hf2 : RDATA <= 32'h00004770; // 0x03c8
8'hf3 : RDATA <= 32'h010003ec; // 0x03cc
8'hf4 : RDATA <= 32'h20000000; // 0x03d0
8'hf5 : RDATA <= 32'h00000004; // 0x03d4
8'hf6 : RDATA <= 32'h01000104; // 0x03d8
8'hf7 : RDATA <= 32'h010003f0; // 0x03dc
8'hf8 : RDATA <= 32'h20000004; // 0x03e0
8'hf9 : RDATA <= 32'h00000364; // 0x03e4
8'hfa : RDATA <= 32'h01000120; // 0x03e8
8'hfb : RDATA <= 32'h05f5e100; // 0x03ec
8'hfc : RDATA <= 32'h00000000; // 0x03f0
8'hfd : RDATA <= 32'h00000000; // 0x03f4
8'hfe : RDATA <= 32'h00000000; // 0x03f8
......
Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_clkreset.v
+ 2
− 2
View file @ c5e46524
......@@ -34,12 +34,12 @@ module cmsdk_clkreset(
initial
begin
#10 clock_q <= 1'b1;
#40 clock_q <= 1'b1;
#100 reset_n_q <= 1'b1;
end
always @(clock_q)
#10 clock_q <= ~clock_q;
#25 clock_q <= ~clock_q;
assign CLK = clock_q;
assign NRST = reset_n_q;
......
Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_chip.v
+ 89
− 416
View file @ c5e46524
......@@ -6,7 +6,7 @@
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Copyright 2021-2, SoC Labs (www.soclabs.org)
// Copyright � 2021-2, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
......@@ -97,41 +97,52 @@ module cmsdk_mcu_chip #(
inout wire VDD,
inout wire VSS,
`endif
/// input wire XTAL1, // input
inout wire XTAL1, // input
inout wire XTAL2, // output
/// input wire NRST, // active low reset
inout wire NRST, // active low reset
inout wire [15:0] P0,
inout wire [15:0] P1,
input wire xtal_clk_i,
output wire xtal_clk_o,
input wire nrst_i,
input wire [15:0] p0_i, // level-shifted input from pad
output wire [15:0] p0_o, // output port drive
output wire [15:0] p0_e, // active high output drive enable (pad tech dependent)
output wire [15:0] p0_z, // active low output drive enable (pad tech dependent)
input wire [15:0] p1_i, // level-shifted input from pad
output wire [15:0] p1_o, // output port drive
output wire [15:0] p1_e, // active high output drive enable (pad tech dependent)
output wire [15:0] p1_z, // active low output drive enable (pad tech dependent)
`ifdef ARM_CMSDK_INCLUDE_JTAG
input wire nTRST,
input wire TDI,
output wire TDO,
input wire ntrst_i,
input wire tdi_i,
output wire tdo_o,
`endif
inout wire SWDIOTMS,
/// input wire SWCLKTCK);
inout wire SWCLKTCK);
input wire swdio_i,
output wire swdio_o,
output wire swdio_e,
output wire swdio_z,
input wire swdclk_i
);
//------------------------------------
// internal wires
// CMSDK internal wire naming preserved
wire xtal_clk_in;
wire xtal_clk_in = xtal_clk_i;
wire xtal_clk_out;
wire nrst_in;
wire [15:0] p0_in; // level-shifted input from pad
wire [15:0] p0_out; // output port drive
wire [15:0] p0_out_en; // active high output drive enable (pad tech dependent)
wire [15:0] p0_out_nen; // active low output drive enable (pad tech dependent)
wire [15:0] p1_in; // level-shifted input from pad
wire [15:0] p1_out; // output port drive
wire [15:0] p1_out_en; // active high output drive enable (pad tech dependent)
wire [15:0] p1_out_nen; // active low output drive enable (pad tech dependent)
wire [15:0] p1_out_mux; // output port drive
wire [15:0] p1_out_en_mux; // active high output drive enable (pad tech dependent)
wire [15:0] p1_out_nen_mux; // active low output drive enable (pad tech dependent)
assign xtal_clk_o = xtal_clk_out;
wire nrst_in = nrst_i;
wire [15:0] p0_in; // level-shifted input from pad
wire [15:0] p0_out; // output port drive
wire [15:0] p0_out_en; // active high output drive enable (pad tech dependent)
wire [15:0] p0_out_nen; // active low output drive enable (pad tech dependent)
wire [15:0] p1_in; // level-shifted input from pad
wire [15:0] p1_out; // output port drive
wire [15:0] p1_out_en; // active high output drive enable (pad tech dependent)
wire [15:0] p1_out_nen; // active low output drive enable (pad tech dependent)
wire [15:0] p1_in_mux; // level-shifted input from pad
wire [15:0] p1_out_mux; // output port drive
wire [15:0] p1_out_en_mux; // active high output drive enable (pad tech dependent)
wire [15:0] p1_out_nen_mux; // active low output drive enable (pad tech dependent)
`ifdef ARM_CMSDK_INCLUDE_JTAG
wire ntrst_in;
......@@ -144,408 +155,67 @@ module cmsdk_mcu_chip #(
wire swdio_out_nen;
wire swdclk_in;
wire ft_clk_o ;
wire ft_ssn_o ;
wire ft_miso_i;
wire ft_miosio_o;
wire ft_miosio_e;
wire ft_miosio_z;
wire ft_miosio_i;
wire ADPRESETREQ;
/*
cmsdk_mcu_core
#(.CLKGATE_PRESENT (CLKGATE_PRESENT),
.BE (BE),
.BKPT (BKPT), // Number of breakpoint comparators
.DBG (DBG), // Debug configuration
.NUMIRQ (NUMIRQ), // NUMIRQ
.SMUL (SMUL), // Multiplier configuration
.SYST (SYST), // SysTick
.WIC (WIC), // Wake-up interrupt controller support
.WICLINES (WICLINES), // Supported WIC lines
`ifdef CORTEX_M0PLUS
.AWIDTH (AWIDTH), // Micro Trace Buffer SRAM address width
.BASEADDR (BASEADDR), // ROM Table Base Address
.HWF (HWF), // Half Word Fetching
.IOP (IOP), // IO Port interface selected
.IRQDIS (IRQDIS), // Interrupt Disable
.MPU (MPU), // Memory Protection support
.MTB (MTB), // MTB select
.USER (USER), // User/Privilege
.VTOR (VTOR), // Vector Table Offset support
`endif
.WPT (WPT), // Number of DWT comparators
.RESET_ALL_REGS (RESET_ALL_REGS), // Do not reset all registers
.BOOT_MEM_TYPE (BOOT_MEM_TYPE), // Boot loader memory type
.ROM_MEM_TYPE (ROM_MEM_TYPE), // ROM memory type
.RAM_MEM_TYPE (RAM_MEM_TYPE), // RAM loader memory type
.INCLUDE_BITBAND (INCLUDE_BITBAND), // Include bit band wrapper
.INCLUDE_DMA (INCLUDE_DMA), // Include DMA feature
.INCLUDE_JTAG (INCLUDE_JTAG) // Include JTAG feature
)
u_cmsdk_mcu_core (
`ifdef POWER_PINS
.VDDIO (VDDIO),
.VSSIO (VSSIO),
.VDD (VDD),
.VSS (VSS),
`endif
.clk (xtal_clk_in), // primary clock
.clk_out (xtal_clk_out), // inverted clock out
.nrst (nrst_in) // primary reset (active-low)
.p0_in (p0_in ), // level-shifted input from pad
.p0_out (p0_out ), // output port drive
.p0_out_en (p0_out_en ), // active high output drive enable (pad tech dependent)
.p0_out_nen (p0_out_nen), // active low output drive enable (pad tech dependent)
.p1_in (p1_in ), // level-shifted input from pad
.p1_out_mux (p1_out ), // output port drive
.p1_out_en_mux (p1_out_en ), // active high output drive enable (pad tech dependent)
.p1_out_nen_mux (p1_out_nen), // active low output drive enable (pad tech dependent)
`ifdef ARM_CMSDK_INCLUDE_JTAG
.ntrst (ntrst_in), // JTAG reset (active-low)
.tdi (tdi_in), // JTAG reset (active-low)
.tdo (tdo_out), // inverted clock out
`endif
.swdio_in (swdio_in), // Serial Wire Debug IO input
.swdio_out (swdio_out), // Serial Wire Debug IO output
.swdio_out_en (swdio_out_en), // Serial Wire Debug IO output drive enable (active high)
.swdio_out_nen (swdio_out_nen), // Serial Wire Debug IO output drive enable (active low)
.swdclk (swdclk_in) // Serial Wire Debug clock input
);
*/
//TIE_HI uTIEHI (.tiehi(tiehi));
wire tiehi = 1'b1;
//TIE_LO uTIELO (.tielo(tielo));
wire tielo = 1'b0;
wire ft_clk_o;
wire ft_ssn_o;
wire ft_miso_i;
wire ft_miosio_o;
wire ft_miosio_e;
wire ft_miosio_z;
wire ft_miosio_i;
// --------------------------------------------------------------------------------
// IO pad (GLIB Generic Library napping)
// Port-0 IO pad driver mapping
// --------------------------------------------------------------------------------
`ifdef POWER_PINS
// Pad IO power supplies
PAD_VDDIO uPAD_VDDIO_1(
.PAD(VDDIO)
);
PAD_VSSIO uPAD_VSSIO_1(
.PAD(VSSIO)
);
// Core power supplies
PAD_VDDSOC uPAD_VDD_1(
.PAD(VDD)
);
PAD_VSS uPAD_VSS_1(
.PAD(VSS)
);
`endif
// Clock, Reset and Serial Wire Debug ports
PAD_INOUT8MA_NOE uPAD_XTAL_I (
.PAD (XTAL1),
.O (tielo),
.I (xtal_clk_in),
.NOE (tiehi)
);
PAD_INOUT8MA_NOE uPAD_XTAL_O (
.PAD (XTAL2),
.O (xtal_clk_out),
.I ( ),
.NOE (tielo)
);
PAD_INOUT8MA_NOE uPAD_NRST_I (
.PAD (NRST),
.O (tielo),
.I (nrst_in),
.NOE (tiehi)
);
PAD_INOUT8MA_NOE uPAD_SWDIO_I (
.PAD (SWDIOTMS),
.O (swdio_out),
.I (swdio_in),
.NOE (swdio_out_nen)
);
PAD_INOUT8MA_NOE uPAD_SWDCLK_I (
.PAD (SWCLKTCK),
.O (tielo),
.I (swdclk_in),
.NOE (tiehi)
);
// GPI.I Port 0 x 16
PAD_INOUT8MA_NOE uPAD_P0_00 (
.PAD (P0[00]),
.O (p0_out[00]),
.I (p0_in[00]),
.NOE (p0_out_nen[00])
);
PAD_INOUT8MA_NOE uPAD_P0_01 (
.PAD (P0[01]),
.O (p0_out[01]),
.I (p0_in[01]),
.NOE (p0_out_nen[01])
);
PAD_INOUT8MA_NOE uPAD_P0_02 (
.PAD (P0[02]),
.O (p0_out[02]),
.I (p0_in[02]),
.NOE (p0_out_nen[02])
);
PAD_INOUT8MA_NOE uPAD_P0_03 (
.PAD (P0[03]),
.O (p0_out[03]),
.I (p0_in[03]),
.NOE (p0_out_nen[03])
);
PAD_INOUT8MA_NOE uPAD_P0_04 (
.PAD (P0[04]),
.O (p0_out[04]),
.I (p0_in[04]),
.NOE (p0_out_nen[04])
);
PAD_INOUT8MA_NOE uPAD_P0_05 (
.PAD (P0[05]),
.O (p0_out[05]),
.I (p0_in[05]),
.NOE (p0_out_nen[05])
);
PAD_INOUT8MA_NOE uPAD_P0_06 (
.PAD (P0[06]),
.O (p0_out[06]),
.I (p0_in[06]),
.NOE (p0_out_nen[06])
);
PAD_INOUT8MA_NOE uPAD_P0_07 (
.PAD (P0[07]),
.O (p0_out[07]),
.I (p0_in[07]),
.NOE (p0_out_nen[07])
);
PAD_INOUT8MA_NOE uPAD_P0_08 (
.PAD (P0[08]),
.O (p0_out[08]),
.I (p0_in[08]),
.NOE (p0_out_nen[08])
);
PAD_INOUT8MA_NOE uPAD_P0_09 (
.PAD (P0[09]),
.O (p0_out[09]),
.I (p0_in[09]),
.NOE (p0_out_nen[09])
);
PAD_INOUT8MA_NOE uPAD_P0_10 (
.PAD (P0[10]),
.O (p0_out[10]),
.I (p0_in[10]),
.NOE (p0_out_nen[10])
);
PAD_INOUT8MA_NOE uPAD_P0_11 (
.PAD (P0[11]),
.O (p0_out[11]),
.I (p0_in[11]),
.NOE (p0_out_nen[11])
);
PAD_INOUT8MA_NOE uPAD_P0_12 (
.PAD (P0[12]),
.O (p0_out[12]),
.I (p0_in[12]),
.NOE (p0_out_nen[12])
);
PAD_INOUT8MA_NOE uPAD_P0_13 (
.PAD (P0[13]),
.O (p0_out[13]),
.I (p0_in[13]),
.NOE (p0_out_nen[13])
);
PAD_INOUT8MA_NOE uPAD_P0_14 (
.PAD (P0[14]),
.O (p0_out[14]),
.I (p0_in[14]),
.NOE (p0_out_nen[14])
);
assign p0_in = p0_i; // level-shifted input from pad
assign p0_o = p0_out; // output port drive
assign p0_e = p0_out_en; // active high output drive enable (pad tech dependent)
assign p0_z = p0_out_nen; // active low output drive enable (pad tech dependent)
PAD_INOUT8MA_NOE uPAD_P0_15 (
.PAD (P0[15]),
.O (p0_out[15]),
.I (p0_in[15]),
.NOE (p0_out_nen[15])
);
// GPI.I Port 1 x 16
/*
PAD_INOUT8MA_NOE uPAD_P1_00 (
.PAD (P1[00]),
.O (p1_out_mux[00]),
.I (p1_in[00]),
.NOE (p1_out_nen_mux[00])
);
PAD_INOUT8MA_NOE uPAD_P1_01 (
.PAD (P1[01]),
.O (p1_out_mux[01]),
.I (p1_in[01]),
.NOE (p1_out_nen_mux[01])
);
PAD_INOUT8MA_NOE uPAD_P1_02 (
.PAD (P1[02]),
.O (p1_out_mux[02]),
.I (p1_in[02]),
.NOE (p1_out_nen_mux[02])
);
PAD_INOUT8MA_NOE uPAD_P1_03 (
.PAD (P1[03]),
.O (p1_out_mux[03]),
.I (p1_in[03]),
.NOE (p1_out_nen_mux[03])
);
*/
PAD_INOUT8MA_NOE uPAD_P1_00 (
.PAD (P1[00]),
.O (1'b0), //p1_out[00]),
.I (ft_miso_i), //p1_in[00]),
.NOE (1'b1) //p1_out_nen[00])
);
assign p1_in[00] = ft_miso_i;
PAD_INOUT8MA_NOE uPAD_P1_01 (
.PAD (P1[01]),
.O (ft_clk_o ), //p1_out[01]),
.I (p1_in[01]),
.NOE (1'b0) //p1_out_nen[01])
);
PAD_INOUT8MA_NOE uPAD_P1_02 (
.PAD (P1[02]),
.O (ft_miosio_o), //p1_out[02]),
.I (ft_miosio_i), //p1_in[02]),
.NOE (ft_miosio_z) //p1_out_nen[02])
);
assign p1_in[02] = ft_miosio_i;
PAD_INOUT8MA_NOE uPAD_P1_03 (
.PAD (P1[03]),
.O (ft_ssn_o),
.I (p1_in[03]),
.NOE (1'b0)
);
// --------------------------------------------------------------------------------
// Port-1 IO pad driver mapping
// --------------------------------------------------------------------------------
// modify p1_mux [3:0] for ft1248 interface
// assign p1_in_mux[3:0] = p1_i[3:0]; // IO MUX controlled bidirectionals
// assign p1_o[3:0] = p1_out_mux[3:0];
// assign p1_e[3:0] = p1_out_en_mux[3:0];
// assign p1_z[3:0] = p1_out_nen_mux[3:0];
assign ft_miso_i = p1_i[0]; // FT_MISO INPUT pad configuration
assign p1_in_mux[0] = p1_i[0];
assign p1_o[0] = 1'b0;
assign p1_e[0] = 1'b0;
assign p1_z[0] = 1'b1;
PAD_INOUT8MA_NOE uPAD_P1_04 (
.PAD (P1[04]),
.O (p1_out_mux[04]),
.I (p1_in[04]),
.NOE (p1_out_nen_mux[04])
);
assign p1_in_mux[1] = p1_i[1]; // FT_CLK OUTPUT pad configuration
assign p1_o[1] = ft_clk_o;
assign p1_e[1] = 1'b1;
assign p1_z[1] = 1'b0;
PAD_INOUT8MA_NOE uPAD_P1_05 (
.PAD (P1[05]),
.O (p1_out_mux[05]),
.I (p1_in[05]),
.NOE (p1_out_nen_mux[05])
);
PAD_INOUT8MA_NOE uPAD_P1_06 (
.PAD (P1[06]),
.O (p1_out_mux[06]),
.I (p1_in[06]),
.NOE (p1_out_nen_mux[06])
);
assign ft_miosio_i = p1_i[2]; // FT_MIOSIO INOUT pad configuration
assign p1_in_mux[2] = p1_i[2];
assign p1_o[2] = ft_miosio_o;
assign p1_e[2] = ft_miosio_e;
assign p1_z[2] = ft_miosio_z;
PAD_INOUT8MA_NOE uPAD_P1_07 (
.PAD (P1[07]),
.O (p1_out_mux[07]),
.I (p1_in[07]),
.NOE (p1_out_nen_mux[07])
);
PAD_INOUT8MA_NOE uPAD_P1_08 (
.PAD (P1[08]),
.O (p1_out_mux[08]),
.I (p1_in[08]),
.NOE (p1_out_nen_mux[08])
);
assign p1_in_mux[3] = p1_i[3]; // FT_SSN OUTPUT pad configuration
assign p1_o[3] = ft_ssn_o;
assign p1_e[3] = 1'b1;
assign p1_z[3] = 1'b0;
PAD_INOUT8MA_NOE uPAD_P1_09 (
.PAD (P1[09]),
.O (p1_out_mux[09]),
.I (p1_in[09]),
.NOE (p1_out_nen_mux[09])
);
PAD_INOUT8MA_NOE uPAD_P1_10 (
.PAD (P1[10]),
.O (p1_out_mux[10]),
.I (p1_in[10]),
.NOE (p1_out_nen_mux[10])
);
assign p1_in_mux[15:4] = p1_i[15:4]; // IO MUX controlled bidirectionals
assign p1_o[15:4] = p1_out_mux[15:4];
assign p1_e[15:4] = p1_out_en_mux[15:4];
assign p1_z[15:4] = p1_out_nen_mux[15:4];
PAD_INOUT8MA_NOE uPAD_P1_11 (
.PAD (P1[11]),
.O (p1_out_mux[11]),
.I (p1_in[11]),
.NOE (p1_out_nen_mux[11])
);
PAD_INOUT8MA_NOE uPAD_P1_12 (
.PAD (P1[12]),
.O (p1_out_mux[12]),
.I (p1_in[12]),
.NOE (p1_out_nen_mux[12])
);
PAD_INOUT8MA_NOE uPAD_P1_13 (
.PAD (P1[13]),
.O (p1_out_mux[13]),
.I (p1_in[13]),
.NOE (p1_out_nen_mux[13])
);
PAD_INOUT8MA_NOE uPAD_P1_14 (
.PAD (P1[14]),
.O (p1_out_mux[14]),
.I (p1_in[14]),
.NOE (p1_out_nen_mux[14])
);
//TIE_HI uTIEHI (.tiehi(tiehi));
wire tiehi = 1'b1;
//TIE_LO uTIELO (.tielo(tielo));
wire tielo = 1'b0;
PAD_INOUT8MA_NOE uPAD_P1_15 (
.PAD (P1[15]),
.O (p1_out_mux[15]),
.I (p1_in[15]),
.NOE (p1_out_nen_mux[15])
);
//------------------------------------
// internal wires
......@@ -567,6 +237,9 @@ PAD_INOUT8MA_NOE uPAD_P1_15 (
wire PMUENABLE;
wire SLEEPDEEP;
wire ADPRESETREQ;
`ifdef CORTEX_M0DESIGNSTART
// if using DesignStart CortexM0, remove these signals
......
Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tb_cmsdk_mcu.v
+ 9
− 10
View file @ c5e46524
......@@ -193,8 +193,7 @@ SROM_Ax32
// Cortex-M0/Cortex-M0+ Microcontroller
// --------------------------------------------------------------------------------
cmsdk_mcu_chip
// cmsdk_mcu
cmsdk_mcu_chip_pads
#(.CLKGATE_PRESENT (CLKGATE_PRESENT),
.BE (BE),
.BKPT (BKPT), // Number of breakpoint comparators
......@@ -293,7 +292,7 @@ SROM_Ax32
// --------------------------------------------------------------------------------
`ifdef ARM_CMSDK_SLOWSPEED_PCLK
// If PCLK is running at slower speed, the UART output will also be slower
assign PCLK = u_cmsdk_mcu.PCLK;
assign PCLK = u_cmsdk_mcu.u_cmsdk_mcu.PCLK;
`else
assign PCLK = XTAL1;
`endif
......@@ -302,22 +301,22 @@ SROM_Ax32
// external UART phase lock to (known) baud rate
// seem unable to use the following (due to generate instance naming?)
// wire baudx16_clk = u_cmsdk_mcu.u_cmsdk_mcu_system.u_apb_subsystem.u_apb_uart_2.BAUDTICK;
// wire baudx16_clk = u_cmsdk_mcu.u_cmsdk_mcu.u_cmsdk_mcu_system.u_apb_subsystem.u_apb_uart_2.BAUDTICK;
// 2000000/208 = 9615 baud (+0.16%)
// 208 / 16
`define BAUDPROG 13
`define BAUDPROG 130
reg [3:0] bauddiv;
wire baudclken = (bauddiv == 4'b0000);
reg [7:0] bauddiv;
wire baudclken = (bauddiv == 8'b00000000);
always @(negedge NRST or posedge PCLK)
if (!NRST)
bauddiv <=0;
else
bauddiv <= (baudclken) ? (`BAUDPROG-1) : (bauddiv -1) ; // count down of 13
bauddiv <= (baudclken) ? (`BAUDPROG-1) : (bauddiv -1) ; // count down of BAUDPROG
wire baudx16_clk = bauddiv[3];
wire baudx16_clk = bauddiv[7]; //prefer:// !baudclken;
wire UARTXD = P1[5];
reg UARTXD_del;
......@@ -424,7 +423,7 @@ wire ft_txd2uart;
`ifdef CORTEX_M0
`ifdef USE_TARMAC
`define ARM_CM0IK_PATH u_cmsdk_mcu.u_cmsdk_mcu_system.u_cortex_m0_integration.u_cortexm0
`define ARM_CM0IK_PATH u_cmsdk_mcu.u_cmsdk_mcu.u_cmsdk_mcu_system.u_cortex_m0_integration.u_cortexm0
CORTEXM0
#(.ACG(1), .AHBSLV(0), .BE(BE), .BKPT(BKPT),
......
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