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Commit afe09bcf authored by dwf1m12's avatar dwf1m12
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new top-level fpgabuild.sh and script updates in the style of nanosoc

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#-----------------------------------------------------------------------------
# SoC Labs Simulation script for system level verification
# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
#
# Contributors
#
# David Fltnn (d.w.flynne@soton.ac.uk)
#
# Copyright 2023, SoC Labs (www.soclabs.org)
#-----------------------------------------------------------------------------
#!/usr/bin/env bash
rm -Rf .gen/
rm -Rf .srcs/
rm -Rf .Xil/
rm -Rf vivado/
rm -f *.backup.*
rm -f vivado.*
rm -Rf vivado/
rm -Rf pynq_export/*/pynq/overlays/soclabs/*
......@@ -27,7 +27,7 @@ file mkdir $outputDir
# local search path for configurations
set search_path ../verilog
set cortexm0_vlog ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical
set cortexm0_vlog ../../../../../../arm-AAA-ip/latest/Cortex-M0/logical
source scripts/rtl_source_cm0.tcl
set search_path [ concat $search_path $cortexm0_vlog/cortexm0_integration/verilog ]
......@@ -35,7 +35,7 @@ read_verilog [ glob $cortexm0_vlog/cortexm0_integration/verilog/*.v ]
read_verilog [ glob $cortexm0_vlog/models/cells/*.v ]
# Arm unmodified CMSDK RTL
set cmsdk_vlog ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0
set cmsdk_vlog ../../../../../../arm-AAA-ip/latest/Corstone-101
source scripts/rtl_source_cmsdk.tcl
set search_path [ concat $search_path $cmsdk_vlog/logical/models/memories ]
......@@ -47,7 +47,7 @@ read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_fpga_sram.v
# configured Arm DMA-PL230 RTL (include ../verilog/pl230_defs.v for local configuration, not the distribution, already on search path)
##set search_path [ concat $search_path ../verilog ]
set dma230_vlog ../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog
set dma230_vlog ../../../../../../arm-AAA-ip/latest/DMA-230/logical
source scripts/rtl_source_dma230.tcl
# ADP, FT1248 and streamio IP
......
......@@ -21,8 +21,8 @@ set project project_pynq_z2
set importDir target_fpga_pynq_z2
set ipDir ./ip_repo
set mcuDir ./vivado/built_mcu_fpga/MCULIB
set pynqDir pynq_export/pz2/pynq/overlays/soclabs
set exportDir /research/soclabs/pynq_export/pz2/pynq/overlays/soclabs
set pynqDir pynq_export/pynq_z2/pynq/overlays/soclabs
set exportDir /research/soclabs/pynq_export/pynq_z2/pynq/overlays/soclabs
#set_property BOARD_PART tul.com:pynq-z2:part0:1.1 [current_project]
#
......@@ -66,15 +66,15 @@ create_root_design ""
add_files -norecurse -scan_for_includes ../verilog/cmsdk_mcu_defs.v
set_property is_global_include true [get_files ../verilog/cmsdk_mcu_defs.v]
add_files -norecurse -scan_for_includes {../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/cmsdk_ahb_memory_models_defs.v ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v}
set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/cmsdk_ahb_memory_models_defs.v]
set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
add_files -norecurse -scan_for_includes {../../../../../../arm-AAA-ip/latest/Corstone-101/logical/models/memories/cmsdk_ahb_memory_models_defs.v ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v}
set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/models/memories/cmsdk_ahb_memory_models_defs.v]
set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/cmsdk_ahb_memory_models_defs.v]
set_property file_type {Verilog Header} [get_files ../../../../../../soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_defs.v]
set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/models/memories/cmsdk_ahb_memory_models_defs.v]
set_property file_type {Verilog Header} [get_files ../verilog/cmsdk_mcu_defs.v]
set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
add_files $importDir/fpga_pinmap.xdc
......
......@@ -21,7 +21,7 @@ set project project_pynq_zcu104
set importDir target_fpga_zcu104
set ipDir ./ip_repo
set mcuDir ./vivado/built_mcu_fpga/MCULIB
set pynqDir pynq_export/pz104/pynq/overlays/soclabs
set pynqDir pynq_export/pynq_zcu104/pynq/overlays/soclabs
#set_property BOARD_PART xilinx.com:zcu104:part0:1.1 [current_project]
#
......@@ -65,15 +65,15 @@ create_root_design ""
add_files -norecurse -scan_for_includes ../verilog/cmsdk_mcu_defs.v
set_property is_global_include true [get_files ../verilog/cmsdk_mcu_defs.v]
add_files -norecurse -scan_for_includes {../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/cmsdk_ahb_memory_models_defs.v ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v}
set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/cmsdk_ahb_memory_models_defs.v]
set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
add_files -norecurse -scan_for_includes {../../../../../../arm-AAA-ip/latest/Corstone-101/logical/models/memories/cmsdk_ahb_memory_models_defs.v ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v}
set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/models/memories/cmsdk_ahb_memory_models_defs.v]
set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/cmsdk_ahb_memory_models_defs.v]
set_property file_type {Verilog Header} [get_files ../../../../../../soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_defs.v]
set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/models/memories/cmsdk_ahb_memory_models_defs.v]
set_property file_type {Verilog Header} [get_files ../verilog/cmsdk_mcu_defs.v]
set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
add_files $importDir/fpga_pinmap.xdc
......
#-----------------------------------------------------------------------------
# SoC Labs Simulation script for system level verification
# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
#
# Contributors
#
# David Fltnn (d.w.flynne@soton.ac.uk)
#
# Copyright 2023, SoC Labs (www.soclabs.org)
#-----------------------------------------------------------------------------
#!/usr/bin/env bash
# Get simulation name from name of script
FPGA_NAME="build_fpga_"$1
# Directory to put simulation files
FPGA_DIR=$SOCLABS_PROJECT_DIR/fpga/$FPGA_NAME
# Create Directory to export fpga files
mkdir -p $FPGA_DIR
cd $ARM_CMSDK_MCU_DIR/fpga_imp
# build fpga
echo "valid targets are:"
echo " pynq_z2"
echo " pynq_zcu104"
echo " clean"
echo ">>"${1}"<<"
cd $ARM_CMSDK_MCU_DIR/fpga_imp ; source $FPGA_NAME.scr
if [ ${1} != 'clean' ]; then
cp -Rp $ARM_CMSDK_MCU_DIR/fpga_imp/pynq_export/$1/* $FPGA_DIR/
fi
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