From afe09bcf8360ed7e886bfd9407d6534a12310b68 Mon Sep 17 00:00:00 2001
From: dwf1m12 <d.w.flynn@soton.ac.uk>
Date: Mon, 24 Jul 2023 18:21:02 +0100
Subject: [PATCH] new top-level fpgabuild.sh and script updates in the style of
nanosoc
---
.../fpga_imp/build_fpga_clean.scr | 23 +++++++++++++
.../soclabs/driver/uartlite.py | 0
.../soclabs/soclabs_cm0sdk_mcu.ipynb | 0
.../soclabs/driver/uartlite.py | 0
.../soclabs/soclabs_cm0sdk_mcu.ipynb | 0
.../fpga_imp/scripts/build_mcu_fpga_ip.tcl | 6 ++--
.../scripts/build_mcu_fpga_pynq_z2.tcl | 20 +++++------
.../scripts/build_mcu_fpga_pynq_zcu104.tcl | 18 +++++-----
fpgabuild.sh | 34 +++++++++++++++++++
9 files changed, 79 insertions(+), 22 deletions(-)
create mode 100755 Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/build_fpga_clean.scr
rename Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/{pz104 => pynq_z2}/jupyter_notebooks/soclabs/driver/uartlite.py (100%)
rename Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/{pz2 => pynq_z2}/jupyter_notebooks/soclabs/soclabs_cm0sdk_mcu.ipynb (100%)
rename Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/{pz2 => pynq_zcu104}/jupyter_notebooks/soclabs/driver/uartlite.py (100%)
rename Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/{pz104 => pynq_zcu104}/jupyter_notebooks/soclabs/soclabs_cm0sdk_mcu.ipynb (100%)
create mode 100755 fpgabuild.sh
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/build_fpga_clean.scr b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/build_fpga_clean.scr
new file mode 100755
index 0000000..f5878e2
--- /dev/null
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/build_fpga_clean.scr
@@ -0,0 +1,23 @@
+#-----------------------------------------------------------------------------
+# SoC Labs Simulation script for system level verification
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# David Fltnn (d.w.flynne@soton.ac.uk)
+#
+# Copyright 2023, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+#!/usr/bin/env bash
+
+rm -Rf .gen/
+rm -Rf .srcs/
+rm -Rf .Xil/
+rm -Rf vivado/
+rm -f *.backup.*
+rm -f vivado.*
+rm -Rf vivado/
+rm -Rf pynq_export/*/pynq/overlays/soclabs/*
+
+
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/pz104/jupyter_notebooks/soclabs/driver/uartlite.py b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/pynq_z2/jupyter_notebooks/soclabs/driver/uartlite.py
similarity index 100%
rename from Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/pz104/jupyter_notebooks/soclabs/driver/uartlite.py
rename to Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/pynq_z2/jupyter_notebooks/soclabs/driver/uartlite.py
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/pz2/jupyter_notebooks/soclabs/soclabs_cm0sdk_mcu.ipynb b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/pynq_z2/jupyter_notebooks/soclabs/soclabs_cm0sdk_mcu.ipynb
similarity index 100%
rename from Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/pz2/jupyter_notebooks/soclabs/soclabs_cm0sdk_mcu.ipynb
rename to Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/pynq_z2/jupyter_notebooks/soclabs/soclabs_cm0sdk_mcu.ipynb
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/pz2/jupyter_notebooks/soclabs/driver/uartlite.py b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/pynq_zcu104/jupyter_notebooks/soclabs/driver/uartlite.py
similarity index 100%
rename from Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/pz2/jupyter_notebooks/soclabs/driver/uartlite.py
rename to Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/pynq_zcu104/jupyter_notebooks/soclabs/driver/uartlite.py
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/pz104/jupyter_notebooks/soclabs/soclabs_cm0sdk_mcu.ipynb b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/pynq_zcu104/jupyter_notebooks/soclabs/soclabs_cm0sdk_mcu.ipynb
similarity index 100%
rename from Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/pz104/jupyter_notebooks/soclabs/soclabs_cm0sdk_mcu.ipynb
rename to Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/pynq_zcu104/jupyter_notebooks/soclabs/soclabs_cm0sdk_mcu.ipynb
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_ip.tcl b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_ip.tcl
index b612592..07511ba 100644
--- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_ip.tcl
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_ip.tcl
@@ -27,7 +27,7 @@ file mkdir $outputDir
# local search path for configurations
set search_path ../verilog
-set cortexm0_vlog ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical
+set cortexm0_vlog ../../../../../../arm-AAA-ip/latest/Cortex-M0/logical
source scripts/rtl_source_cm0.tcl
set search_path [ concat $search_path $cortexm0_vlog/cortexm0_integration/verilog ]
@@ -35,7 +35,7 @@ read_verilog [ glob $cortexm0_vlog/cortexm0_integration/verilog/*.v ]
read_verilog [ glob $cortexm0_vlog/models/cells/*.v ]
# Arm unmodified CMSDK RTL
-set cmsdk_vlog ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0
+set cmsdk_vlog ../../../../../../arm-AAA-ip/latest/Corstone-101
source scripts/rtl_source_cmsdk.tcl
set search_path [ concat $search_path $cmsdk_vlog/logical/models/memories ]
@@ -47,7 +47,7 @@ read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_fpga_sram.v
# configured Arm DMA-PL230 RTL (include ../verilog/pl230_defs.v for local configuration, not the distribution, already on search path)
##set search_path [ concat $search_path ../verilog ]
-set dma230_vlog ../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog
+set dma230_vlog ../../../../../../arm-AAA-ip/latest/DMA-230/logical
source scripts/rtl_source_dma230.tcl
# ADP, FT1248 and streamio IP
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_pynq_z2.tcl b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_pynq_z2.tcl
index 450ae3c..138c3e3 100644
--- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_pynq_z2.tcl
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_pynq_z2.tcl
@@ -21,8 +21,8 @@ set project project_pynq_z2
set importDir target_fpga_pynq_z2
set ipDir ./ip_repo
set mcuDir ./vivado/built_mcu_fpga/MCULIB
-set pynqDir pynq_export/pz2/pynq/overlays/soclabs
-set exportDir /research/soclabs/pynq_export/pz2/pynq/overlays/soclabs
+set pynqDir pynq_export/pynq_z2/pynq/overlays/soclabs
+set exportDir /research/soclabs/pynq_export/pynq_z2/pynq/overlays/soclabs
#set_property BOARD_PART tul.com:pynq-z2:part0:1.1 [current_project]
#
@@ -66,15 +66,15 @@ create_root_design ""
add_files -norecurse -scan_for_includes ../verilog/cmsdk_mcu_defs.v
set_property is_global_include true [get_files ../verilog/cmsdk_mcu_defs.v]
-add_files -norecurse -scan_for_includes {../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/cmsdk_ahb_memory_models_defs.v ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v}
-set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/cmsdk_ahb_memory_models_defs.v]
-set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
-set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
+add_files -norecurse -scan_for_includes {../../../../../../arm-AAA-ip/latest/Corstone-101/logical/models/memories/cmsdk_ahb_memory_models_defs.v ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v}
+set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/models/memories/cmsdk_ahb_memory_models_defs.v]
+set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
+set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
-set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/cmsdk_ahb_memory_models_defs.v]
-set_property file_type {Verilog Header} [get_files ../../../../../../soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_defs.v]
-set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
-set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
+set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/models/memories/cmsdk_ahb_memory_models_defs.v]
+set_property file_type {Verilog Header} [get_files ../verilog/cmsdk_mcu_defs.v]
+set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
+set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
add_files $importDir/fpga_pinmap.xdc
diff --git a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl
index 24311bd..679a6ae 100644
--- a/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl
+++ b/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_pynq_zcu104.tcl
@@ -21,7 +21,7 @@ set project project_pynq_zcu104
set importDir target_fpga_zcu104
set ipDir ./ip_repo
set mcuDir ./vivado/built_mcu_fpga/MCULIB
-set pynqDir pynq_export/pz104/pynq/overlays/soclabs
+set pynqDir pynq_export/pynq_zcu104/pynq/overlays/soclabs
#set_property BOARD_PART xilinx.com:zcu104:part0:1.1 [current_project]
#
@@ -65,15 +65,15 @@ create_root_design ""
add_files -norecurse -scan_for_includes ../verilog/cmsdk_mcu_defs.v
set_property is_global_include true [get_files ../verilog/cmsdk_mcu_defs.v]
-add_files -norecurse -scan_for_includes {../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/cmsdk_ahb_memory_models_defs.v ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v}
-set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/cmsdk_ahb_memory_models_defs.v]
-set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
-set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
+add_files -norecurse -scan_for_includes {../../../../../../arm-AAA-ip/latest/Corstone-101/logical/models/memories/cmsdk_ahb_memory_models_defs.v ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v}
+set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/models/memories/cmsdk_ahb_memory_models_defs.v]
+set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
+set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
-set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/cmsdk_ahb_memory_models_defs.v]
-set_property file_type {Verilog Header} [get_files ../../../../../../soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_defs.v]
-set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
-set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
+set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/models/memories/cmsdk_ahb_memory_models_defs.v]
+set_property file_type {Verilog Header} [get_files ../verilog/cmsdk_mcu_defs.v]
+set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
+set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
add_files $importDir/fpga_pinmap.xdc
diff --git a/fpgabuild.sh b/fpgabuild.sh
new file mode 100755
index 0000000..d69eb21
--- /dev/null
+++ b/fpgabuild.sh
@@ -0,0 +1,34 @@
+#-----------------------------------------------------------------------------
+# SoC Labs Simulation script for system level verification
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# David Fltnn (d.w.flynne@soton.ac.uk)
+#
+# Copyright 2023, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+#!/usr/bin/env bash
+
+# Get simulation name from name of script
+FPGA_NAME="build_fpga_"$1
+
+# Directory to put simulation files
+FPGA_DIR=$SOCLABS_PROJECT_DIR/fpga/$FPGA_NAME
+
+# Create Directory to export fpga files
+mkdir -p $FPGA_DIR
+cd $ARM_CMSDK_MCU_DIR/fpga_imp
+
+# build fpga
+echo "valid targets are:"
+echo " pynq_z2"
+echo " pynq_zcu104"
+echo " clean"
+
+echo ">>"${1}"<<"
+cd $ARM_CMSDK_MCU_DIR/fpga_imp ; source $FPGA_NAME.scr
+if [ ${1} != 'clean' ]; then
+ cp -Rp $ARM_CMSDK_MCU_DIR/fpga_imp/pynq_export/$1/* $FPGA_DIR/
+fi
--
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