Update project for latest AAA PL230 DMA controller - simulation and FPGA implementation

Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/build_mcu_fpga_ip.tcl

@@ -45,6 +45,11 @@ read_verilog  $cmsdk_vlog/logical/models/memories/cmsdk_fpga_rom.v
 read_verilog  $cmsdk_vlog/logical/models/memories/cmsdk_ahb_ram.v
 read_verilog  $cmsdk_vlog/logical/models/memories/cmsdk_fpga_sram.v
 
+# configured Arm DMA-PL230 RTL (include ../verilog/pl230_defs.v for local configuration, not the distribution, already on search path)
+##set search_path [ concat $search_path ../verilog ]
+set dma230_vlog    ../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog
+source scripts/rtl_source_dma230.tcl
+
 # ADP, FT1248 and streamio IP
 source scripts/rtl_source_soclabs_ip.tcl
 

Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/rtl_source_cmsdk.tcl

@@ -16,3 +16,12 @@ read_verilog  [ glob $cmsdk_vlog/logical/cmsdk_ahb_bitband/verilog/*.v ]
 read_verilog  [ glob $cmsdk_vlog/logical/cmsdk_ahb_master_mux/verilog/*.v ]
 read_verilog  $cmsdk_vlog/logical/models/clkgate/cmsdk_clock_gate.v
 read_verilog  $cmsdk_vlog/logical/cmsdk_ahb_to_sram/verilog/cmsdk_ahb_to_sram.v
+
+set search_path [ concat $search_path ../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog ]
+read_verilog  ../verilog/pl230_defs.v
+read_verilog ../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_ahb_ctrl.v
+read_verilog ../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_apb_regs.v
+read_verilog ../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_dma_data.v
+read_verilog ../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_udma.v
+read_verilog ../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_undefs.v
+

Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/scripts/rtl_source_dma230.tcl

+### DMA PL230 rtl source build
+read_verilog  ../verilog/pl230_defs.v
+read_verilog $dma230_vlog/pl230_ahb_ctrl.v
+read_verilog $dma230_vlog/pl230_apb_regs.v
+read_verilog $dma230_vlog/pl230_dma_data.v
+read_verilog $dma230_vlog/pl230_udma.v
+read_verilog $dma230_vlog/pl230_undefs.v
+

Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_chip_pads.v

@@ -179,9 +179,11 @@ module cmsdk_mcu_chip_pads (
 
 `ifdef ARM_CMSDK_INCLUDE_DMA
   parameter INCLUDE_DMA = 1; // Include instantiation of DMA-230
+  parameter DMA_CHANNEL_NUM = 1;
   // This option also add a number of bus components
 `else
   parameter INCLUDE_DMA = 0;
+  parameter DMA_CHANNEL_NUM = 1;
 `endif
 
 `ifdef ARM_CMSDK_INCLUDE_JTAG

Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/cmsdk_mcu_system.v

@@ -700,7 +700,7 @@ u_cortexm0_ds
 
   cmsdk_ahb_master_mux #(
     .PORT0_ENABLE (1),
-    .PORT1_ENABLE (1),
+    .PORT1_ENABLE (INCLUDE_DMA),
     .PORT2_ENABLE (1),
     .DW           (32)
     )
@@ -772,7 +772,7 @@ u_cortexm0_ds
     .HRDATAM      (sys_hrdata[31:0])
   );
 
-  assign sys_hmaster = (sys_hmaster_i==2'b10); // 2'b00 (core) or 2'b10 (dma)
+  assign sys_hmaster = (sys_hmaster_i==2'b01); // 2'b00 (core) or 2'b10 (dma)
   // This signal is currently not used, but if the customer need to extend the subsystem, this signal may
   // be needed
 

Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/tbench_M0.vc

@@ -87,15 +87,14 @@
 
 
 //// Optional PL230 Micro DMA controller - configure in local ../verilog/pl230_defs.v file
-//-y ../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog
-+incdir+../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog
+/// upgrade to AAA 'rel2' version
++incdir+../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog
 ../verilog/pl230_defs.v
-../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog/pl230_ahb_ctrl.v
-../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog/pl230_apb_regs.v
-../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog/pl230_dma_data.v
-../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog/pl230_udma.v
-../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog/pl230_undefs.v
-
+../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_ahb_ctrl.v
+../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_apb_regs.v
+../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_dma_data.v
+../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_udma.v
+../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_undefs.v
 
 ../../../../../IPLIB/FT1248_streamio_v1_0/ft1248_streamio_v1_0.v
 ../../../../../IPLIB/ADPcontrol_v1_0/ADPcontrol_v1_0.v

Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/verilog/v2html_M0.vc

@@ -92,15 +92,15 @@
 +incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog
 +incdir+../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/models/memories/
 
-//  //// Optional PL230 Micro DMA controller - configure in local ../verilog/pl230_defs.v file
-//  //-y ../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog
-//  +incdir+../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog
-//  ../verilog/pl230_defs.v
-//  ../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog/pl230_ahb_ctrl.v
-//  ../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog/pl230_apb_regs.v
-//  ../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog/pl230_dma_data.v
-//  ../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog/pl230_udma.v
-//  ../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel1/verilog/pl230_undefs.v
+//// Optional PL230 Micro DMA controller - configure in local ../verilog/pl230_defs.v file
+/// upgrade to AAA 'rel2' version
++incdir+../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog
+../verilog/pl230_defs.v
+../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_ahb_ctrl.v
+../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_apb_regs.v
+../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_dma_data.v
+../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_udma.v
+../../../../../../arm-AAA-ip/DMA-230_MicroDMA_Controller/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog/pl230_undefs.v
 
 // ============= Cortex-M0 Module search path =============
 // guts of core not exposed, periphery only