ddda4a64c07b133b6d60c539ac403fb6644bb55f to 28d17f2aa58ecf27e8168e8c5874457caaf29f4f · SoCLabs / ASIC Library Tech

flist/asic_lib_ip.flist

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//-----------------------------------------------------------------------------

// FPGA Library Memory Filelist

// ASIC Library Memory Filelist

// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.

//

// Contributors

@@ -9,7 +9,7 @@

// Copyright � 2021-3, SoC Labs (www.soclabs.org)

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

// Abstract : Verilog Command File for NanoSoC Testbench

// Abstract : Verilog Command File for ASIC Memories

//-----------------------------------------------------------------------------

// ============= Verilog library extensions ===========

@@ -18,15 +18,9 @@

// =============    NanoSoC Testbench search path    =============

// +incdir+$(SOCLABS_ASIC_LIB_TECH_DIR)/sram/verilog/

// - Top-level testbench

// - Memories

$(SOCLABS_ASIC_LIB_TECH_DIR)/sram/verilog/sl_ahb_sram.v

$(SOCLABS_ASIC_LIB_TECH_DIR)/sram/verilog/sl_sram.v

$(SOCLABS_ASIC_LIB_TECH_DIR)/rom/verilog/bootrom.v

$(SOCLABS_ASIC_LIB_TECH_DIR)/pads/verilog/PAD_INOUT8MA_NOE.v

$(SOCLABS_ASIC_LIB_TECH_DIR)/pads/verilog/PAD_VDDIO.v

$(SOCLABS_ASIC_LIB_TECH_DIR)/pads/verilog/PAD_VSSIO.v

$(SOCLABS_ASIC_LIB_TECH_DIR)/pads/verilog/PAD_VDDSOC.v

$(SOCLABS_ASIC_LIB_TECH_DIR)/pads/verilog/PAD_VSS.v

$(SOCLABS_ASIC_LIB_TECH_DIR)/sync/verilog/SYNCHRONIZER_EDGES.v

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flist/asic_lib_ip_TSMC28nm.flist0 → 100644

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//-----------------------------------------------------------------------------

// ASIC Library Memory Filelist

// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.

//

// Contributors

//

// Daniel Newbrook (d.newbrook@soton.ac.uk)

//

// Copyright � 2021-3, SoC Labs (www.soclabs.org)

//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------

// Abstract : Verilog Command File for NanoSoC Testbench

//-----------------------------------------------------------------------------

// ============= Verilog library extensions ===========

+libext+.v+.vlib

// =============    NanoSoC Testbench search path    =============

// +incdir+$(SOCLABS_ASIC_LIB_TECH_DIR)/sram/verilog/

// - Memories

$(SOCLABS_ASIC_LIB_TECH_DIR)/sram/verilog/sl_ahb_sram.v

$(SOCLABS_ASIC_LIB_TECH_DIR)/sram/TSMC28nm/verilog/sl_sram.v

$(SOCLABS_ASIC_LIB_TECH_DIR)/rom/verilog/bootrom.v

$(SOCLABS_ASIC_LIB_TECH_DIR)/sync/verilog/SYNCHRONIZER_EDGES.v

 No newline at end of file

sram/TSMC28nm/verilog/sl_sram.v0 → 100644

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//-----------------------------------------------------------------------------

// SoCLabs ASIC RAM Wrapper 

// - substituted using the same name from the FPGA tech library

// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.

//

// Contributors

//

// David Flynn (d.flynn@soton.ac.uk)

//

// Copyright 2021-3, SoC Labs (www.soclabs.org)

//-----------------------------------------------------------------------------

module sl_sram #(

// --------------------------------------------------------------------------

// Parameter Declarations

// --------------------------------------------------------------------------

  parameter AW = 16

 )

 (

  `ifdef POWER_PINS

  inout  wire          VDD,

  inout  wire          VSS,

  `endif

  // Inputs

  input  wire          CLK,

  input  wire [AW-1:2] ADDR,

  input  wire [31:0]   WDATA,

  input  wire [3:0]    WREN,

  input  wire          CS,

  // Outputs

  output wire [31:0]   RDATA

  );

// fixed pre-compiled 16K instance supported

localparam  TIE_EMA = 3'b010;

localparam  TIE_EMAW = 2'b00;

wire [AW-3:0] ADDR12 = ADDR;

wire [31:0] WDATA32 = WDATA;

wire [31:0] RDATA32;

assign      RDATA = RDATA32;

wire        CEN = !CS;

wire        GWEN = &(~WREN);

wire [31:0] WEN32 = { {8{!WREN[3]}},{8{!WREN[2]}},{8{!WREN[1]}},{8{!WREN[0]}} };

localparam  TIE_RET1N = 1'b1;

generate

  if (AW==14) begin

     sram_16k

      u_sram (

  `ifdef POWER_PINS

      .VDD (VDD),

      .VSS  (VSS),

  `endif

      .Q     (RDATA32),

      .CLK   (CLK),

      .CEN   (CEN),

      .WEN   (WEN32),

      .A     (ADDR12),

      .D     (WDATA32),

      .EMA   (TIE_EMA),

      .EMAW  (TIE_EMAW),

      .GWEN  (GWEN),

      .RET1N (TIE_RET1N)

    );

  end

  else if (AW==15) begin

     sram_32k

      u_sram (

  `ifdef POWER_PINS

      .VDD (VDD),

      .VSS  (VSS),

  `endif

      .Q     (RDATA32),

      .CLK   (CLK),

      .CEN   (CEN),

      .WEN   (WEN32),

      .A     (ADDR12),

      .D     (WDATA32),

      .EMA   (TIE_EMA),

      .EMAW  (TIE_EMAW),

      .GWEN  (GWEN),

      .RET1N (TIE_RET1N)

    );

  end

endgenerate

endmodule

sram/verilog/sl_ahb_sram.v

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@@ -74,7 +74,7 @@ module sl_ahb_sram #(

        .SRAMCS     (cs)

   );

    // FPGA SRAM model

    // ASIC SRAM model

    sl_sram #(

        .AW (RAM_ADDR_W)

    ) u_sram (

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Commits on Source 1

Files

flist/asic_lib_ip.flist

flist/asic_lib_ip_TSMC28nm.flist

sram/TSMC28nm/verilog/sl_sram.v

sram/verilog/sl_ahb_sram.v