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SoCLabs
ASIC Library Tech
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28d17f2aa58ecf27e8168e8c5874457caaf29f4f
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Created with Raphaël 2.2.0
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Jul
Fix tie offs in TSMC 28nm sram instantiation
main
main
Add TSMC 16nm SRAM wrapper
update pad model for ASIC with no technology pads
Initial update for 65nm and 28nm flows
Fix bootrom enable active level
Fix TSMC rom_via EMA tie off
Fix clock connection
Add 16K and 8K options for SRAM
invert GWEN and WEN signalling for Arm RegFiles
Add Pad files to override generic_lib
Added bootrom
Add Power Pins
Add ROM
Initial commit
Initial commit
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