Update TSMC28nm SRAM tie offs

sram/TSMC28nm/verilog/sl_sram.v

@@ -33,7 +33,7 @@ module sl_sram #(
   );
 
 // fixed pre-compiled 16K instance supported
-localparam  TIE_EMA = 3'b010;
+localparam  TIE_EMA = 3'b011;
 localparam  TIE_EMAW = 2'b00;
 wire [AW-3:0] ADDR12 = ADDR;
 wire [31:0] WDATA32 = WDATA;
@@ -64,7 +64,7 @@ generate
       .RET1N (TIE_RET1N),
       .EMAS  (1'b0),
       .STOV  (1'b0),
-      .WABL  (1'b1),
+      .WABL  (1'b0),
       .WABLM (2'b00)
     );
 
@@ -88,7 +88,7 @@ generate
       .RET1N (TIE_RET1N),
       .EMAS  (1'b0),
       .STOV  (1'b0),
-      .WABL  (1'b1),
+      .WABL  (1'b0),
       .WABLM (2'b00)
     );
   end